2 * linux/arch/arm/mach-pxa/irq.c
4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
19 #include <asm/hardware.h>
21 #include <asm/mach/irq.h>
22 #include <asm/arch/pxa-regs.h>
28 * This is for peripheral IRQs internal to the PXA chip.
31 static void pxa_mask_low_irq(unsigned int irq
)
36 static void pxa_unmask_low_irq(unsigned int irq
)
41 static int pxa_set_wake(unsigned int irq
, unsigned int on
)
50 /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
62 static struct irq_chip pxa_internal_chip_low
= {
64 .ack
= pxa_mask_low_irq
,
65 .mask
= pxa_mask_low_irq
,
66 .unmask
= pxa_unmask_low_irq
,
67 .set_wake
= pxa_set_wake
,
73 * This is for the second set of internal IRQs as found on the PXA27x.
76 static void pxa_mask_high_irq(unsigned int irq
)
78 ICMR2
&= ~(1 << (irq
- 32));
81 static void pxa_unmask_high_irq(unsigned int irq
)
83 ICMR2
|= (1 << (irq
- 32));
86 static struct irq_chip pxa_internal_chip_high
= {
88 .ack
= pxa_mask_high_irq
,
89 .mask
= pxa_mask_high_irq
,
90 .unmask
= pxa_unmask_high_irq
,
93 void __init
pxa_init_irq_high(void)
100 for (irq
= PXA_IRQ(32); irq
< PXA_IRQ(64); irq
++) {
101 set_irq_chip(irq
, &pxa_internal_chip_high
);
102 set_irq_handler(irq
, handle_level_irq
);
103 set_irq_flags(irq
, IRQF_VALID
);
108 /* Note that if an input/irq line ever gets changed to an output during
109 * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
113 /* PXA27x: Various gpios can issue wakeup events. This logic only
114 * handles the simple cases, not the WEMUX2 and WEMUX3 options
116 #define PXA27x_GPIO_NOWAKE_MASK \
117 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
118 #define WAKEMASK(gpio) \
120 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
121 : ((gpio == 35) ? (1 << 24) : 0))
124 /* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */
125 #define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
129 * PXA GPIO edge detection for IRQs:
130 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
131 * Use this instead of directly setting GRER/GFER.
134 static long GPIO_IRQ_rising_edge
[4];
135 static long GPIO_IRQ_falling_edge
[4];
136 static long GPIO_IRQ_mask
[4];
138 static int pxa_gpio_irq_type(unsigned int irq
, unsigned int type
)
143 gpio
= IRQ_TO_GPIO(irq
);
145 mask
= WAKEMASK(gpio
);
147 if (type
== IRQT_PROBE
) {
148 /* Don't mess with enabled GPIOs using preconfigured edges or
149 GPIOs set to alternate function or to output during probe */
150 if ((GPIO_IRQ_rising_edge
[idx
] | GPIO_IRQ_falling_edge
[idx
] | GPDR(gpio
)) &
153 if (GAFR(gpio
) & (0x3 << (((gpio
) & 0xf)*2)))
155 type
= __IRQT_RISEDGE
| __IRQT_FALEDGE
;
158 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
160 pxa_gpio_mode(gpio
| GPIO_IN
);
162 if (type
& __IRQT_RISEDGE
) {
163 /* printk("rising "); */
164 __set_bit (gpio
, GPIO_IRQ_rising_edge
);
167 __clear_bit (gpio
, GPIO_IRQ_rising_edge
);
171 if (type
& __IRQT_FALEDGE
) {
172 /* printk("falling "); */
173 __set_bit (gpio
, GPIO_IRQ_falling_edge
);
176 __clear_bit (gpio
, GPIO_IRQ_falling_edge
);
180 /* printk("edges\n"); */
182 GRER(gpio
) = GPIO_IRQ_rising_edge
[idx
] & GPIO_IRQ_mask
[idx
];
183 GFER(gpio
) = GPIO_IRQ_falling_edge
[idx
] & GPIO_IRQ_mask
[idx
];
188 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
191 static void pxa_ack_low_gpio(unsigned int irq
)
193 GEDR0
= (1 << (irq
- IRQ_GPIO0
));
196 static int pxa_set_gpio_wake(unsigned int irq
, unsigned int on
)
198 int gpio
= IRQ_TO_GPIO(irq
);
199 u32 mask
= WAKEMASK(gpio
);
212 static struct irq_chip pxa_low_gpio_chip
= {
214 .ack
= pxa_ack_low_gpio
,
215 .mask
= pxa_mask_low_irq
,
216 .unmask
= pxa_unmask_low_irq
,
217 .set_type
= pxa_gpio_irq_type
,
218 .set_wake
= pxa_set_gpio_wake
,
222 * Demux handler for GPIO>=2 edge detect interrupts
225 static void pxa_gpio_demux_handler(unsigned int irq
, struct irq_desc
*desc
)
237 desc
= irq_desc
+ irq
;
241 desc_handle_irq(irq
, desc
);
253 desc
= irq_desc
+ irq
;
256 desc_handle_irq(irq
, desc
);
268 desc
= irq_desc
+ irq
;
271 desc_handle_irq(irq
, desc
);
279 #if PXA_LAST_GPIO >= 96
284 desc
= irq_desc
+ irq
;
287 desc_handle_irq(irq
, desc
);
298 static void pxa_ack_muxed_gpio(unsigned int irq
)
300 int gpio
= irq
- IRQ_GPIO(2) + 2;
301 GEDR(gpio
) = GPIO_bit(gpio
);
304 static void pxa_mask_muxed_gpio(unsigned int irq
)
306 int gpio
= irq
- IRQ_GPIO(2) + 2;
307 __clear_bit(gpio
, GPIO_IRQ_mask
);
308 GRER(gpio
) &= ~GPIO_bit(gpio
);
309 GFER(gpio
) &= ~GPIO_bit(gpio
);
312 static void pxa_unmask_muxed_gpio(unsigned int irq
)
314 int gpio
= irq
- IRQ_GPIO(2) + 2;
316 __set_bit(gpio
, GPIO_IRQ_mask
);
317 GRER(gpio
) = GPIO_IRQ_rising_edge
[idx
] & GPIO_IRQ_mask
[idx
];
318 GFER(gpio
) = GPIO_IRQ_falling_edge
[idx
] & GPIO_IRQ_mask
[idx
];
321 static struct irq_chip pxa_muxed_gpio_chip
= {
323 .ack
= pxa_ack_muxed_gpio
,
324 .mask
= pxa_mask_muxed_gpio
,
325 .unmask
= pxa_unmask_muxed_gpio
,
326 .set_type
= pxa_gpio_irq_type
,
327 .set_wake
= pxa_set_gpio_wake
,
330 void __init
pxa_init_irq(void)
334 /* disable all IRQs */
337 /* all IRQs are IRQ, not FIQ */
340 /* clear all GPIO edge detects */
352 /* And similarly for the extra regs on the PXA27x */
358 /* only unmasked interrupts kick us out of idle */
361 /* GPIO 0 and 1 must have their mask bit always set */
362 GPIO_IRQ_mask
[0] = 3;
364 for (irq
= PXA_IRQ(0); irq
<= PXA_IRQ(31); irq
++) {
365 set_irq_chip(irq
, &pxa_internal_chip_low
);
366 set_irq_handler(irq
, handle_level_irq
);
367 set_irq_flags(irq
, IRQF_VALID
);
374 for (irq
= IRQ_GPIO0
; irq
<= IRQ_GPIO1
; irq
++) {
375 set_irq_chip(irq
, &pxa_low_gpio_chip
);
376 set_irq_handler(irq
, handle_edge_irq
);
377 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
380 for (irq
= IRQ_GPIO(2); irq
<= IRQ_GPIO(PXA_LAST_GPIO
); irq
++) {
381 set_irq_chip(irq
, &pxa_muxed_gpio_chip
);
382 set_irq_handler(irq
, handle_edge_irq
);
383 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
386 /* Install handler for GPIO>=2 edge detect interrupts */
387 set_irq_chip(IRQ_GPIO_2_x
, &pxa_internal_chip_low
);
388 set_irq_chained_handler(IRQ_GPIO_2_x
, pxa_gpio_demux_handler
);