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[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-pxa / pxa27x.c
1 /*
2 * linux/arch/arm/mach-pxa/pxa27x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA27x aka Bulverde.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14 #include <linux/dmaengine.h>
15 #include <linux/dma/pxa-dma.h>
16 #include <linux/gpio.h>
17 #include <linux/gpio-pxa.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/irqchip.h>
22 #include <linux/suspend.h>
23 #include <linux/platform_device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/io.h>
26 #include <linux/irq.h>
27 #include <linux/platform_data/i2c-pxa.h>
28 #include <linux/platform_data/mmp_dma.h>
29
30 #include <asm/mach/map.h>
31 #include <mach/hardware.h>
32 #include <asm/irq.h>
33 #include <asm/suspend.h>
34 #include <mach/irqs.h>
35 #include "pxa27x.h"
36 #include <mach/reset.h>
37 #include <linux/platform_data/usb-ohci-pxa27x.h>
38 #include "pm.h"
39 #include <mach/dma.h>
40 #include <mach/smemc.h>
41
42 #include "generic.h"
43 #include "devices.h"
44 #include <linux/clk-provider.h>
45 #include <linux/clkdev.h>
46
47 void pxa27x_clear_otgph(void)
48 {
49 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
50 PSSR |= PSSR_OTGPH;
51 }
52 EXPORT_SYMBOL(pxa27x_clear_otgph);
53
54 static unsigned long ac97_reset_config[] = {
55 GPIO113_AC97_nRESET_GPIO_HIGH,
56 GPIO113_AC97_nRESET,
57 GPIO95_AC97_nRESET_GPIO_HIGH,
58 GPIO95_AC97_nRESET,
59 };
60
61 void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
62 {
63 /*
64 * This helper function is used to work around a bug in the pxa27x's
65 * ac97 controller during a warm reset. The configuration of the
66 * reset_gpio is changed as follows:
67 * to_gpio == true: configured to generic output gpio and driven high
68 * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
69 */
70
71 if (reset_gpio == 113)
72 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
73 &ac97_reset_config[1], 1);
74
75 if (reset_gpio == 95)
76 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
77 &ac97_reset_config[3], 1);
78 }
79 EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
80
81 #ifdef CONFIG_PM
82
83 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
84 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
85
86 /*
87 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
88 */
89 static unsigned int pwrmode = PWRMODE_SLEEP;
90
91 int pxa27x_set_pwrmode(unsigned int mode)
92 {
93 switch (mode) {
94 case PWRMODE_SLEEP:
95 case PWRMODE_DEEPSLEEP:
96 pwrmode = mode;
97 return 0;
98 }
99
100 return -EINVAL;
101 }
102
103 /*
104 * List of global PXA peripheral registers to preserve.
105 * More ones like CP and general purpose register values are preserved
106 * with the stack pointer in sleep.S.
107 */
108 enum {
109 SLEEP_SAVE_PSTR,
110 SLEEP_SAVE_MDREFR,
111 SLEEP_SAVE_PCFR,
112 SLEEP_SAVE_COUNT
113 };
114
115 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
116 {
117 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
118 SAVE(PCFR);
119
120 SAVE(PSTR);
121 }
122
123 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
124 {
125 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
126 RESTORE(PCFR);
127
128 PSSR = PSSR_RDH | PSSR_PH;
129
130 RESTORE(PSTR);
131 }
132
133 void pxa27x_cpu_pm_enter(suspend_state_t state)
134 {
135 extern void pxa_cpu_standby(void);
136 #ifndef CONFIG_IWMMXT
137 u64 acc0;
138
139 asm volatile(".arch_extension xscale\n\t"
140 "mra %Q0, %R0, acc0" : "=r" (acc0));
141 #endif
142
143 /* ensure voltage-change sequencer not initiated, which hangs */
144 PCFR &= ~PCFR_FVC;
145
146 /* Clear edge-detect status register. */
147 PEDR = 0xDF12FE1B;
148
149 /* Clear reset status */
150 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
151
152 switch (state) {
153 case PM_SUSPEND_STANDBY:
154 pxa_cpu_standby();
155 break;
156 case PM_SUSPEND_MEM:
157 cpu_suspend(pwrmode, pxa27x_finish_suspend);
158 #ifndef CONFIG_IWMMXT
159 asm volatile(".arch_extension xscale\n\t"
160 "mar acc0, %Q0, %R0" : "=r" (acc0));
161 #endif
162 break;
163 }
164 }
165
166 static int pxa27x_cpu_pm_valid(suspend_state_t state)
167 {
168 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
169 }
170
171 static int pxa27x_cpu_pm_prepare(void)
172 {
173 /* set resume return address */
174 PSPR = __pa_symbol(cpu_resume);
175 return 0;
176 }
177
178 static void pxa27x_cpu_pm_finish(void)
179 {
180 /* ensure not to come back here if it wasn't intended */
181 PSPR = 0;
182 }
183
184 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
185 .save_count = SLEEP_SAVE_COUNT,
186 .save = pxa27x_cpu_pm_save,
187 .restore = pxa27x_cpu_pm_restore,
188 .valid = pxa27x_cpu_pm_valid,
189 .enter = pxa27x_cpu_pm_enter,
190 .prepare = pxa27x_cpu_pm_prepare,
191 .finish = pxa27x_cpu_pm_finish,
192 };
193
194 static void __init pxa27x_init_pm(void)
195 {
196 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
197 }
198 #else
199 static inline void pxa27x_init_pm(void) {}
200 #endif
201
202 /* PXA27x: Various gpios can issue wakeup events. This logic only
203 * handles the simple cases, not the WEMUX2 and WEMUX3 options
204 */
205 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
206 {
207 int gpio = pxa_irq_to_gpio(d->irq);
208 uint32_t mask;
209
210 if (gpio >= 0 && gpio < 128)
211 return gpio_set_wake(gpio, on);
212
213 if (d->irq == IRQ_KEYPAD)
214 return keypad_set_wake(on);
215
216 switch (d->irq) {
217 case IRQ_RTCAlrm:
218 mask = PWER_RTC;
219 break;
220 case IRQ_USB:
221 mask = 1u << 26;
222 break;
223 default:
224 return -EINVAL;
225 }
226
227 if (on)
228 PWER |= mask;
229 else
230 PWER &=~mask;
231
232 return 0;
233 }
234
235 void __init pxa27x_init_irq(void)
236 {
237 pxa_init_irq(34, pxa27x_set_wake);
238 }
239
240 static int __init
241 pxa27x_dt_init_irq(struct device_node *node, struct device_node *parent)
242 {
243 pxa_dt_irq_init(pxa27x_set_wake);
244 set_handle_irq(ichp_handle_irq);
245
246 return 0;
247 }
248 IRQCHIP_DECLARE(pxa27x_intc, "marvell,pxa-intc", pxa27x_dt_init_irq);
249
250 static struct map_desc pxa27x_io_desc[] __initdata = {
251 { /* Mem Ctl */
252 .virtual = (unsigned long)SMEMC_VIRT,
253 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
254 .length = SMEMC_SIZE,
255 .type = MT_DEVICE
256 }, { /* UNCACHED_PHYS_0 */
257 .virtual = UNCACHED_PHYS_0,
258 .pfn = __phys_to_pfn(0x00000000),
259 .length = UNCACHED_PHYS_0_SIZE,
260 .type = MT_DEVICE
261 },
262 };
263
264 void __init pxa27x_map_io(void)
265 {
266 pxa_map_io();
267 iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
268 pxa27x_get_clk_frequency_khz(1);
269 }
270
271 /*
272 * device registration specific to PXA27x.
273 */
274 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
275 {
276 local_irq_disable();
277 PCFR |= PCFR_PI2CEN;
278 local_irq_enable();
279 pxa_register_device(&pxa27x_device_i2c_power, info);
280 }
281
282 static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
283 .irq_base = PXA_GPIO_TO_IRQ(0),
284 .gpio_set_wake = gpio_set_wake,
285 };
286
287 static struct platform_device *devices[] __initdata = {
288 &pxa27x_device_udc,
289 &pxa_device_pmu,
290 &pxa_device_i2s,
291 &pxa_device_asoc_ssp1,
292 &pxa_device_asoc_ssp2,
293 &pxa_device_asoc_ssp3,
294 &pxa_device_asoc_platform,
295 &pxa_device_rtc,
296 &pxa27x_device_ssp1,
297 &pxa27x_device_ssp2,
298 &pxa27x_device_ssp3,
299 &pxa27x_device_pwm0,
300 &pxa27x_device_pwm1,
301 };
302
303 static const struct dma_slave_map pxa27x_slave_map[] = {
304 /* PXA25x, PXA27x and PXA3xx common entries */
305 { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
306 { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
307 { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
308 PDMA_FILTER_PARAM(LOWEST, 10) },
309 { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
310 { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
311 { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
312 { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
313 { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
314 { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
315 { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
316 { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
317 { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
318 { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
319 { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
320 { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
321
322 /* PXA27x specific map */
323 { "pxa2xx-i2s", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
324 { "pxa2xx-i2s", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
325 { "pxa27x-camera.0", "CI_Y", PDMA_FILTER_PARAM(HIGHEST, 68) },
326 { "pxa27x-camera.0", "CI_U", PDMA_FILTER_PARAM(HIGHEST, 69) },
327 { "pxa27x-camera.0", "CI_V", PDMA_FILTER_PARAM(HIGHEST, 70) },
328 };
329
330 static struct mmp_dma_platdata pxa27x_dma_pdata = {
331 .dma_channels = 32,
332 .nb_requestors = 75,
333 .slave_map = pxa27x_slave_map,
334 .slave_map_cnt = ARRAY_SIZE(pxa27x_slave_map),
335 };
336
337 static int __init pxa27x_init(void)
338 {
339 int ret = 0;
340
341 if (cpu_is_pxa27x()) {
342
343 reset_status = RCSR;
344
345 pxa27x_init_pm();
346
347 register_syscore_ops(&pxa_irq_syscore_ops);
348 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
349
350 if (!of_have_populated_dt()) {
351 pxa_register_device(&pxa27x_device_gpio,
352 &pxa27x_gpio_info);
353 pxa2xx_set_dmac_info(&pxa27x_dma_pdata);
354 ret = platform_add_devices(devices,
355 ARRAY_SIZE(devices));
356 }
357 }
358
359 return ret;
360 }
361
362 postcore_initcall(pxa27x_init);