2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
23 #include <linux/sysdev.h>
25 #include <asm/arch/hardware.h>
26 #include <asm/arch/pxa3xx-regs.h>
27 #include <asm/arch/ohci.h>
28 #include <asm/arch/pm.h>
29 #include <asm/arch/dma.h>
30 #include <asm/arch/ssp.h>
36 /* Crystal clock: 13MHz */
37 #define BASE_CLK 13000000
39 /* Ring Oscillator Clock: 60MHz */
40 #define RO_CLK 60000000
42 #define ACCR_D0CS (1 << 26)
43 #define ACCR_PCCE (1 << 11)
45 /* crystal frequency to static memory controller multiplier (SMCFS) */
46 static unsigned char smcfs_mult
[8] = { 6, 0, 8, 0, 0, 16, };
48 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
49 static unsigned char hss_mult
[4] = { 8, 12, 16, 0 };
52 * Get the clock frequency as reflected by CCSR and the turbo flag.
53 * We assume these values have been applied via a fcs.
54 * If info is not 0 we also display the current settings.
56 unsigned int pxa3xx_get_clk_frequency_khz(int info
)
58 unsigned long acsr
, xclkcfg
;
59 unsigned int t
, xl
, xn
, hss
, ro
, XL
, XN
, CLK
, HSS
;
61 /* Read XCLKCFG register turbo bit */
62 __asm__
__volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg
));
68 xn
= (acsr
>> 8) & 0x7;
69 hss
= (acsr
>> 14) & 0x3;
74 ro
= acsr
& ACCR_D0CS
;
76 CLK
= (ro
) ? RO_CLK
: ((t
) ? XN
: XL
);
77 HSS
= (ro
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
80 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
81 RO_CLK
/ 1000000, (RO_CLK
% 1000000) / 10000,
83 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
84 XL
/ 1000000, (XL
% 1000000) / 10000, xl
);
85 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
86 XN
/ 1000000, (XN
% 1000000) / 10000, xn
,
88 pr_info("HSIO bus clock: %d.%02dMHz\n",
89 HSS
/ 1000000, (HSS
% 1000000) / 10000);
96 * Return the current static memory controller clock frequency
99 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
102 unsigned int smcfs
, clk
= 0;
106 smcfs
= (acsr
>> 23) & 0x7;
107 clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: smcfs_mult
[smcfs
] * BASE_CLK
;
109 return (clk
/ 10000);
113 * Return the current AC97 clock frequency.
115 static unsigned long clk_pxa3xx_ac97_getrate(struct clk
*clk
)
117 unsigned long rate
= 312000000;
118 unsigned long ac97_div
;
122 /* This may loose precision for some rates but won't for the
123 * standard 24.576MHz.
125 rate
/= (ac97_div
>> 12) & 0x7fff;
126 rate
*= (ac97_div
& 0xfff);
132 * Return the current HSIO bus clock frequency
134 static unsigned long clk_pxa3xx_hsio_getrate(struct clk
*clk
)
137 unsigned int hss
, hsio_clk
;
141 hss
= (acsr
>> 14) & 0x3;
142 hsio_clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
147 void clk_pxa3xx_cken_enable(struct clk
*clk
)
149 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
157 void clk_pxa3xx_cken_disable(struct clk
*clk
)
159 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
167 const struct clkops clk_pxa3xx_cken_ops
= {
168 .enable
= clk_pxa3xx_cken_enable
,
169 .disable
= clk_pxa3xx_cken_disable
,
172 static const struct clkops clk_pxa3xx_hsio_ops
= {
173 .enable
= clk_pxa3xx_cken_enable
,
174 .disable
= clk_pxa3xx_cken_disable
,
175 .getrate
= clk_pxa3xx_hsio_getrate
,
178 static const struct clkops clk_pxa3xx_ac97_ops
= {
179 .enable
= clk_pxa3xx_cken_enable
,
180 .disable
= clk_pxa3xx_cken_disable
,
181 .getrate
= clk_pxa3xx_ac97_getrate
,
184 static void clk_pout_enable(struct clk
*clk
)
189 static void clk_pout_disable(struct clk
*clk
)
194 static const struct clkops clk_pout_ops
= {
195 .enable
= clk_pout_enable
,
196 .disable
= clk_pout_disable
,
199 static struct clk pxa3xx_clks
[] = {
202 .ops
= &clk_pout_ops
,
207 PXA3xx_CK("LCDCLK", LCD
, &clk_pxa3xx_hsio_ops
, &pxa_device_fb
.dev
),
208 PXA3xx_CK("CAMCLK", CAMERA
, &clk_pxa3xx_hsio_ops
, NULL
),
209 PXA3xx_CK("AC97CLK", AC97
, &clk_pxa3xx_ac97_ops
, NULL
),
211 PXA3xx_CKEN("UARTCLK", FFUART
, 14857000, 1, &pxa_device_ffuart
.dev
),
212 PXA3xx_CKEN("UARTCLK", BTUART
, 14857000, 1, &pxa_device_btuart
.dev
),
213 PXA3xx_CKEN("UARTCLK", STUART
, 14857000, 1, NULL
),
215 PXA3xx_CKEN("I2CCLK", I2C
, 32842000, 0, &pxa_device_i2c
.dev
),
216 PXA3xx_CKEN("UDCCLK", UDC
, 48000000, 5, &pxa27x_device_udc
.dev
),
217 PXA3xx_CKEN("USBCLK", USBH
, 48000000, 0, &pxa27x_device_ohci
.dev
),
218 PXA3xx_CKEN("KBDCLK", KEYPAD
, 32768, 0, &pxa27x_device_keypad
.dev
),
220 PXA3xx_CKEN("SSPCLK", SSP1
, 13000000, 0, &pxa27x_device_ssp1
.dev
),
221 PXA3xx_CKEN("SSPCLK", SSP2
, 13000000, 0, &pxa27x_device_ssp2
.dev
),
222 PXA3xx_CKEN("SSPCLK", SSP3
, 13000000, 0, &pxa27x_device_ssp3
.dev
),
223 PXA3xx_CKEN("SSPCLK", SSP4
, 13000000, 0, &pxa3xx_device_ssp4
.dev
),
224 PXA3xx_CKEN("PWMCLK", PWM0
, 13000000, 0, &pxa27x_device_pwm0
.dev
),
225 PXA3xx_CKEN("PWMCLK", PWM1
, 13000000, 0, &pxa27x_device_pwm1
.dev
),
227 PXA3xx_CKEN("MMCCLK", MMC1
, 19500000, 0, &pxa_device_mci
.dev
),
228 PXA3xx_CKEN("MMCCLK", MMC2
, 19500000, 0, &pxa3xx_device_mci2
.dev
),
233 #define ISRAM_START 0x5c000000
234 #define ISRAM_SIZE SZ_256K
236 static void __iomem
*sram
;
237 static unsigned long wakeup_src
;
239 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
240 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
242 enum { SLEEP_SAVE_CKENA
,
249 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save
)
256 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save
)
264 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
265 * memory controller has to be reinitialised, so we place some code
266 * in the SRAM to perform this function.
268 * We disable FIQs across the standby - otherwise, we might receive a
269 * FIQ while the SDRAM is unavailable.
271 static void pxa3xx_cpu_standby(unsigned int pwrmode
)
273 extern const char pm_enter_standby_start
[], pm_enter_standby_end
[];
274 void (*fn
)(unsigned int) = (void __force
*)(sram
+ 0x8000);
276 memcpy_toio(sram
+ 0x8000, pm_enter_standby_start
,
277 pm_enter_standby_end
- pm_enter_standby_start
);
281 AD2D0ER
= wakeup_src
;
295 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
296 * PXA3xx development kits assumes that the resuming process continues
297 * with the address stored within the first 4 bytes of SDRAM. The PSPR
298 * register is used privately by BootROM and OBM, and _must_ be set to
299 * 0x5c014000 for the moment.
301 static void pxa3xx_cpu_pm_suspend(void)
303 volatile unsigned long *p
= (volatile void *)0xc0000000;
304 unsigned long saved_data
= *p
;
306 extern void pxa3xx_cpu_suspend(void);
307 extern void pxa3xx_cpu_resume(void);
309 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
310 CKENA
|= (1 << CKEN_BOOT
) | (1 << CKEN_TPM
);
311 CKENB
|= 1 << (CKEN_HSIO2
& 0x1f);
313 /* clear and setup wakeup source */
319 PCFR
|= (1u << 13); /* L1_DIS */
320 PCFR
&= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
324 /* overwrite with the resume address */
325 *p
= virt_to_phys(pxa3xx_cpu_resume
);
327 pxa3xx_cpu_suspend();
334 static void pxa3xx_cpu_pm_enter(suspend_state_t state
)
337 * Don't sleep if no wakeup sources are defined
339 if (wakeup_src
== 0) {
340 printk(KERN_ERR
"Not suspending: no wakeup sources\n");
345 case PM_SUSPEND_STANDBY
:
346 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2
);
350 pxa3xx_cpu_pm_suspend();
355 static int pxa3xx_cpu_pm_valid(suspend_state_t state
)
357 return state
== PM_SUSPEND_MEM
|| state
== PM_SUSPEND_STANDBY
;
360 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns
= {
361 .save_count
= SLEEP_SAVE_COUNT
,
362 .save
= pxa3xx_cpu_pm_save
,
363 .restore
= pxa3xx_cpu_pm_restore
,
364 .valid
= pxa3xx_cpu_pm_valid
,
365 .enter
= pxa3xx_cpu_pm_enter
,
368 static void __init
pxa3xx_init_pm(void)
370 sram
= ioremap(ISRAM_START
, ISRAM_SIZE
);
372 printk(KERN_ERR
"Unable to map ISRAM: disabling standby/suspend\n");
377 * Since we copy wakeup code into the SRAM, we need to ensure
378 * that it is preserved over the low power modes. Note: bit 8
379 * is undocumented in the developer manual, but must be set.
381 AD1R
|= ADXR_L2
| ADXR_R0
;
382 AD2R
|= ADXR_L2
| ADXR_R0
;
383 AD3R
|= ADXR_L2
| ADXR_R0
;
386 * Clear the resume enable registers.
393 pxa_cpu_pm_fns
= &pxa3xx_cpu_pm_fns
;
396 static int pxa3xx_set_wake(unsigned int irq
, unsigned int on
)
398 unsigned long flags
, mask
= 0;
402 mask
= ADXER_MFP_WSSP3
;
415 mask
= ADXER_MFP_WAC97
;
421 mask
= ADXER_MFP_WSSP2
;
424 mask
= ADXER_MFP_WI2C
;
427 mask
= ADXER_MFP_WUART3
;
430 mask
= ADXER_MFP_WUART2
;
433 mask
= ADXER_MFP_WUART1
;
436 mask
= ADXER_MFP_WMMC1
;
439 mask
= ADXER_MFP_WSSP1
;
445 mask
= ADXER_MFP_WSSP4
;
454 mask
= ADXER_MFP_WMMC2
;
457 mask
= ADXER_MFP_WFLASH
;
463 mask
= ADXER_WEXTWAKE0
;
466 mask
= ADXER_WEXTWAKE1
;
469 mask
= ADXER_MFP_GEN12
;
475 local_irq_save(flags
);
480 local_irq_restore(flags
);
485 static inline void pxa3xx_init_pm(void) {}
486 #define pxa3xx_set_wake NULL
489 void __init
pxa3xx_init_irq(void)
491 /* enable CP6 access */
493 __asm__
__volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value
));
495 __asm__
__volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value
));
497 pxa_init_irq(56, pxa3xx_set_wake
);
498 pxa_init_gpio(128, NULL
);
502 * device registration specific to PXA3xx.
505 static struct platform_device
*devices
[] __initdata
= {
506 /* &pxa_device_udc, The UDC driver is PXA25x only */
520 static struct sys_device pxa3xx_sysdev
[] = {
522 .cls
= &pxa_irq_sysclass
,
524 .cls
= &pxa3xx_mfp_sysclass
,
526 .cls
= &pxa_gpio_sysclass
,
530 static int __init
pxa3xx_init(void)
534 if (cpu_is_pxa3xx()) {
536 * clear RDH bit every time after reset
538 * Note: the last 3 bits DxS are write-1-to-clear so carefully
539 * preserve them here in case they will be referenced later
541 ASCR
&= ~(ASCR_RDH
| ASCR_D1S
| ASCR_D2S
| ASCR_D3S
);
543 clks_register(pxa3xx_clks
, ARRAY_SIZE(pxa3xx_clks
));
545 if ((ret
= pxa_init_dma(32)))
550 for (i
= 0; i
< ARRAY_SIZE(pxa3xx_sysdev
); i
++) {
551 ret
= sysdev_register(&pxa3xx_sysdev
[i
]);
553 pr_err("failed to register sysdev[%d]\n", i
);
556 ret
= platform_add_devices(devices
, ARRAY_SIZE(devices
));
562 postcore_initcall(pxa3xx_init
);