2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/irq.h>
22 #include <linux/syscore_ops.h>
23 #include <linux/i2c/pxa-i2c.h>
25 #include <asm/mach/map.h>
26 #include <asm/suspend.h>
27 #include <mach/hardware.h>
28 #include <mach/pxa3xx-regs.h>
29 #include <mach/reset.h>
30 #include <linux/platform_data/usb-ohci-pxa27x.h>
33 #include <mach/smemc.h>
34 #include <mach/irqs.h>
40 #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
41 #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
43 static DEFINE_PXA3_CKEN(pxa3xx_ffuart
, FFUART
, 14857000, 1);
44 static DEFINE_PXA3_CKEN(pxa3xx_btuart
, BTUART
, 14857000, 1);
45 static DEFINE_PXA3_CKEN(pxa3xx_stuart
, STUART
, 14857000, 1);
46 static DEFINE_PXA3_CKEN(pxa3xx_i2c
, I2C
, 32842000, 0);
47 static DEFINE_PXA3_CKEN(pxa3xx_udc
, UDC
, 48000000, 5);
48 static DEFINE_PXA3_CKEN(pxa3xx_usbh
, USBH
, 48000000, 0);
49 static DEFINE_PXA3_CKEN(pxa3xx_u2d
, USB2
, 48000000, 0);
50 static DEFINE_PXA3_CKEN(pxa3xx_keypad
, KEYPAD
, 32768, 0);
51 static DEFINE_PXA3_CKEN(pxa3xx_ssp1
, SSP1
, 13000000, 0);
52 static DEFINE_PXA3_CKEN(pxa3xx_ssp2
, SSP2
, 13000000, 0);
53 static DEFINE_PXA3_CKEN(pxa3xx_ssp3
, SSP3
, 13000000, 0);
54 static DEFINE_PXA3_CKEN(pxa3xx_ssp4
, SSP4
, 13000000, 0);
55 static DEFINE_PXA3_CKEN(pxa3xx_pwm0
, PWM0
, 13000000, 0);
56 static DEFINE_PXA3_CKEN(pxa3xx_pwm1
, PWM1
, 13000000, 0);
57 static DEFINE_PXA3_CKEN(pxa3xx_mmc1
, MMC1
, 19500000, 0);
58 static DEFINE_PXA3_CKEN(pxa3xx_mmc2
, MMC2
, 19500000, 0);
59 static DEFINE_PXA3_CKEN(pxa3xx_gpio
, GPIO
, 13000000, 0);
61 static DEFINE_CK(pxa3xx_lcd
, LCD
, &clk_pxa3xx_hsio_ops
);
62 static DEFINE_CK(pxa3xx_smemc
, SMC
, &clk_pxa3xx_smemc_ops
);
63 static DEFINE_CK(pxa3xx_camera
, CAMERA
, &clk_pxa3xx_hsio_ops
);
64 static DEFINE_CK(pxa3xx_ac97
, AC97
, &clk_pxa3xx_ac97_ops
);
65 static DEFINE_CLK(pxa3xx_pout
, &clk_pxa3xx_pout_ops
, 13000000, 70);
67 static struct clk_lookup pxa3xx_clkregs
[] = {
68 INIT_CLKREG(&clk_pxa3xx_pout
, NULL
, "CLK_POUT"),
69 /* Power I2C clock is always on */
70 INIT_CLKREG(&clk_dummy
, "pxa3xx-pwri2c.1", NULL
),
71 INIT_CLKREG(&clk_pxa3xx_lcd
, "pxa2xx-fb", NULL
),
72 INIT_CLKREG(&clk_pxa3xx_camera
, NULL
, "CAMCLK"),
73 INIT_CLKREG(&clk_pxa3xx_ac97
, NULL
, "AC97CLK"),
74 INIT_CLKREG(&clk_pxa3xx_ffuart
, "pxa2xx-uart.0", NULL
),
75 INIT_CLKREG(&clk_pxa3xx_btuart
, "pxa2xx-uart.1", NULL
),
76 INIT_CLKREG(&clk_pxa3xx_stuart
, "pxa2xx-uart.2", NULL
),
77 INIT_CLKREG(&clk_pxa3xx_stuart
, "pxa2xx-ir", "UARTCLK"),
78 INIT_CLKREG(&clk_pxa3xx_i2c
, "pxa2xx-i2c.0", NULL
),
79 INIT_CLKREG(&clk_pxa3xx_udc
, "pxa27x-udc", NULL
),
80 INIT_CLKREG(&clk_pxa3xx_usbh
, "pxa27x-ohci", NULL
),
81 INIT_CLKREG(&clk_pxa3xx_u2d
, "pxa3xx-u2d", NULL
),
82 INIT_CLKREG(&clk_pxa3xx_keypad
, "pxa27x-keypad", NULL
),
83 INIT_CLKREG(&clk_pxa3xx_ssp1
, "pxa27x-ssp.0", NULL
),
84 INIT_CLKREG(&clk_pxa3xx_ssp2
, "pxa27x-ssp.1", NULL
),
85 INIT_CLKREG(&clk_pxa3xx_ssp3
, "pxa27x-ssp.2", NULL
),
86 INIT_CLKREG(&clk_pxa3xx_ssp4
, "pxa27x-ssp.3", NULL
),
87 INIT_CLKREG(&clk_pxa3xx_pwm0
, "pxa27x-pwm.0", NULL
),
88 INIT_CLKREG(&clk_pxa3xx_pwm1
, "pxa27x-pwm.1", NULL
),
89 INIT_CLKREG(&clk_pxa3xx_mmc1
, "pxa2xx-mci.0", NULL
),
90 INIT_CLKREG(&clk_pxa3xx_mmc2
, "pxa2xx-mci.1", NULL
),
91 INIT_CLKREG(&clk_pxa3xx_smemc
, "pxa2xx-pcmcia", NULL
),
92 INIT_CLKREG(&clk_pxa3xx_gpio
, "pxa-gpio", NULL
),
93 INIT_CLKREG(&clk_dummy
, "sa1100-rtc", NULL
),
98 #define ISRAM_START 0x5c000000
99 #define ISRAM_SIZE SZ_256K
101 static void __iomem
*sram
;
102 static unsigned long wakeup_src
;
105 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
106 * memory controller has to be reinitialised, so we place some code
107 * in the SRAM to perform this function.
109 * We disable FIQs across the standby - otherwise, we might receive a
110 * FIQ while the SDRAM is unavailable.
112 static void pxa3xx_cpu_standby(unsigned int pwrmode
)
114 extern const char pm_enter_standby_start
[], pm_enter_standby_end
[];
115 void (*fn
)(unsigned int) = (void __force
*)(sram
+ 0x8000);
117 memcpy_toio(sram
+ 0x8000, pm_enter_standby_start
,
118 pm_enter_standby_end
- pm_enter_standby_start
);
122 AD2D0ER
= wakeup_src
;
136 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
137 * PXA3xx development kits assumes that the resuming process continues
138 * with the address stored within the first 4 bytes of SDRAM. The PSPR
139 * register is used privately by BootROM and OBM, and _must_ be set to
140 * 0x5c014000 for the moment.
142 static void pxa3xx_cpu_pm_suspend(void)
144 volatile unsigned long *p
= (volatile void *)0xc0000000;
145 unsigned long saved_data
= *p
;
146 #ifndef CONFIG_IWMMXT
149 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0
));
152 extern int pxa3xx_finish_suspend(unsigned long);
154 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
155 CKENA
|= (1 << CKEN_BOOT
) | (1 << CKEN_TPM
);
156 CKENB
|= 1 << (CKEN_HSIO2
& 0x1f);
158 /* clear and setup wakeup source */
164 PCFR
|= (1u << 13); /* L1_DIS */
165 PCFR
&= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
169 /* overwrite with the resume address */
170 *p
= virt_to_phys(cpu_resume
);
172 cpu_suspend(0, pxa3xx_finish_suspend
);
178 #ifndef CONFIG_IWMMXT
179 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0
));
183 static void pxa3xx_cpu_pm_enter(suspend_state_t state
)
186 * Don't sleep if no wakeup sources are defined
188 if (wakeup_src
== 0) {
189 printk(KERN_ERR
"Not suspending: no wakeup sources\n");
194 case PM_SUSPEND_STANDBY
:
195 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2
);
199 pxa3xx_cpu_pm_suspend();
204 static int pxa3xx_cpu_pm_valid(suspend_state_t state
)
206 return state
== PM_SUSPEND_MEM
|| state
== PM_SUSPEND_STANDBY
;
209 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns
= {
210 .valid
= pxa3xx_cpu_pm_valid
,
211 .enter
= pxa3xx_cpu_pm_enter
,
214 static void __init
pxa3xx_init_pm(void)
216 sram
= ioremap(ISRAM_START
, ISRAM_SIZE
);
218 printk(KERN_ERR
"Unable to map ISRAM: disabling standby/suspend\n");
223 * Since we copy wakeup code into the SRAM, we need to ensure
224 * that it is preserved over the low power modes. Note: bit 8
225 * is undocumented in the developer manual, but must be set.
227 AD1R
|= ADXR_L2
| ADXR_R0
;
228 AD2R
|= ADXR_L2
| ADXR_R0
;
229 AD3R
|= ADXR_L2
| ADXR_R0
;
232 * Clear the resume enable registers.
239 pxa_cpu_pm_fns
= &pxa3xx_cpu_pm_fns
;
242 static int pxa3xx_set_wake(struct irq_data
*d
, unsigned int on
)
244 unsigned long flags
, mask
= 0;
248 mask
= ADXER_MFP_WSSP3
;
261 mask
= ADXER_MFP_WAC97
;
267 mask
= ADXER_MFP_WSSP2
;
270 mask
= ADXER_MFP_WI2C
;
273 mask
= ADXER_MFP_WUART3
;
276 mask
= ADXER_MFP_WUART2
;
279 mask
= ADXER_MFP_WUART1
;
282 mask
= ADXER_MFP_WMMC1
;
285 mask
= ADXER_MFP_WSSP1
;
291 mask
= ADXER_MFP_WSSP4
;
300 mask
= ADXER_MFP_WMMC2
;
303 mask
= ADXER_MFP_WFLASH
;
309 mask
= ADXER_WEXTWAKE0
;
312 mask
= ADXER_WEXTWAKE1
;
315 mask
= ADXER_MFP_GEN12
;
321 local_irq_save(flags
);
326 local_irq_restore(flags
);
331 static inline void pxa3xx_init_pm(void) {}
332 #define pxa3xx_set_wake NULL
335 static void pxa_ack_ext_wakeup(struct irq_data
*d
)
337 PECR
|= PECR_IS(d
->irq
- IRQ_WAKEUP0
);
340 static void pxa_mask_ext_wakeup(struct irq_data
*d
)
343 PECR
&= ~PECR_IE(d
->irq
- IRQ_WAKEUP0
);
346 static void pxa_unmask_ext_wakeup(struct irq_data
*d
)
349 PECR
|= PECR_IE(d
->irq
- IRQ_WAKEUP0
);
352 static int pxa_set_ext_wakeup_type(struct irq_data
*d
, unsigned int flow_type
)
354 if (flow_type
& IRQ_TYPE_EDGE_RISING
)
355 PWER
|= 1 << (d
->irq
- IRQ_WAKEUP0
);
357 if (flow_type
& IRQ_TYPE_EDGE_FALLING
)
358 PWER
|= 1 << (d
->irq
- IRQ_WAKEUP0
+ 2);
363 static struct irq_chip pxa_ext_wakeup_chip
= {
365 .irq_ack
= pxa_ack_ext_wakeup
,
366 .irq_mask
= pxa_mask_ext_wakeup
,
367 .irq_unmask
= pxa_unmask_ext_wakeup
,
368 .irq_set_type
= pxa_set_ext_wakeup_type
,
371 static void __init
pxa_init_ext_wakeup_irq(int (*fn
)(struct irq_data
*,
376 for (irq
= IRQ_WAKEUP0
; irq
<= IRQ_WAKEUP1
; irq
++) {
377 irq_set_chip_and_handler(irq
, &pxa_ext_wakeup_chip
,
379 set_irq_flags(irq
, IRQF_VALID
);
382 pxa_ext_wakeup_chip
.irq_set_wake
= fn
;
385 void __init
pxa3xx_init_irq(void)
387 /* enable CP6 access */
389 __asm__
__volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value
));
391 __asm__
__volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value
));
393 pxa_init_irq(56, pxa3xx_set_wake
);
394 pxa_init_ext_wakeup_irq(pxa3xx_set_wake
);
397 static struct map_desc pxa3xx_io_desc
[] __initdata
= {
399 .virtual = (unsigned long)SMEMC_VIRT
,
400 .pfn
= __phys_to_pfn(PXA3XX_SMEMC_BASE
),
401 .length
= 0x00200000,
406 void __init
pxa3xx_map_io(void)
409 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc
));
410 pxa3xx_get_clk_frequency_khz(1);
414 * device registration specific to PXA3xx.
417 void __init
pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data
*info
)
419 pxa_register_device(&pxa3xx_device_i2c_power
, info
);
422 static struct platform_device
*devices
[] __initdata
= {
427 &pxa_device_asoc_ssp1
,
428 &pxa_device_asoc_ssp2
,
429 &pxa_device_asoc_ssp3
,
430 &pxa_device_asoc_ssp4
,
431 &pxa_device_asoc_platform
,
442 static int __init
pxa3xx_init(void)
446 if (cpu_is_pxa3xx()) {
451 * clear RDH bit every time after reset
453 * Note: the last 3 bits DxS are write-1-to-clear so carefully
454 * preserve them here in case they will be referenced later
456 ASCR
&= ~(ASCR_RDH
| ASCR_D1S
| ASCR_D2S
| ASCR_D3S
);
458 clkdev_add_table(pxa3xx_clkregs
, ARRAY_SIZE(pxa3xx_clkregs
));
460 if ((ret
= pxa_init_dma(IRQ_DMA
, 32)))
465 register_syscore_ops(&pxa_irq_syscore_ops
);
466 register_syscore_ops(&pxa3xx_mfp_syscore_ops
);
467 register_syscore_ops(&pxa3xx_clock_syscore_ops
);
469 ret
= platform_add_devices(devices
, ARRAY_SIZE(devices
));
475 postcore_initcall(pxa3xx_init
);