2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
23 #include <linux/sysdev.h>
25 #include <mach/hardware.h>
26 #include <mach/gpio.h>
27 #include <mach/pxa3xx-regs.h>
28 #include <mach/reset.h>
29 #include <mach/ohci.h>
39 /* Crystal clock: 13MHz */
40 #define BASE_CLK 13000000
42 /* Ring Oscillator Clock: 60MHz */
43 #define RO_CLK 60000000
45 #define ACCR_D0CS (1 << 26)
46 #define ACCR_PCCE (1 << 11)
48 /* crystal frequency to static memory controller multiplier (SMCFS) */
49 static unsigned char smcfs_mult
[8] = { 6, 0, 8, 0, 0, 16, };
51 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
52 static unsigned char hss_mult
[4] = { 8, 12, 16, 0 };
55 * Get the clock frequency as reflected by CCSR and the turbo flag.
56 * We assume these values have been applied via a fcs.
57 * If info is not 0 we also display the current settings.
59 unsigned int pxa3xx_get_clk_frequency_khz(int info
)
61 unsigned long acsr
, xclkcfg
;
62 unsigned int t
, xl
, xn
, hss
, ro
, XL
, XN
, CLK
, HSS
;
64 /* Read XCLKCFG register turbo bit */
65 __asm__
__volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg
));
71 xn
= (acsr
>> 8) & 0x7;
72 hss
= (acsr
>> 14) & 0x3;
77 ro
= acsr
& ACCR_D0CS
;
79 CLK
= (ro
) ? RO_CLK
: ((t
) ? XN
: XL
);
80 HSS
= (ro
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
83 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
84 RO_CLK
/ 1000000, (RO_CLK
% 1000000) / 10000,
86 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
87 XL
/ 1000000, (XL
% 1000000) / 10000, xl
);
88 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
89 XN
/ 1000000, (XN
% 1000000) / 10000, xn
,
91 pr_info("HSIO bus clock: %d.%02dMHz\n",
92 HSS
/ 1000000, (HSS
% 1000000) / 10000);
99 * Return the current static memory controller clock frequency
102 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
105 unsigned int smcfs
, clk
= 0;
109 smcfs
= (acsr
>> 23) & 0x7;
110 clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: smcfs_mult
[smcfs
] * BASE_CLK
;
112 return (clk
/ 10000);
115 void pxa3xx_clear_reset_status(unsigned int mask
)
117 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
122 * Return the current AC97 clock frequency.
124 static unsigned long clk_pxa3xx_ac97_getrate(struct clk
*clk
)
126 unsigned long rate
= 312000000;
127 unsigned long ac97_div
;
131 /* This may loose precision for some rates but won't for the
132 * standard 24.576MHz.
134 rate
/= (ac97_div
>> 12) & 0x7fff;
135 rate
*= (ac97_div
& 0xfff);
141 * Return the current HSIO bus clock frequency
143 static unsigned long clk_pxa3xx_hsio_getrate(struct clk
*clk
)
146 unsigned int hss
, hsio_clk
;
150 hss
= (acsr
>> 14) & 0x3;
151 hsio_clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
156 void clk_pxa3xx_cken_enable(struct clk
*clk
)
158 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
166 void clk_pxa3xx_cken_disable(struct clk
*clk
)
168 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
176 const struct clkops clk_pxa3xx_cken_ops
= {
177 .enable
= clk_pxa3xx_cken_enable
,
178 .disable
= clk_pxa3xx_cken_disable
,
181 static const struct clkops clk_pxa3xx_hsio_ops
= {
182 .enable
= clk_pxa3xx_cken_enable
,
183 .disable
= clk_pxa3xx_cken_disable
,
184 .getrate
= clk_pxa3xx_hsio_getrate
,
187 static const struct clkops clk_pxa3xx_ac97_ops
= {
188 .enable
= clk_pxa3xx_cken_enable
,
189 .disable
= clk_pxa3xx_cken_disable
,
190 .getrate
= clk_pxa3xx_ac97_getrate
,
193 static void clk_pout_enable(struct clk
*clk
)
198 static void clk_pout_disable(struct clk
*clk
)
203 static const struct clkops clk_pout_ops
= {
204 .enable
= clk_pout_enable
,
205 .disable
= clk_pout_disable
,
208 static void clk_dummy_enable(struct clk
*clk
)
212 static void clk_dummy_disable(struct clk
*clk
)
216 static const struct clkops clk_dummy_ops
= {
217 .enable
= clk_dummy_enable
,
218 .disable
= clk_dummy_disable
,
221 static struct clk clk_pxa3xx_pout
= {
222 .ops
= &clk_pout_ops
,
227 static struct clk clk_dummy
= {
228 .ops
= &clk_dummy_ops
,
231 static DEFINE_PXA3_CK(pxa3xx_lcd
, LCD
, &clk_pxa3xx_hsio_ops
);
232 static DEFINE_PXA3_CK(pxa3xx_camera
, CAMERA
, &clk_pxa3xx_hsio_ops
);
233 static DEFINE_PXA3_CK(pxa3xx_ac97
, AC97
, &clk_pxa3xx_ac97_ops
);
234 static DEFINE_PXA3_CKEN(pxa3xx_ffuart
, FFUART
, 14857000, 1);
235 static DEFINE_PXA3_CKEN(pxa3xx_btuart
, BTUART
, 14857000, 1);
236 static DEFINE_PXA3_CKEN(pxa3xx_stuart
, STUART
, 14857000, 1);
237 static DEFINE_PXA3_CKEN(pxa3xx_i2c
, I2C
, 32842000, 0);
238 static DEFINE_PXA3_CKEN(pxa3xx_udc
, UDC
, 48000000, 5);
239 static DEFINE_PXA3_CKEN(pxa3xx_usbh
, USBH
, 48000000, 0);
240 static DEFINE_PXA3_CKEN(pxa3xx_u2d
, USB2
, 48000000, 0);
241 static DEFINE_PXA3_CKEN(pxa3xx_keypad
, KEYPAD
, 32768, 0);
242 static DEFINE_PXA3_CKEN(pxa3xx_ssp1
, SSP1
, 13000000, 0);
243 static DEFINE_PXA3_CKEN(pxa3xx_ssp2
, SSP2
, 13000000, 0);
244 static DEFINE_PXA3_CKEN(pxa3xx_ssp3
, SSP3
, 13000000, 0);
245 static DEFINE_PXA3_CKEN(pxa3xx_ssp4
, SSP4
, 13000000, 0);
246 static DEFINE_PXA3_CKEN(pxa3xx_pwm0
, PWM0
, 13000000, 0);
247 static DEFINE_PXA3_CKEN(pxa3xx_pwm1
, PWM1
, 13000000, 0);
248 static DEFINE_PXA3_CKEN(pxa3xx_mmc1
, MMC1
, 19500000, 0);
249 static DEFINE_PXA3_CKEN(pxa3xx_mmc2
, MMC2
, 19500000, 0);
251 static struct clk_lookup pxa3xx_clkregs
[] = {
252 INIT_CLKREG(&clk_pxa3xx_pout
, NULL
, "CLK_POUT"),
253 /* Power I2C clock is always on */
254 INIT_CLKREG(&clk_dummy
, "pxa3xx-pwri2c.1", NULL
),
255 INIT_CLKREG(&clk_pxa3xx_lcd
, "pxa2xx-fb", NULL
),
256 INIT_CLKREG(&clk_pxa3xx_camera
, NULL
, "CAMCLK"),
257 INIT_CLKREG(&clk_pxa3xx_ac97
, NULL
, "AC97CLK"),
258 INIT_CLKREG(&clk_pxa3xx_ffuart
, "pxa2xx-uart.0", NULL
),
259 INIT_CLKREG(&clk_pxa3xx_btuart
, "pxa2xx-uart.1", NULL
),
260 INIT_CLKREG(&clk_pxa3xx_stuart
, "pxa2xx-uart.2", NULL
),
261 INIT_CLKREG(&clk_pxa3xx_stuart
, "pxa2xx-ir", "UARTCLK"),
262 INIT_CLKREG(&clk_pxa3xx_i2c
, "pxa2xx-i2c.0", NULL
),
263 INIT_CLKREG(&clk_pxa3xx_udc
, "pxa27x-udc", NULL
),
264 INIT_CLKREG(&clk_pxa3xx_usbh
, "pxa27x-ohci", NULL
),
265 INIT_CLKREG(&clk_pxa3xx_u2d
, NULL
, "U2DCLK"),
266 INIT_CLKREG(&clk_pxa3xx_keypad
, "pxa27x-keypad", NULL
),
267 INIT_CLKREG(&clk_pxa3xx_ssp1
, "pxa27x-ssp.0", NULL
),
268 INIT_CLKREG(&clk_pxa3xx_ssp2
, "pxa27x-ssp.1", NULL
),
269 INIT_CLKREG(&clk_pxa3xx_ssp3
, "pxa27x-ssp.2", NULL
),
270 INIT_CLKREG(&clk_pxa3xx_ssp4
, "pxa27x-ssp.3", NULL
),
271 INIT_CLKREG(&clk_pxa3xx_pwm0
, "pxa27x-pwm.0", NULL
),
272 INIT_CLKREG(&clk_pxa3xx_pwm1
, "pxa27x-pwm.1", NULL
),
273 INIT_CLKREG(&clk_pxa3xx_mmc1
, "pxa2xx-mci.0", NULL
),
274 INIT_CLKREG(&clk_pxa3xx_mmc2
, "pxa2xx-mci.1", NULL
),
279 #define ISRAM_START 0x5c000000
280 #define ISRAM_SIZE SZ_256K
282 static void __iomem
*sram
;
283 static unsigned long wakeup_src
;
285 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
286 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
288 enum { SLEEP_SAVE_CKENA
,
295 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save
)
302 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save
)
310 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
311 * memory controller has to be reinitialised, so we place some code
312 * in the SRAM to perform this function.
314 * We disable FIQs across the standby - otherwise, we might receive a
315 * FIQ while the SDRAM is unavailable.
317 static void pxa3xx_cpu_standby(unsigned int pwrmode
)
319 extern const char pm_enter_standby_start
[], pm_enter_standby_end
[];
320 void (*fn
)(unsigned int) = (void __force
*)(sram
+ 0x8000);
322 memcpy_toio(sram
+ 0x8000, pm_enter_standby_start
,
323 pm_enter_standby_end
- pm_enter_standby_start
);
327 AD2D0ER
= wakeup_src
;
341 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
342 * PXA3xx development kits assumes that the resuming process continues
343 * with the address stored within the first 4 bytes of SDRAM. The PSPR
344 * register is used privately by BootROM and OBM, and _must_ be set to
345 * 0x5c014000 for the moment.
347 static void pxa3xx_cpu_pm_suspend(void)
349 volatile unsigned long *p
= (volatile void *)0xc0000000;
350 unsigned long saved_data
= *p
;
352 extern void pxa3xx_cpu_suspend(void);
353 extern void pxa3xx_cpu_resume(void);
355 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
356 CKENA
|= (1 << CKEN_BOOT
) | (1 << CKEN_TPM
);
357 CKENB
|= 1 << (CKEN_HSIO2
& 0x1f);
359 /* clear and setup wakeup source */
365 PCFR
|= (1u << 13); /* L1_DIS */
366 PCFR
&= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
370 /* overwrite with the resume address */
371 *p
= virt_to_phys(pxa3xx_cpu_resume
);
373 pxa3xx_cpu_suspend();
380 static void pxa3xx_cpu_pm_enter(suspend_state_t state
)
383 * Don't sleep if no wakeup sources are defined
385 if (wakeup_src
== 0) {
386 printk(KERN_ERR
"Not suspending: no wakeup sources\n");
391 case PM_SUSPEND_STANDBY
:
392 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2
);
396 pxa3xx_cpu_pm_suspend();
401 static int pxa3xx_cpu_pm_valid(suspend_state_t state
)
403 return state
== PM_SUSPEND_MEM
|| state
== PM_SUSPEND_STANDBY
;
406 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns
= {
407 .save_count
= SLEEP_SAVE_COUNT
,
408 .save
= pxa3xx_cpu_pm_save
,
409 .restore
= pxa3xx_cpu_pm_restore
,
410 .valid
= pxa3xx_cpu_pm_valid
,
411 .enter
= pxa3xx_cpu_pm_enter
,
414 static void __init
pxa3xx_init_pm(void)
416 sram
= ioremap(ISRAM_START
, ISRAM_SIZE
);
418 printk(KERN_ERR
"Unable to map ISRAM: disabling standby/suspend\n");
423 * Since we copy wakeup code into the SRAM, we need to ensure
424 * that it is preserved over the low power modes. Note: bit 8
425 * is undocumented in the developer manual, but must be set.
427 AD1R
|= ADXR_L2
| ADXR_R0
;
428 AD2R
|= ADXR_L2
| ADXR_R0
;
429 AD3R
|= ADXR_L2
| ADXR_R0
;
432 * Clear the resume enable registers.
439 pxa_cpu_pm_fns
= &pxa3xx_cpu_pm_fns
;
442 static int pxa3xx_set_wake(unsigned int irq
, unsigned int on
)
444 unsigned long flags
, mask
= 0;
448 mask
= ADXER_MFP_WSSP3
;
461 mask
= ADXER_MFP_WAC97
;
467 mask
= ADXER_MFP_WSSP2
;
470 mask
= ADXER_MFP_WI2C
;
473 mask
= ADXER_MFP_WUART3
;
476 mask
= ADXER_MFP_WUART2
;
479 mask
= ADXER_MFP_WUART1
;
482 mask
= ADXER_MFP_WMMC1
;
485 mask
= ADXER_MFP_WSSP1
;
491 mask
= ADXER_MFP_WSSP4
;
500 mask
= ADXER_MFP_WMMC2
;
503 mask
= ADXER_MFP_WFLASH
;
509 mask
= ADXER_WEXTWAKE0
;
512 mask
= ADXER_WEXTWAKE1
;
515 mask
= ADXER_MFP_GEN12
;
521 local_irq_save(flags
);
526 local_irq_restore(flags
);
531 static inline void pxa3xx_init_pm(void) {}
532 #define pxa3xx_set_wake NULL
535 void __init
pxa3xx_init_irq(void)
537 /* enable CP6 access */
539 __asm__
__volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value
));
541 __asm__
__volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value
));
543 pxa_init_irq(56, pxa3xx_set_wake
);
544 pxa_init_gpio(IRQ_GPIO_2_x
, 2, 127, NULL
);
548 * device registration specific to PXA3xx.
551 void __init
pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data
*info
)
553 pxa_register_device(&pxa3xx_device_i2c_power
, info
);
556 static struct platform_device
*devices
[] __initdata
= {
569 static struct sys_device pxa3xx_sysdev
[] = {
571 .cls
= &pxa_irq_sysclass
,
573 .cls
= &pxa3xx_mfp_sysclass
,
575 .cls
= &pxa_gpio_sysclass
,
579 static int __init
pxa3xx_init(void)
583 if (cpu_is_pxa3xx()) {
588 * clear RDH bit every time after reset
590 * Note: the last 3 bits DxS are write-1-to-clear so carefully
591 * preserve them here in case they will be referenced later
593 ASCR
&= ~(ASCR_RDH
| ASCR_D1S
| ASCR_D2S
| ASCR_D3S
);
595 clks_register(pxa3xx_clkregs
, ARRAY_SIZE(pxa3xx_clkregs
));
597 if ((ret
= pxa_init_dma(IRQ_DMA
, 32)))
602 for (i
= 0; i
< ARRAY_SIZE(pxa3xx_sysdev
); i
++) {
603 ret
= sysdev_register(&pxa3xx_sysdev
[i
]);
605 pr_err("failed to register sysdev[%d]\n", i
);
608 ret
= platform_add_devices(devices
, ARRAY_SIZE(devices
));
614 postcore_initcall(pxa3xx_init
);