1 /* linux/arch/arm/mach-s5p6440/clock.c
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5P6440 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
26 #include <plat/cpu-freq.h>
27 #include <mach/regs-clock.h>
28 #include <plat/clock.h>
30 #include <plat/clock-clksrc.h>
31 #include <plat/s5p-clock.h>
33 #include <plat/s5p6440.h>
35 /* APLL Mux output clock */
36 static struct clksrc_clk clk_mout_apll
= {
41 .sources
= &clk_src_apll
,
42 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 0, .size
= 1 },
45 static int s5p6440_epll_enable(struct clk
*clk
, int enable
)
47 unsigned int ctrlbit
= clk
->ctrlbit
;
48 unsigned int epll_con
= __raw_readl(S5P_EPLL_CON
) & ~ctrlbit
;
51 __raw_writel(epll_con
| ctrlbit
, S5P_EPLL_CON
);
53 __raw_writel(epll_con
, S5P_EPLL_CON
);
58 static unsigned long s5p6440_epll_get_rate(struct clk
*clk
)
63 static u32 epll_div
[][5] = {
64 { 36000000, 0, 48, 1, 4 },
65 { 48000000, 0, 32, 1, 3 },
66 { 60000000, 0, 40, 1, 3 },
67 { 72000000, 0, 48, 1, 3 },
68 { 84000000, 0, 28, 1, 2 },
69 { 96000000, 0, 32, 1, 2 },
70 { 32768000, 45264, 43, 1, 4 },
71 { 45158000, 6903, 30, 1, 3 },
72 { 49152000, 50332, 32, 1, 3 },
73 { 67738000, 10398, 45, 1, 3 },
74 { 73728000, 9961, 49, 1, 3 }
77 static int s5p6440_epll_set_rate(struct clk
*clk
, unsigned long rate
)
79 unsigned int epll_con
, epll_con_k
;
82 if (clk
->rate
== rate
) /* Return if nothing changed */
85 epll_con
= __raw_readl(S5P_EPLL_CON
);
86 epll_con_k
= __raw_readl(S5P_EPLL_CON_K
);
88 epll_con_k
&= ~(PLL90XX_KDIV_MASK
);
89 epll_con
&= ~(PLL90XX_MDIV_MASK
| PLL90XX_PDIV_MASK
| PLL90XX_SDIV_MASK
);
91 for (i
= 0; i
< ARRAY_SIZE(epll_div
); i
++) {
92 if (epll_div
[i
][0] == rate
) {
93 epll_con_k
|= (epll_div
[i
][1] << PLL90XX_KDIV_SHIFT
);
94 epll_con
|= (epll_div
[i
][2] << PLL90XX_MDIV_SHIFT
) |
95 (epll_div
[i
][3] << PLL90XX_PDIV_SHIFT
) |
96 (epll_div
[i
][4] << PLL90XX_SDIV_SHIFT
);
101 if (i
== ARRAY_SIZE(epll_div
)) {
102 printk(KERN_ERR
"%s: Invalid Clock EPLL Frequency\n", __func__
);
106 __raw_writel(epll_con
, S5P_EPLL_CON
);
107 __raw_writel(epll_con_k
, S5P_EPLL_CON_K
);
114 static struct clk_ops s5p6440_epll_ops
= {
115 .get_rate
= s5p6440_epll_get_rate
,
116 .set_rate
= s5p6440_epll_set_rate
,
119 static struct clksrc_clk clk_mout_epll
= {
124 .sources
= &clk_src_epll
,
125 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 2, .size
= 1 },
128 static struct clksrc_clk clk_mout_mpll
= {
133 .sources
= &clk_src_mpll
,
134 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 1, .size
= 1 },
137 static struct clk clk_h_low
= {
143 .ops
= &clk_ops_def_setrate
,
146 static struct clk clk_p_low
= {
152 .ops
= &clk_ops_def_setrate
,
161 static const u32 clock_table
[][3] = {
162 /*{ARM_CLK, DIVarm, DIVhclk}*/
163 {L0
* 1000, (0 << ARM_DIV_RATIO_SHIFT
), (3 << S5P_CLKDIV0_HCLK_SHIFT
)},
164 {L1
* 1000, (1 << ARM_DIV_RATIO_SHIFT
), (1 << S5P_CLKDIV0_HCLK_SHIFT
)},
165 {L2
* 1000, (3 << ARM_DIV_RATIO_SHIFT
), (0 << S5P_CLKDIV0_HCLK_SHIFT
)},
168 static unsigned long s5p6440_armclk_get_rate(struct clk
*clk
)
170 unsigned long rate
= clk_get_rate(clk
->parent
);
173 /* divisor mask starts at bit0, so no need to shift */
174 clkdiv
= __raw_readl(ARM_CLK_DIV
) & ARM_DIV_MASK
;
176 return rate
/ (clkdiv
+ 1);
179 static unsigned long s5p6440_armclk_round_rate(struct clk
*clk
,
184 for (iter
= 1 ; iter
< ARRAY_SIZE(clock_table
) ; iter
++) {
185 if (rate
> clock_table
[iter
][0])
186 return clock_table
[iter
-1][0];
189 return clock_table
[ARRAY_SIZE(clock_table
) - 1][0];
192 static int s5p6440_armclk_set_rate(struct clk
*clk
, unsigned long rate
)
197 u32 cur_rate
= clk
->ops
->get_rate(clk
);
200 round_tmp
= clk
->ops
->round_rate(clk
, rate
);
201 if (round_tmp
== cur_rate
)
205 for (iter
= 0 ; iter
< ARRAY_SIZE(clock_table
) ; iter
++) {
206 if (round_tmp
== clock_table
[iter
][0])
210 if (iter
>= ARRAY_SIZE(clock_table
))
211 iter
= ARRAY_SIZE(clock_table
) - 1;
213 local_irq_save(flags
);
214 if (cur_rate
> round_tmp
) {
216 clk_div0_tmp
= __raw_readl(ARM_CLK_DIV
) & ~(ARM_DIV_MASK
);
217 clk_div0_tmp
|= clock_table
[iter
][1];
218 __raw_writel(clk_div0_tmp
, ARM_CLK_DIV
);
220 clk_div0_tmp
= __raw_readl(ARM_CLK_DIV
) &
221 ~(S5P_CLKDIV0_HCLK_MASK
);
222 clk_div0_tmp
|= clock_table
[iter
][2];
223 __raw_writel(clk_div0_tmp
, ARM_CLK_DIV
);
228 clk_div0_tmp
= __raw_readl(ARM_CLK_DIV
) &
229 ~(S5P_CLKDIV0_HCLK_MASK
);
230 clk_div0_tmp
|= clock_table
[iter
][2];
231 __raw_writel(clk_div0_tmp
, ARM_CLK_DIV
);
233 clk_div0_tmp
= __raw_readl(ARM_CLK_DIV
) & ~(ARM_DIV_MASK
);
234 clk_div0_tmp
|= clock_table
[iter
][1];
235 __raw_writel(clk_div0_tmp
, ARM_CLK_DIV
);
237 local_irq_restore(flags
);
239 clk
->rate
= clock_table
[iter
][0];
244 static struct clk_ops s5p6440_clkarm_ops
= {
245 .get_rate
= s5p6440_armclk_get_rate
,
246 .set_rate
= s5p6440_armclk_set_rate
,
247 .round_rate
= s5p6440_armclk_round_rate
,
250 static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk
*clk
)
252 unsigned long rate
= clk_get_rate(clk
->parent
);
254 if (__raw_readl(S5P_CLK_DIV0
) & S5P_CLKDIV0_MPLL_MASK
)
260 static struct clk clk_dout_mpll
= {
263 .parent
= &clk_mout_mpll
.clk
,
264 .ops
= &(struct clk_ops
) {
265 .get_rate
= s5p6440_clk_doutmpll_get_rate
,
269 int s5p6440_clk48m_ctrl(struct clk
*clk
, int enable
)
274 /* can't rely on clock lock, this register has other usages */
275 local_irq_save(flags
);
277 val
= __raw_readl(S5P_OTHERS
);
279 val
|= S5P_OTHERS_USB_SIG_MASK
;
281 val
&= ~S5P_OTHERS_USB_SIG_MASK
;
283 __raw_writel(val
, S5P_OTHERS
);
285 local_irq_restore(flags
);
290 static int s5p6440_pclk_ctrl(struct clk
*clk
, int enable
)
292 return s5p_gatectrl(S5P_CLK_GATE_PCLK
, clk
, enable
);
295 static int s5p6440_hclk0_ctrl(struct clk
*clk
, int enable
)
297 return s5p_gatectrl(S5P_CLK_GATE_HCLK0
, clk
, enable
);
300 static int s5p6440_hclk1_ctrl(struct clk
*clk
, int enable
)
302 return s5p_gatectrl(S5P_CLK_GATE_HCLK1
, clk
, enable
);
305 static int s5p6440_sclk_ctrl(struct clk
*clk
, int enable
)
307 return s5p_gatectrl(S5P_CLK_GATE_SCLK0
, clk
, enable
);
310 static int s5p6440_mem_ctrl(struct clk
*clk
, int enable
)
312 return s5p_gatectrl(S5P_CLK_GATE_MEM0
, clk
, enable
);
316 * The following clocks will be disabled during clock initialization. It is
317 * recommended to keep the following clocks disabled until the driver requests
318 * for enabling the clock.
320 static struct clk init_clocks_disable
[] = {
325 .enable
= s5p6440_mem_ctrl
,
326 .ctrlbit
= S5P_CLKCON_MEM0_HCLK_NFCON
,
330 .parent
= &clk_p_low
,
331 .enable
= s5p6440_pclk_ctrl
,
332 .ctrlbit
= S5P_CLKCON_PCLK_TSADC
,
336 .parent
= &clk_p_low
,
337 .enable
= s5p6440_pclk_ctrl
,
338 .ctrlbit
= S5P_CLKCON_PCLK_IIC0
,
342 .parent
= &clk_p_low
,
343 .enable
= s5p6440_pclk_ctrl
,
344 .ctrlbit
= S5P_CLKCON_PCLK_IIS2
,
348 .parent
= &clk_p_low
,
349 .enable
= s5p6440_pclk_ctrl
,
350 .ctrlbit
= S5P_CLKCON_PCLK_SPI0
,
354 .parent
= &clk_p_low
,
355 .enable
= s5p6440_pclk_ctrl
,
356 .ctrlbit
= S5P_CLKCON_PCLK_SPI1
,
358 .name
= "sclk_spi_48",
361 .enable
= s5p6440_sclk_ctrl
,
362 .ctrlbit
= S5P_CLKCON_SCLK0_SPI0_48
,
364 .name
= "sclk_spi_48",
367 .enable
= s5p6440_sclk_ctrl
,
368 .ctrlbit
= S5P_CLKCON_SCLK0_SPI1_48
,
373 .enable
= s5p6440_sclk_ctrl
,
374 .ctrlbit
= S5P_CLKCON_SCLK0_MMC0_48
,
379 .enable
= s5p6440_sclk_ctrl
,
380 .ctrlbit
= S5P_CLKCON_SCLK0_MMC1_48
,
385 .enable
= s5p6440_sclk_ctrl
,
386 .ctrlbit
= S5P_CLKCON_SCLK0_MMC2_48
,
390 .parent
= &clk_h_low
,
391 .enable
= s5p6440_hclk0_ctrl
,
392 .ctrlbit
= S5P_CLKCON_HCLK0_USB
396 .parent
= &clk_h_low
,
397 .enable
= s5p6440_hclk0_ctrl
,
398 .ctrlbit
= S5P_CLKCON_HCLK0_POST0
402 .parent
= &clk_h_low
,
403 .enable
= s5p6440_hclk1_ctrl
,
404 .ctrlbit
= S5P_CLKCON_HCLK1_DISPCON
,
408 .parent
= &clk_h_low
,
409 .enable
= s5p6440_hclk0_ctrl
,
410 .ctrlbit
= S5P_CLKCON_HCLK0_HSMMC0
,
414 .parent
= &clk_h_low
,
415 .enable
= s5p6440_hclk0_ctrl
,
416 .ctrlbit
= S5P_CLKCON_HCLK0_HSMMC1
,
420 .parent
= &clk_h_low
,
421 .enable
= s5p6440_hclk0_ctrl
,
422 .ctrlbit
= S5P_CLKCON_HCLK0_HSMMC2
,
426 .parent
= &clk_p_low
,
427 .enable
= s5p6440_pclk_ctrl
,
428 .ctrlbit
= S5P_CLKCON_PCLK_RTC
,
432 .parent
= &clk_p_low
,
433 .enable
= s5p6440_pclk_ctrl
,
434 .ctrlbit
= S5P_CLKCON_PCLK_WDT
,
438 .parent
= &clk_p_low
,
439 .enable
= s5p6440_pclk_ctrl
,
440 .ctrlbit
= S5P_CLKCON_PCLK_PWM
,
445 * The following clocks will be enabled during clock initialization.
447 static struct clk init_clocks
[] = {
451 .parent
= &clk_p_low
,
452 .enable
= s5p6440_pclk_ctrl
,
453 .ctrlbit
= S5P_CLKCON_PCLK_GPIO
,
457 .parent
= &clk_p_low
,
458 .enable
= s5p6440_pclk_ctrl
,
459 .ctrlbit
= S5P_CLKCON_PCLK_UART0
,
463 .parent
= &clk_p_low
,
464 .enable
= s5p6440_pclk_ctrl
,
465 .ctrlbit
= S5P_CLKCON_PCLK_UART1
,
469 .parent
= &clk_p_low
,
470 .enable
= s5p6440_pclk_ctrl
,
471 .ctrlbit
= S5P_CLKCON_PCLK_UART2
,
475 .parent
= &clk_p_low
,
476 .enable
= s5p6440_pclk_ctrl
,
477 .ctrlbit
= S5P_CLKCON_PCLK_UART3
,
481 static struct clk clk_iis_cd_v40
= {
482 .name
= "iis_cdclk_v40",
486 static struct clk clk_pcm_cd
= {
491 static struct clk
*clkset_spi_mmc_list
[] = {
497 static struct clksrc_sources clkset_spi_mmc
= {
498 .sources
= clkset_spi_mmc_list
,
499 .nr_sources
= ARRAY_SIZE(clkset_spi_mmc_list
),
502 static struct clk
*clkset_uart_list
[] = {
507 static struct clksrc_sources clkset_uart
= {
508 .sources
= clkset_uart_list
,
509 .nr_sources
= ARRAY_SIZE(clkset_uart_list
),
512 static struct clksrc_clk clksrcs
[] = {
517 .ctrlbit
= S5P_CLKCON_SCLK0_MMC0
,
518 .enable
= s5p6440_sclk_ctrl
,
520 .sources
= &clkset_spi_mmc
,
521 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 18, .size
= 2 },
522 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 0, .size
= 4 },
527 .ctrlbit
= S5P_CLKCON_SCLK0_MMC1
,
528 .enable
= s5p6440_sclk_ctrl
,
530 .sources
= &clkset_spi_mmc
,
531 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 20, .size
= 2 },
532 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 4, .size
= 4 },
537 .ctrlbit
= S5P_CLKCON_SCLK0_MMC2
,
538 .enable
= s5p6440_sclk_ctrl
,
540 .sources
= &clkset_spi_mmc
,
541 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 22, .size
= 2 },
542 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 8, .size
= 4 },
547 .ctrlbit
= S5P_CLKCON_SCLK0_UART
,
548 .enable
= s5p6440_sclk_ctrl
,
550 .sources
= &clkset_uart
,
551 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 13, .size
= 1 },
552 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 16, .size
= 4 },
557 .ctrlbit
= S5P_CLKCON_SCLK0_SPI0
,
558 .enable
= s5p6440_sclk_ctrl
,
560 .sources
= &clkset_spi_mmc
,
561 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 14, .size
= 2 },
562 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 0, .size
= 4 },
567 .ctrlbit
= S5P_CLKCON_SCLK0_SPI1
,
568 .enable
= s5p6440_sclk_ctrl
,
570 .sources
= &clkset_spi_mmc
,
571 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 16, .size
= 2 },
572 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 4, .size
= 4 },
576 /* Clock initialisation code */
577 static struct clksrc_clk
*init_parents
[] = {
583 void __init_or_cpufreq
s5p6440_setup_clocks(void)
585 struct clk
*xtal_clk
;
589 unsigned long hclk_low
;
591 unsigned long pclk_low
;
599 /* Set S5P6440 functions for clk_fout_epll */
600 clk_fout_epll
.enable
= s5p6440_epll_enable
;
601 clk_fout_epll
.ops
= &s5p6440_epll_ops
;
603 /* Set S5P6440 functions for arm clock */
604 clk_arm
.parent
= &clk_mout_apll
.clk
;
605 clk_arm
.ops
= &s5p6440_clkarm_ops
;
606 clk_48m
.enable
= s5p6440_clk48m_ctrl
;
608 clkdiv0
= __raw_readl(S5P_CLK_DIV0
);
609 clkdiv3
= __raw_readl(S5P_CLK_DIV3
);
611 xtal_clk
= clk_get(NULL
, "ext_xtal");
612 BUG_ON(IS_ERR(xtal_clk
));
614 xtal
= clk_get_rate(xtal_clk
);
617 epll
= s5p_get_pll90xx(xtal
, __raw_readl(S5P_EPLL_CON
),
618 __raw_readl(S5P_EPLL_CON_K
));
619 mpll
= s5p_get_pll45xx(xtal
, __raw_readl(S5P_MPLL_CON
), pll_4502
);
620 apll
= s5p_get_pll45xx(xtal
, __raw_readl(S5P_APLL_CON
), pll_4502
);
622 printk(KERN_INFO
"S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
624 print_mhz(apll
), print_mhz(mpll
), print_mhz(epll
));
626 fclk
= apll
/ GET_DIV(clkdiv0
, S5P_CLKDIV0_ARM
);
627 hclk
= fclk
/ GET_DIV(clkdiv0
, S5P_CLKDIV0_HCLK
);
628 pclk
= hclk
/ GET_DIV(clkdiv0
, S5P_CLKDIV0_PCLK
);
630 if (__raw_readl(S5P_OTHERS
) & S5P_OTHERS_HCLK_LOW_SEL_MPLL
) {
631 /* Asynchronous mode */
632 hclk_low
= mpll
/ GET_DIV(clkdiv3
, S5P_CLKDIV3_HCLK_LOW
);
634 /* Synchronous mode */
635 hclk_low
= apll
/ GET_DIV(clkdiv3
, S5P_CLKDIV3_HCLK_LOW
);
638 pclk_low
= hclk_low
/ GET_DIV(clkdiv3
, S5P_CLKDIV3_PCLK_LOW
);
640 printk(KERN_INFO
"S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
641 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
642 print_mhz(hclk
), print_mhz(hclk_low
),
643 print_mhz(pclk
), print_mhz(pclk_low
));
645 clk_fout_mpll
.rate
= mpll
;
646 clk_fout_epll
.rate
= epll
;
647 clk_fout_apll
.rate
= apll
;
652 clk_h_low
.rate
= hclk_low
;
653 clk_p_low
.rate
= pclk_low
;
655 for (ptr
= 0; ptr
< ARRAY_SIZE(init_parents
); ptr
++)
656 s3c_set_clksrc(init_parents
[ptr
], true);
658 for (ptr
= 0; ptr
< ARRAY_SIZE(clksrcs
); ptr
++)
659 s3c_set_clksrc(&clksrcs
[ptr
], true);
662 static struct clk
*clks
[] __initdata
= {
673 void __init
s5p6440_register_clocks(void)
679 ret
= s3c24xx_register_clocks(clks
, ARRAY_SIZE(clks
));
681 printk(KERN_ERR
"Failed to register %u clocks\n", ret
);
683 s3c_register_clksrc(clksrcs
, ARRAY_SIZE(clksrcs
));
684 s3c_register_clocks(init_clocks
, ARRAY_SIZE(init_clocks
));
686 clkp
= init_clocks_disable
;
687 for (ptr
= 0; ptr
< ARRAY_SIZE(init_clocks_disable
); ptr
++, clkp
++) {
689 ret
= s3c24xx_register_clock(clkp
);
691 printk(KERN_ERR
"Failed to register clock %s (%d)\n",
694 (clkp
->enable
)(clkp
, 0);