arch/arm/mach-sa1100/generic.c

   1 /*
   2  * linux/arch/arm/mach-sa1100/generic.c
   3  *
   4  * Author: Nicolas Pitre
   5  *
   6  * Code common to all SA11x0 machines.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/gpio.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/pm.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/ioport.h>
  21 #include <linux/platform_device.h>
  22
  23 #include <video/sa1100fb.h>
  24
  25 #include <asm/div64.h>
  26 #include <mach/hardware.h>
  27 #include <asm/system.h>
  28 #include <asm/mach/map.h>
  29 #include <asm/mach/flash.h>
  30 #include <asm/irq.h>
  31
  32 #include "generic.h"
  33
  34 unsigned int reset_status;
  35 EXPORT_SYMBOL(reset_status);
  36
  37 #define NR_FREQS        16
  38
  39 /*
  40  * This table is setup for a 3.6864MHz Crystal.
  41  */
  42 static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
  43          590,   /*  59.0 MHz */
  44          737,   /*  73.7 MHz */
  45          885,   /*  88.5 MHz */
  46         1032,   /* 103.2 MHz */
  47         1180,   /* 118.0 MHz */
  48         1327,   /* 132.7 MHz */
  49         1475,   /* 147.5 MHz */
  50         1622,   /* 162.2 MHz */
  51         1769,   /* 176.9 MHz */
  52         1917,   /* 191.7 MHz */
  53         2064,   /* 206.4 MHz */
  54         2212,   /* 221.2 MHz */
  55         2359,   /* 235.9 MHz */
  56         2507,   /* 250.7 MHz */
  57         2654,   /* 265.4 MHz */
  58         2802    /* 280.2 MHz */
  59 };
  60
  61 /* rounds up(!)  */
  62 unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
  63 {
  64         int i;
  65
  66         khz /= 100;
  67
  68         for (i = 0; i < NR_FREQS; i++)
  69                 if (cclk_frequency_100khz[i] >= khz)
  70                         break;
  71
  72         return i;
  73 }
  74
  75 unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
  76 {
  77         unsigned int freq = 0;
  78         if (idx < NR_FREQS)
  79                 freq = cclk_frequency_100khz[idx] * 100;
  80         return freq;
  81 }
  82
  83
  84 /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
  85  * this platform, anyway.
  86  */
  87 int sa11x0_verify_speed(struct cpufreq_policy *policy)
  88 {
  89         unsigned int tmp;
  90         if (policy->cpu)
  91                 return -EINVAL;
  92
  93         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  94
  95         /* make sure that at least one frequency is within the policy */
  96         tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
  97         if (tmp > policy->max)
  98                 policy->max = tmp;
  99
 100         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
 101
 102         return 0;
 103 }
 104
 105 unsigned int sa11x0_getspeed(unsigned int cpu)
 106 {
 107         if (cpu)
 108                 return 0;
 109         return cclk_frequency_100khz[PPCR & 0xf] * 100;
 110 }
 111
 112 /*
 113  * Default power-off for SA1100
 114  */
 115 static void sa1100_power_off(void)
 116 {
 117         mdelay(100);
 118         local_irq_disable();
 119         /* disable internal oscillator, float CS lines */
 120         PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
 121         /* enable wake-up on GPIO0 (Assabet...) */
 122         PWER = GFER = GRER = 1;
 123         /*
 124          * set scratchpad to zero, just in case it is used as a
 125          * restart address by the bootloader.
 126          */
 127         PSPR = 0;
 128         /* enter sleep mode */
 129         PMCR = PMCR_SF;
 130 }
 131
 132 void sa11x0_restart(char mode, const char *cmd)
 133 {
 134         if (mode == 's') {
 135                 /* Jump into ROM at address 0 */
 136                 soft_restart(0);
 137         } else {
 138                 /* Use on-chip reset capability */
 139                 RSRR = RSRR_SWR;
 140         }
 141 }
 142
 143 static void sa11x0_register_device(struct platform_device *dev, void *data)
 144 {
 145         int err;
 146         dev->dev.platform_data = data;
 147         err = platform_device_register(dev);
 148         if (err)
 149                 printk(KERN_ERR "Unable to register device %s: %d\n",
 150                         dev->name, err);
 151 }
 152
 153
 154 static struct resource sa11x0udc_resources[] = {
 155         [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
 156         [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
 157 };
 158
 159 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
 160
 161 static struct platform_device sa11x0udc_device = {
 162         .name           = "sa11x0-udc",
 163         .id             = -1,
 164         .dev            = {
 165                 .dma_mask = &sa11x0udc_dma_mask,
 166                 .coherent_dma_mask = 0xffffffff,
 167         },
 168         .num_resources  = ARRAY_SIZE(sa11x0udc_resources),
 169         .resource       = sa11x0udc_resources,
 170 };
 171
 172 static struct resource sa11x0uart1_resources[] = {
 173         [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
 174         [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
 175 };
 176
 177 static struct platform_device sa11x0uart1_device = {
 178         .name           = "sa11x0-uart",
 179         .id             = 1,
 180         .num_resources  = ARRAY_SIZE(sa11x0uart1_resources),
 181         .resource       = sa11x0uart1_resources,
 182 };
 183
 184 static struct resource sa11x0uart3_resources[] = {
 185         [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
 186         [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
 187 };
 188
 189 static struct platform_device sa11x0uart3_device = {
 190         .name           = "sa11x0-uart",
 191         .id             = 3,
 192         .num_resources  = ARRAY_SIZE(sa11x0uart3_resources),
 193         .resource       = sa11x0uart3_resources,
 194 };
 195
 196 static struct resource sa11x0mcp_resources[] = {
 197         [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
 198         [1] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
 199 };
 200
 201 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
 202
 203 static struct platform_device sa11x0mcp_device = {
 204         .name           = "sa11x0-mcp",
 205         .id             = -1,
 206         .dev = {
 207                 .dma_mask = &sa11x0mcp_dma_mask,
 208                 .coherent_dma_mask = 0xffffffff,
 209         },
 210         .num_resources  = ARRAY_SIZE(sa11x0mcp_resources),
 211         .resource       = sa11x0mcp_resources,
 212 };
 213
 214 void sa11x0_register_mcp(struct mcp_plat_data *data)
 215 {
 216         sa11x0_register_device(&sa11x0mcp_device, data);
 217 }
 218
 219 static struct resource sa11x0ssp_resources[] = {
 220         [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
 221         [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
 222 };
 223
 224 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
 225
 226 static struct platform_device sa11x0ssp_device = {
 227         .name           = "sa11x0-ssp",
 228         .id             = -1,
 229         .dev = {
 230                 .dma_mask = &sa11x0ssp_dma_mask,
 231                 .coherent_dma_mask = 0xffffffff,
 232         },
 233         .num_resources  = ARRAY_SIZE(sa11x0ssp_resources),
 234         .resource       = sa11x0ssp_resources,
 235 };
 236
 237 static struct resource sa11x0fb_resources[] = {
 238         [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
 239         [1] = DEFINE_RES_IRQ(IRQ_LCD),
 240 };
 241
 242 static struct platform_device sa11x0fb_device = {
 243         .name           = "sa11x0-fb",
 244         .id             = -1,
 245         .dev = {
 246                 .coherent_dma_mask = 0xffffffff,
 247         },
 248         .num_resources  = ARRAY_SIZE(sa11x0fb_resources),
 249         .resource       = sa11x0fb_resources,
 250 };
 251
 252 void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
 253 {
 254         sa11x0_register_device(&sa11x0fb_device, inf);
 255 }
 256
 257 static struct platform_device sa11x0pcmcia_device = {
 258         .name           = "sa11x0-pcmcia",
 259         .id             = -1,
 260 };
 261
 262 static struct platform_device sa11x0mtd_device = {
 263         .name           = "sa1100-mtd",
 264         .id             = -1,
 265 };
 266
 267 void sa11x0_register_mtd(struct flash_platform_data *flash,
 268                          struct resource *res, int nr)
 269 {
 270         flash->name = "sa1100";
 271         sa11x0mtd_device.resource = res;
 272         sa11x0mtd_device.num_resources = nr;
 273         sa11x0_register_device(&sa11x0mtd_device, flash);
 274 }
 275
 276 static struct resource sa11x0ir_resources[] = {
 277         DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
 278         DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
 279         DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
 280         DEFINE_RES_IRQ(IRQ_Ser2ICP),
 281 };
 282
 283 static struct platform_device sa11x0ir_device = {
 284         .name           = "sa11x0-ir",
 285         .id             = -1,
 286         .num_resources  = ARRAY_SIZE(sa11x0ir_resources),
 287         .resource       = sa11x0ir_resources,
 288 };
 289
 290 void sa11x0_register_irda(struct irda_platform_data *irda)
 291 {
 292         sa11x0_register_device(&sa11x0ir_device, irda);
 293 }
 294
 295 static struct platform_device sa11x0rtc_device = {
 296         .name           = "sa1100-rtc",
 297         .id             = -1,
 298 };
 299
 300 static struct resource sa11x0dma_resources[] = {
 301         DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
 302         DEFINE_RES_IRQ(IRQ_DMA0),
 303         DEFINE_RES_IRQ(IRQ_DMA1),
 304         DEFINE_RES_IRQ(IRQ_DMA2),
 305         DEFINE_RES_IRQ(IRQ_DMA3),
 306         DEFINE_RES_IRQ(IRQ_DMA4),
 307         DEFINE_RES_IRQ(IRQ_DMA5),
 308 };
 309
 310 static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
 311
 312 static struct platform_device sa11x0dma_device = {
 313         .name           = "sa11x0-dma",
 314         .id             = -1,
 315         .dev = {
 316                 .dma_mask = &sa11x0dma_dma_mask,
 317                 .coherent_dma_mask = 0xffffffff,
 318         },
 319         .num_resources  = ARRAY_SIZE(sa11x0dma_resources),
 320         .resource       = sa11x0dma_resources,
 321 };
 322
 323 static struct platform_device *sa11x0_devices[] __initdata = {
 324         &sa11x0udc_device,
 325         &sa11x0uart1_device,
 326         &sa11x0uart3_device,
 327         &sa11x0ssp_device,
 328         &sa11x0pcmcia_device,
 329         &sa11x0rtc_device,
 330         &sa11x0dma_device,
 331 };
 332
 333 static int __init sa1100_init(void)
 334 {
 335         pm_power_off = sa1100_power_off;
 336         return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
 337 }
 338
 339 arch_initcall(sa1100_init);
 340
 341
 342 /*
 343  * Common I/O mapping:
 344  *
 345  * Typically, static virtual address mappings are as follow:
 346  *
 347  * 0xf0000000-0xf3ffffff:       miscellaneous stuff (CPLDs, etc.)
 348  * 0xf4000000-0xf4ffffff:       SA-1111
 349  * 0xf5000000-0xf5ffffff:       reserved (used by cache flushing area)
 350  * 0xf6000000-0xfffeffff:       reserved (internal SA1100 IO defined above)
 351  * 0xffff0000-0xffff0fff:       SA1100 exception vectors
 352  * 0xffff2000-0xffff2fff:       Minicache copy_user_page area
 353  *
 354  * Below 0xe8000000 is reserved for vm allocation.
 355  *
 356  * The machine specific code must provide the extra mapping beside the
 357  * default mapping provided here.
 358  */
 359
 360 static struct map_desc standard_io_desc[] __initdata = {
 361         {       /* PCM */
 362                 .virtual        =  0xf8000000,
 363                 .pfn            = __phys_to_pfn(0x80000000),
 364                 .length         = 0x00100000,
 365                 .type           = MT_DEVICE
 366         }, {    /* SCM */
 367                 .virtual        =  0xfa000000,
 368                 .pfn            = __phys_to_pfn(0x90000000),
 369                 .length         = 0x00100000,
 370                 .type           = MT_DEVICE
 371         }, {    /* MER */
 372                 .virtual        =  0xfc000000,
 373                 .pfn            = __phys_to_pfn(0xa0000000),
 374                 .length         = 0x00100000,
 375                 .type           = MT_DEVICE
 376         }, {    /* LCD + DMA */
 377                 .virtual        =  0xfe000000,
 378                 .pfn            = __phys_to_pfn(0xb0000000),
 379                 .length         = 0x00200000,
 380                 .type           = MT_DEVICE
 381         },
 382 };
 383
 384 void __init sa1100_map_io(void)
 385 {
 386         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
 387 }
 388
 389 /*
 390  * Disable the memory bus request/grant signals on the SA1110 to
 391  * ensure that we don't receive spurious memory requests.  We set
 392  * the MBGNT signal false to ensure the SA1111 doesn't own the
 393  * SDRAM bus.
 394  */
 395 void sa1110_mb_disable(void)
 396 {
 397         unsigned long flags;
 398
 399         local_irq_save(flags);
 400
 401         PGSR &= ~GPIO_MBGNT;
 402         GPCR = GPIO_MBGNT;
 403         GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
 404
 405         GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
 406
 407         local_irq_restore(flags);
 408 }
 409
 410 /*
 411  * If the system is going to use the SA-1111 DMA engines, set up
 412  * the memory bus request/grant pins.
 413  */
 414 void sa1110_mb_enable(void)
 415 {
 416         unsigned long flags;
 417
 418         local_irq_save(flags);
 419
 420         PGSR &= ~GPIO_MBGNT;
 421         GPCR = GPIO_MBGNT;
 422         GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
 423
 424         GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
 425         TUCR |= TUCR_MR;
 426
 427         local_irq_restore(flags);
 428 }
 429