arch/arm/mach-sa1100/include/mach/memory.h

   1 /*
   2  * arch/arm/mach-sa1100/include/mach/memory.h
   3  *
   4  * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org>
   5  */
   6
   7 #ifndef __ASM_ARCH_MEMORY_H
   8 #define __ASM_ARCH_MEMORY_H
   9
  10 #include <asm/sizes.h>
  11
  12 /*
  13  * Physical DRAM offset is 0xc0000000 on the SA1100
  14  */
  15 #define PHYS_OFFSET     UL(0xc0000000)
  16
  17 #ifndef __ASSEMBLY__
  18
  19 #ifdef CONFIG_SA1111
  20 void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
  21
  22 #define arch_adjust_zones(node, size, holes) \
  23         sa1111_adjust_zones(node, size, holes)
  24
  25 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_1M - 1)
  26
  27 #endif
  28 #endif
  29
  30 /*
  31  * Virtual view <-> DMA view memory address translations
  32  * virt_to_bus: Used to translate the virtual address to an
  33  *              address suitable to be passed to set_dma_addr
  34  * bus_to_virt: Used to convert an address for DMA operations
  35  *              to an address that the kernel can use.
  36  *
  37  * On the SA1100, bus addresses are equivalent to physical addresses.
  38  */
  39 #define __virt_to_bus(x)         __virt_to_phys(x)
  40 #define __bus_to_virt(x)         __phys_to_virt(x)
  41
  42 /*
  43  * Because of the wide memory address space between physical RAM banks on the
  44  * SA1100, it's much convenient to use Linux's SparseMEM support to implement
  45  * our memory map representation.  Assuming all memory nodes have equal access
  46  * characteristics, we then have generic discontiguous memory support.
  47  *
  48  * The sparsemem banks are matched with the physical memory bank addresses
  49  * which are incidentally the same as virtual addresses.
  50  *
  51  *      node 0:  0xc0000000 - 0xc7ffffff
  52  *      node 1:  0xc8000000 - 0xcfffffff
  53  *      node 2:  0xd0000000 - 0xd7ffffff
  54  *      node 3:  0xd8000000 - 0xdfffffff
  55  */
  56 #define MAX_PHYSMEM_BITS        32
  57 #define SECTION_SIZE_BITS       27
  58
  59 /*
  60  * Cache flushing area - SA1100 zero bank
  61  */
  62 #define FLUSH_BASE_PHYS         0xe0000000
  63 #define FLUSH_BASE              0xf5000000
  64 #define FLUSH_BASE_MINICACHE    0xf5100000
  65
  66 #endif