arch/arm/mach-shmobile/setup-r8a7779.c

   1 /*
   2  * r8a7779 processor support
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_data/dma-rcar-hpbdma.h>
  29 #include <linux/platform_data/gpio-rcar.h>
  30 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/delay.h>
  33 #include <linux/input.h>
  34 #include <linux/io.h>
  35 #include <linux/serial_sci.h>
  36 #include <linux/sh_timer.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/usb/hcd.h>
  40 #include <linux/usb/ehci_pdriver.h>
  41 #include <linux/usb/ohci_pdriver.h>
  42 #include <linux/pm_runtime.h>
  43 #include <mach/r8a7779.h>
  44 #include <asm/mach-types.h>
  45 #include <asm/mach/arch.h>
  46 #include <asm/mach/time.h>
  47 #include <asm/mach/map.h>
  48 #include <asm/hardware/cache-l2x0.h>
  49 #include "common.h"
  50 #include "irqs.h"
  51
  52 static struct map_desc r8a7779_io_desc[] __initdata = {
  53         /* 2M entity map for 0xf0000000 (MPCORE) */
  54         {
  55                 .virtual        = 0xf0000000,
  56                 .pfn            = __phys_to_pfn(0xf0000000),
  57                 .length         = SZ_2M,
  58                 .type           = MT_DEVICE_NONSHARED
  59         },
  60         /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
  61         {
  62                 .virtual        = 0xfe000000,
  63                 .pfn            = __phys_to_pfn(0xfe000000),
  64                 .length         = SZ_16M,
  65                 .type           = MT_DEVICE_NONSHARED
  66         },
  67 };
  68
  69 void __init r8a7779_map_io(void)
  70 {
  71         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
  72 }
  73
  74 /* IRQ */
  75 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
  76 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
  77 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
  78 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
  79 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
  80
  81 #define INT2NTSR0 IOMEM(0xfe700060)
  82 #define INT2NTSR1 IOMEM(0xfe700064)
  83
  84 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
  85         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
  86         .sense_bitfield_width = 2,
  87 };
  88
  89 static struct resource irqpin0_resources[] __initdata = {
  90         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
  91         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
  92         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
  93         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
  94         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
  95         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
  96         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
  97         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
  98         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
  99 };
 100
 101 void __init r8a7779_init_irq_extpin_dt(int irlm)
 102 {
 103         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 104         u32 tmp;
 105
 106         if (!icr0) {
 107                 pr_warn("r8a7779: unable to setup external irq pin mode\n");
 108                 return;
 109         }
 110
 111         tmp = ioread32(icr0);
 112         if (irlm)
 113                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 114         else
 115                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 116         tmp |= (1 << 21); /* LVLMODE = 1 */
 117         iowrite32(tmp, icr0);
 118         iounmap(icr0);
 119 }
 120
 121 void __init r8a7779_init_irq_extpin(int irlm)
 122 {
 123         r8a7779_init_irq_extpin_dt(irlm);
 124         if (irlm)
 125                 platform_device_register_resndata(
 126                         NULL, "renesas_intc_irqpin", -1,
 127                         irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
 128                         &irqpin0_platform_data, sizeof(irqpin0_platform_data));
 129 }
 130
 131 /* PFC/GPIO */
 132 static struct resource r8a7779_pfc_resources[] = {
 133         DEFINE_RES_MEM(0xfffc0000, 0x023c),
 134 };
 135
 136 static struct platform_device r8a7779_pfc_device = {
 137         .name           = "pfc-r8a7779",
 138         .id             = -1,
 139         .resource       = r8a7779_pfc_resources,
 140         .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
 141 };
 142
 143 #define R8A7779_GPIO(idx, npins) \
 144 static struct resource r8a7779_gpio##idx##_resources[] = {              \
 145         DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
 146         DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 147 };                                                                      \
 148                                                                         \
 149 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
 150         .gpio_base      = 32 * (idx),                                   \
 151         .irq_base       = 0,                                            \
 152         .number_of_pins = npins,                                        \
 153         .pctl_name      = "pfc-r8a7779",                                \
 154 };                                                                      \
 155                                                                         \
 156 static struct platform_device r8a7779_gpio##idx##_device = {            \
 157         .name           = "gpio_rcar",                                  \
 158         .id             = idx,                                          \
 159         .resource       = r8a7779_gpio##idx##_resources,                \
 160         .num_resources  = ARRAY_SIZE(r8a7779_gpio##idx##_resources),    \
 161         .dev            = {                                             \
 162                 .platform_data  = &r8a7779_gpio##idx##_platform_data,   \
 163         },                                                              \
 164 }
 165
 166 R8A7779_GPIO(0, 32);
 167 R8A7779_GPIO(1, 32);
 168 R8A7779_GPIO(2, 32);
 169 R8A7779_GPIO(3, 32);
 170 R8A7779_GPIO(4, 32);
 171 R8A7779_GPIO(5, 32);
 172 R8A7779_GPIO(6, 9);
 173
 174 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
 175         &r8a7779_pfc_device,
 176         &r8a7779_gpio0_device,
 177         &r8a7779_gpio1_device,
 178         &r8a7779_gpio2_device,
 179         &r8a7779_gpio3_device,
 180         &r8a7779_gpio4_device,
 181         &r8a7779_gpio5_device,
 182         &r8a7779_gpio6_device,
 183 };
 184
 185 void __init r8a7779_pinmux_init(void)
 186 {
 187         platform_add_devices(r8a7779_pinctrl_devices,
 188                             ARRAY_SIZE(r8a7779_pinctrl_devices));
 189 }
 190
 191 /* SCIF */
 192 #define R8A7779_SCIF(index, baseaddr, irq)                      \
 193 static struct plat_sci_port scif##index##_platform_data = {     \
 194         .type           = PORT_SCIF,                            \
 195         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
 196         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
 197 };                                                              \
 198                                                                 \
 199 static struct resource scif##index##_resources[] = {            \
 200         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 201         DEFINE_RES_IRQ(irq),                                    \
 202 };                                                              \
 203                                                                 \
 204 static struct platform_device scif##index##_device = {          \
 205         .name           = "sh-sci",                             \
 206         .id             = index,                                \
 207         .resource       = scif##index##_resources,              \
 208         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 209         .dev            = {                                     \
 210                 .platform_data  = &scif##index##_platform_data, \
 211         },                                                      \
 212 }
 213
 214 R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
 215 R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
 216 R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
 217 R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
 218 R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
 219 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
 220
 221 /* TMU */
 222 static struct sh_timer_config tmu0_platform_data = {
 223         .channels_mask = 7,
 224 };
 225
 226 static struct resource tmu0_resources[] = {
 227         DEFINE_RES_MEM(0xffd80000, 0x30),
 228         DEFINE_RES_IRQ(gic_iid(0x40)),
 229         DEFINE_RES_IRQ(gic_iid(0x41)),
 230         DEFINE_RES_IRQ(gic_iid(0x42)),
 231 };
 232
 233 static struct platform_device tmu0_device = {
 234         .name           = "sh-tmu",
 235         .id             = 0,
 236         .dev = {
 237                 .platform_data  = &tmu0_platform_data,
 238         },
 239         .resource       = tmu0_resources,
 240         .num_resources  = ARRAY_SIZE(tmu0_resources),
 241 };
 242
 243 /* I2C */
 244 static struct resource rcar_i2c0_res[] = {
 245         {
 246                 .start  = 0xffc70000,
 247                 .end    = 0xffc70fff,
 248                 .flags  = IORESOURCE_MEM,
 249         }, {
 250                 .start  = gic_iid(0x6f),
 251                 .flags  = IORESOURCE_IRQ,
 252         },
 253 };
 254
 255 static struct platform_device i2c0_device = {
 256         .name           = "i2c-rcar",
 257         .id             = 0,
 258         .resource       = rcar_i2c0_res,
 259         .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
 260 };
 261
 262 static struct resource rcar_i2c1_res[] = {
 263         {
 264                 .start  = 0xffc71000,
 265                 .end    = 0xffc71fff,
 266                 .flags  = IORESOURCE_MEM,
 267         }, {
 268                 .start  = gic_iid(0x72),
 269                 .flags  = IORESOURCE_IRQ,
 270         },
 271 };
 272
 273 static struct platform_device i2c1_device = {
 274         .name           = "i2c-rcar",
 275         .id             = 1,
 276         .resource       = rcar_i2c1_res,
 277         .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
 278 };
 279
 280 static struct resource rcar_i2c2_res[] = {
 281         {
 282                 .start  = 0xffc72000,
 283                 .end    = 0xffc72fff,
 284                 .flags  = IORESOURCE_MEM,
 285         }, {
 286                 .start  = gic_iid(0x70),
 287                 .flags  = IORESOURCE_IRQ,
 288         },
 289 };
 290
 291 static struct platform_device i2c2_device = {
 292         .name           = "i2c-rcar",
 293         .id             = 2,
 294         .resource       = rcar_i2c2_res,
 295         .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
 296 };
 297
 298 static struct resource rcar_i2c3_res[] = {
 299         {
 300                 .start  = 0xffc73000,
 301                 .end    = 0xffc73fff,
 302                 .flags  = IORESOURCE_MEM,
 303         }, {
 304                 .start  = gic_iid(0x71),
 305                 .flags  = IORESOURCE_IRQ,
 306         },
 307 };
 308
 309 static struct platform_device i2c3_device = {
 310         .name           = "i2c-rcar",
 311         .id             = 3,
 312         .resource       = rcar_i2c3_res,
 313         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 314 };
 315
 316 static struct resource sata_resources[] = {
 317         [0] = {
 318                 .name   = "rcar-sata",
 319                 .start  = 0xfc600000,
 320                 .end    = 0xfc601fff,
 321                 .flags  = IORESOURCE_MEM,
 322         },
 323         [1] = {
 324                 .start  = gic_iid(0x84),
 325                 .flags  = IORESOURCE_IRQ,
 326         },
 327 };
 328
 329 static struct platform_device sata_device = {
 330         .name           = "sata_rcar",
 331         .id             = -1,
 332         .resource       = sata_resources,
 333         .num_resources  = ARRAY_SIZE(sata_resources),
 334         .dev            = {
 335                 .dma_mask               = &sata_device.dev.coherent_dma_mask,
 336                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 337         },
 338 };
 339
 340 /* USB */
 341 static struct usb_phy *phy;
 342
 343 static int usb_power_on(struct platform_device *pdev)
 344 {
 345         if (IS_ERR(phy))
 346                 return PTR_ERR(phy);
 347
 348         pm_runtime_enable(&pdev->dev);
 349         pm_runtime_get_sync(&pdev->dev);
 350
 351         usb_phy_init(phy);
 352
 353         return 0;
 354 }
 355
 356 static void usb_power_off(struct platform_device *pdev)
 357 {
 358         if (IS_ERR(phy))
 359                 return;
 360
 361         usb_phy_shutdown(phy);
 362
 363         pm_runtime_put_sync(&pdev->dev);
 364         pm_runtime_disable(&pdev->dev);
 365 }
 366
 367 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 368 {
 369         /*
 370          * Below are recommended values from the datasheet;
 371          * see [USB :: Setting of EHCI Internal Buffer].
 372          */
 373         /* EHCI IP internal buffer setting */
 374         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 375         /* EHCI IP internal buffer enable */
 376         iowrite32(0x00000001, hcd->regs + 0x009C);
 377
 378         return 0;
 379 }
 380
 381 static struct usb_ehci_pdata ehcix_pdata = {
 382         .power_on       = usb_power_on,
 383         .power_off      = usb_power_off,
 384         .power_suspend  = usb_power_off,
 385         .pre_setup      = ehci_init_internal_buffer,
 386 };
 387
 388 static struct resource ehci0_resources[] = {
 389         [0] = {
 390                 .start  = 0xffe70000,
 391                 .end    = 0xffe70400 - 1,
 392                 .flags  = IORESOURCE_MEM,
 393         },
 394         [1] = {
 395                 .start  = gic_iid(0x4c),
 396                 .flags  = IORESOURCE_IRQ,
 397         },
 398 };
 399
 400 static struct platform_device ehci0_device = {
 401         .name   = "ehci-platform",
 402         .id     = 0,
 403         .dev    = {
 404                 .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
 405                 .coherent_dma_mask      = 0xffffffff,
 406                 .platform_data          = &ehcix_pdata,
 407         },
 408         .num_resources  = ARRAY_SIZE(ehci0_resources),
 409         .resource       = ehci0_resources,
 410 };
 411
 412 static struct resource ehci1_resources[] = {
 413         [0] = {
 414                 .start  = 0xfff70000,
 415                 .end    = 0xfff70400 - 1,
 416                 .flags  = IORESOURCE_MEM,
 417         },
 418         [1] = {
 419                 .start  = gic_iid(0x4d),
 420                 .flags  = IORESOURCE_IRQ,
 421         },
 422 };
 423
 424 static struct platform_device ehci1_device = {
 425         .name   = "ehci-platform",
 426         .id     = 1,
 427         .dev    = {
 428                 .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
 429                 .coherent_dma_mask      = 0xffffffff,
 430                 .platform_data          = &ehcix_pdata,
 431         },
 432         .num_resources  = ARRAY_SIZE(ehci1_resources),
 433         .resource       = ehci1_resources,
 434 };
 435
 436 static struct usb_ohci_pdata ohcix_pdata = {
 437         .power_on       = usb_power_on,
 438         .power_off      = usb_power_off,
 439         .power_suspend  = usb_power_off,
 440 };
 441
 442 static struct resource ohci0_resources[] = {
 443         [0] = {
 444                 .start  = 0xffe70400,
 445                 .end    = 0xffe70800 - 1,
 446                 .flags  = IORESOURCE_MEM,
 447         },
 448         [1] = {
 449                 .start  = gic_iid(0x4c),
 450                 .flags  = IORESOURCE_IRQ,
 451         },
 452 };
 453
 454 static struct platform_device ohci0_device = {
 455         .name   = "ohci-platform",
 456         .id     = 0,
 457         .dev    = {
 458                 .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
 459                 .coherent_dma_mask      = 0xffffffff,
 460                 .platform_data          = &ohcix_pdata,
 461         },
 462         .num_resources  = ARRAY_SIZE(ohci0_resources),
 463         .resource       = ohci0_resources,
 464 };
 465
 466 static struct resource ohci1_resources[] = {
 467         [0] = {
 468                 .start  = 0xfff70400,
 469                 .end    = 0xfff70800 - 1,
 470                 .flags  = IORESOURCE_MEM,
 471         },
 472         [1] = {
 473                 .start  = gic_iid(0x4d),
 474                 .flags  = IORESOURCE_IRQ,
 475         },
 476 };
 477
 478 static struct platform_device ohci1_device = {
 479         .name   = "ohci-platform",
 480         .id     = 1,
 481         .dev    = {
 482                 .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
 483                 .coherent_dma_mask      = 0xffffffff,
 484                 .platform_data          = &ohcix_pdata,
 485         },
 486         .num_resources  = ARRAY_SIZE(ohci1_resources),
 487         .resource       = ohci1_resources,
 488 };
 489
 490 /* HPB-DMA */
 491
 492 /* Asynchronous mode register bits */
 493 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK           BIT(23) /* MMC1 */
 494 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE         BIT(23) /* MMC1 */
 495 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI          0       /* MMC1 */
 496 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK         BIT(22) /* MMC1 */
 497 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST        BIT(22) /* MMC1 */
 498 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST       0       /* MMC1 */
 499 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK           BIT(21) /* MMC0 */
 500 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE         BIT(21) /* MMC0 */
 501 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI          0       /* MMC0 */
 502 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK         BIT(20) /* MMC0 */
 503 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST        BIT(20) /* MMC0 */
 504 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST       0       /* MMC0 */
 505 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK           BIT(19) /* SDHI3 */
 506 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE         BIT(19) /* SDHI3 */
 507 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI          0       /* SDHI3 */
 508 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK         BIT(18) /* SDHI3 */
 509 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST        BIT(18) /* SDHI3 */
 510 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST       0       /* SDHI3 */
 511 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK           BIT(17) /* SDHI3 */
 512 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE         BIT(17) /* SDHI3 */
 513 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI          0       /* SDHI3 */
 514 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK         BIT(16) /* SDHI3 */
 515 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST        BIT(16) /* SDHI3 */
 516 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST       0       /* SDHI3 */
 517 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK           BIT(15) /* SDHI3 */
 518 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE         BIT(15) /* SDHI3 */
 519 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI          0       /* SDHI3 */
 520 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK         BIT(14) /* SDHI3 */
 521 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST        BIT(14) /* SDHI3 */
 522 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST       0       /* SDHI3 */
 523 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK           BIT(13) /* SDHI2 */
 524 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE         BIT(13) /* SDHI2 */
 525 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI          0       /* SDHI2 */
 526 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK         BIT(12) /* SDHI2 */
 527 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST        BIT(12) /* SDHI2 */
 528 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST       0       /* SDHI2 */
 529 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK           BIT(11) /* SDHI2 */
 530 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE         BIT(11) /* SDHI2 */
 531 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI          0       /* SDHI2 */
 532 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK         BIT(10) /* SDHI2 */
 533 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST        BIT(10) /* SDHI2 */
 534 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST       0       /* SDHI2 */
 535 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK           BIT(9)  /* SDHI2 */
 536 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE         BIT(9)  /* SDHI2 */
 537 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI          0       /* SDHI2 */
 538 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK         BIT(8)  /* SDHI2 */
 539 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST        BIT(8)  /* SDHI2 */
 540 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST       0       /* SDHI2 */
 541 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK           BIT(7)  /* SDHI0 */
 542 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE         BIT(7)  /* SDHI0 */
 543 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI          0       /* SDHI0 */
 544 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK         BIT(6)  /* SDHI0 */
 545 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST        BIT(6)  /* SDHI0 */
 546 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST       0       /* SDHI0 */
 547 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK           BIT(5)  /* SDHI0 */
 548 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE         BIT(5)  /* SDHI0 */
 549 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI          0       /* SDHI0 */
 550 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK         BIT(4)  /* SDHI0 */
 551 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST        BIT(4)  /* SDHI0 */
 552 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST       0       /* SDHI0 */
 553 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK           BIT(3)  /* SDHI0 */
 554 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE         BIT(3)  /* SDHI0 */
 555 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI          0       /* SDHI0 */
 556 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK         BIT(2)  /* SDHI0 */
 557 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST        BIT(2)  /* SDHI0 */
 558 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST       0       /* SDHI0 */
 559 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK           BIT(1)  /* SDHI1 */
 560 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE         BIT(1)  /* SDHI1 */
 561 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI          0       /* SDHI1 */
 562 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK         BIT(0)  /* SDHI1 */
 563 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST        BIT(0)  /* SDHI1 */
 564 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST       0       /* SDHI1 */
 565
 566 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 567         {
 568                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 569                 .addr   = 0xffe4c000 + 0x30,
 570                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 571                           HPB_DMAE_DCR_DMDL |
 572                           HPB_DMAE_DCR_DPDS_16BIT,
 573                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 574                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 575                           HPB_DMAE_ASYNCRSTR_ASRST23,
 576                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
 577                           HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
 578                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
 579                           HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
 580                 .port   = 0x0D0C,
 581                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 582                 .dma_ch = 21,
 583         }, {
 584                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 585                 .addr   = 0xffe4c000 + 0x30,
 586                 .dcr    = HPB_DMAE_DCR_SMDL |
 587                           HPB_DMAE_DCR_SPDS_16BIT |
 588                           HPB_DMAE_DCR_DPDS_16BIT,
 589                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 590                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 591                           HPB_DMAE_ASYNCRSTR_ASRST23,
 592                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
 593                           HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
 594                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
 595                           HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
 596                 .port   = 0x0D0C,
 597                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 598                 .dma_ch = 22,
 599         },
 600 };
 601
 602 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 603         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 604         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 605 };
 606
 607 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 608         .slaves                 = hpb_dmae_slaves,
 609         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 610         .channels               = hpb_dmae_channels,
 611         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 612         .ts_shift               = {
 613                 [XMIT_SZ_8BIT]  = 0,
 614                 [XMIT_SZ_16BIT] = 1,
 615                 [XMIT_SZ_32BIT] = 2,
 616         },
 617         .num_hw_channels        = 44,
 618 };
 619
 620 static struct resource hpb_dmae_resources[] __initdata = {
 621         /* Channel registers */
 622         DEFINE_RES_MEM(0xffc08000, 0x1000),
 623         /* Common registers */
 624         DEFINE_RES_MEM(0xffc09000, 0x170),
 625         /* Asynchronous reset registers */
 626         DEFINE_RES_MEM(0xffc00300, 4),
 627         /* Asynchronous mode registers */
 628         DEFINE_RES_MEM(0xffc00400, 4),
 629         /* IRQ for DMA channels */
 630         DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
 631 };
 632
 633 static void __init r8a7779_register_hpb_dmae(void)
 634 {
 635         platform_device_register_resndata(NULL, "hpb-dma-engine",
 636                                           -1, hpb_dmae_resources,
 637                                           ARRAY_SIZE(hpb_dmae_resources),
 638                                           &dma_platform_data,
 639                                           sizeof(dma_platform_data));
 640 }
 641
 642 static struct platform_device *r8a7779_devices_dt[] __initdata = {
 643         &scif0_device,
 644         &scif1_device,
 645         &scif2_device,
 646         &scif3_device,
 647         &scif4_device,
 648         &scif5_device,
 649         &tmu0_device,
 650 };
 651
 652 static struct platform_device *r8a7779_standard_devices[] __initdata = {
 653         &i2c0_device,
 654         &i2c1_device,
 655         &i2c2_device,
 656         &i2c3_device,
 657         &sata_device,
 658 };
 659
 660 void __init r8a7779_add_standard_devices(void)
 661 {
 662 #ifdef CONFIG_CACHE_L2X0
 663         /* Shared attribute override enable, 64K*16way */
 664         l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 665 #endif
 666         r8a7779_pm_init();
 667
 668         r8a7779_init_pm_domains();
 669
 670         platform_add_devices(r8a7779_devices_dt,
 671                             ARRAY_SIZE(r8a7779_devices_dt));
 672         platform_add_devices(r8a7779_standard_devices,
 673                             ARRAY_SIZE(r8a7779_standard_devices));
 674         r8a7779_register_hpb_dmae();
 675 }
 676
 677 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 678 void __init __weak r8a7779_register_twd(void) { }
 679
 680 void __init r8a7779_earlytimer_init(void)
 681 {
 682         r8a7779_clock_init();
 683         r8a7779_register_twd();
 684         shmobile_earlytimer_init();
 685 }
 686
 687 void __init r8a7779_add_early_devices(void)
 688 {
 689         early_platform_add_devices(r8a7779_devices_dt,
 690                                    ARRAY_SIZE(r8a7779_devices_dt));
 691
 692         /* Early serial console setup is not included here due to
 693          * memory map collisions. The SCIF serial ports in r8a7779
 694          * are difficult to entity map 1:1 due to collision with the
 695          * virtual memory range used by the coherent DMA code on ARM.
 696          *
 697          * Anyone wanting to debug early can remove UPF_IOREMAP from
 698          * the sh-sci serial console platform data, adjust mapbase
 699          * to a static M:N virt:phys mapping that needs to be added to
 700          * the mappings passed with iotable_init() above.
 701          *
 702          * Then add a call to shmobile_setup_console() from this function.
 703          *
 704          * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
 705          * command line in case of the marzen board.
 706          */
 707 }
 708
 709 static struct platform_device *r8a7779_late_devices[] __initdata = {
 710         &ehci0_device,
 711         &ehci1_device,
 712         &ohci0_device,
 713         &ohci1_device,
 714 };
 715
 716 void __init r8a7779_init_late(void)
 717 {
 718         /* get USB PHY */
 719         phy = usb_get_phy(USB_PHY_TYPE_USB2);
 720
 721         shmobile_init_late();
 722         platform_add_devices(r8a7779_late_devices,
 723                              ARRAY_SIZE(r8a7779_late_devices));
 724 }
 725
 726 #ifdef CONFIG_USE_OF
 727 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 728 {
 729         return 0; /* always allow wakeup */
 730 }
 731
 732 void __init r8a7779_init_irq_dt(void)
 733 {
 734         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 735
 736         irqchip_init();
 737
 738         /* route all interrupts to ARM */
 739         __raw_writel(0xffffffff, INT2NTSR0);
 740         __raw_writel(0x3fffffff, INT2NTSR1);
 741
 742         /* unmask all known interrupts in INTCS2 */
 743         __raw_writel(0xfffffff0, INT2SMSKCR0);
 744         __raw_writel(0xfff7ffff, INT2SMSKCR1);
 745         __raw_writel(0xfffbffdf, INT2SMSKCR2);
 746         __raw_writel(0xbffffffc, INT2SMSKCR3);
 747         __raw_writel(0x003fee3f, INT2SMSKCR4);
 748 }
 749
 750 void __init r8a7779_init_delay(void)
 751 {
 752         shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
 753 }
 754
 755 void __init r8a7779_add_standard_devices_dt(void)
 756 {
 757         /* clocks are setup late during boot in the case of DT */
 758         r8a7779_clock_init();
 759
 760         platform_add_devices(r8a7779_devices_dt,
 761                              ARRAY_SIZE(r8a7779_devices_dt));
 762         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 763 }
 764
 765 static const char *r8a7779_compat_dt[] __initdata = {
 766         "renesas,r8a7779",
 767         NULL,
 768 };
 769
 770 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
 771         .map_io         = r8a7779_map_io,
 772         .init_early     = r8a7779_init_delay,
 773         .nr_irqs        = NR_IRQS_LEGACY,
 774         .init_irq       = r8a7779_init_irq_dt,
 775         .init_machine   = r8a7779_add_standard_devices_dt,
 776         .init_late      = r8a7779_init_late,
 777         .dt_compat      = r8a7779_compat_dt,
 778 MACHINE_END
 779 #endif /* CONFIG_USE_OF */