2 * r8a7779 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
26 #include <linux/input.h>
28 #include <linux/serial_sci.h>
29 #include <linux/sh_intc.h>
30 #include <linux/sh_timer.h>
31 #include <mach/hardware.h>
32 #include <mach/irqs.h>
33 #include <mach/r8a7779.h>
34 #include <mach/common.h>
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/time.h>
38 #include <asm/mach/map.h>
39 #include <asm/hardware/cache-l2x0.h>
41 static struct map_desc r8a7779_io_desc
[] __initdata
= {
42 /* 2M entity map for 0xf0000000 (MPCORE) */
44 .virtual = 0xf0000000,
45 .pfn
= __phys_to_pfn(0xf0000000),
47 .type
= MT_DEVICE_NONSHARED
49 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
51 .virtual = 0xfe000000,
52 .pfn
= __phys_to_pfn(0xfe000000),
54 .type
= MT_DEVICE_NONSHARED
58 void __init
r8a7779_map_io(void)
60 iotable_init(r8a7779_io_desc
, ARRAY_SIZE(r8a7779_io_desc
));
63 static struct plat_sci_port scif0_platform_data
= {
64 .mapbase
= 0xffe40000,
65 .flags
= UPF_BOOT_AUTOCONF
| UPF_IOREMAP
,
66 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
67 .scbrr_algo_id
= SCBRR_ALGO_2
,
69 .irqs
= { gic_spi(88), gic_spi(88),
70 gic_spi(88), gic_spi(88) },
73 static struct platform_device scif0_device
= {
77 .platform_data
= &scif0_platform_data
,
81 static struct plat_sci_port scif1_platform_data
= {
82 .mapbase
= 0xffe41000,
83 .flags
= UPF_BOOT_AUTOCONF
| UPF_IOREMAP
,
84 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
85 .scbrr_algo_id
= SCBRR_ALGO_2
,
87 .irqs
= { gic_spi(89), gic_spi(89),
88 gic_spi(89), gic_spi(89) },
91 static struct platform_device scif1_device
= {
95 .platform_data
= &scif1_platform_data
,
99 static struct plat_sci_port scif2_platform_data
= {
100 .mapbase
= 0xffe42000,
101 .flags
= UPF_BOOT_AUTOCONF
| UPF_IOREMAP
,
102 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
103 .scbrr_algo_id
= SCBRR_ALGO_2
,
105 .irqs
= { gic_spi(90), gic_spi(90),
106 gic_spi(90), gic_spi(90) },
109 static struct platform_device scif2_device
= {
113 .platform_data
= &scif2_platform_data
,
117 static struct plat_sci_port scif3_platform_data
= {
118 .mapbase
= 0xffe43000,
119 .flags
= UPF_BOOT_AUTOCONF
| UPF_IOREMAP
,
120 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
121 .scbrr_algo_id
= SCBRR_ALGO_2
,
123 .irqs
= { gic_spi(91), gic_spi(91),
124 gic_spi(91), gic_spi(91) },
127 static struct platform_device scif3_device
= {
131 .platform_data
= &scif3_platform_data
,
135 static struct plat_sci_port scif4_platform_data
= {
136 .mapbase
= 0xffe44000,
137 .flags
= UPF_BOOT_AUTOCONF
| UPF_IOREMAP
,
138 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
139 .scbrr_algo_id
= SCBRR_ALGO_2
,
141 .irqs
= { gic_spi(92), gic_spi(92),
142 gic_spi(92), gic_spi(92) },
145 static struct platform_device scif4_device
= {
149 .platform_data
= &scif4_platform_data
,
153 static struct plat_sci_port scif5_platform_data
= {
154 .mapbase
= 0xffe45000,
155 .flags
= UPF_BOOT_AUTOCONF
| UPF_IOREMAP
,
156 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
157 .scbrr_algo_id
= SCBRR_ALGO_2
,
159 .irqs
= { gic_spi(93), gic_spi(93),
160 gic_spi(93), gic_spi(93) },
163 static struct platform_device scif5_device
= {
167 .platform_data
= &scif5_platform_data
,
172 static struct sh_timer_config tmu00_platform_data
= {
174 .channel_offset
= 0x4,
176 .clockevent_rating
= 200,
179 static struct resource tmu00_resources
[] = {
184 .flags
= IORESOURCE_MEM
,
187 .start
= gic_spi(32),
188 .flags
= IORESOURCE_IRQ
,
192 static struct platform_device tmu00_device
= {
196 .platform_data
= &tmu00_platform_data
,
198 .resource
= tmu00_resources
,
199 .num_resources
= ARRAY_SIZE(tmu00_resources
),
202 static struct sh_timer_config tmu01_platform_data
= {
204 .channel_offset
= 0x10,
206 .clocksource_rating
= 200,
209 static struct resource tmu01_resources
[] = {
214 .flags
= IORESOURCE_MEM
,
217 .start
= gic_spi(33),
218 .flags
= IORESOURCE_IRQ
,
222 static struct platform_device tmu01_device
= {
226 .platform_data
= &tmu01_platform_data
,
228 .resource
= tmu01_resources
,
229 .num_resources
= ARRAY_SIZE(tmu01_resources
),
233 static struct resource rcar_i2c0_res
[] = {
237 .flags
= IORESOURCE_MEM
,
239 .start
= gic_spi(79),
240 .flags
= IORESOURCE_IRQ
,
244 static struct platform_device i2c0_device
= {
247 .resource
= rcar_i2c0_res
,
248 .num_resources
= ARRAY_SIZE(rcar_i2c0_res
),
251 static struct resource rcar_i2c1_res
[] = {
255 .flags
= IORESOURCE_MEM
,
257 .start
= gic_spi(82),
258 .flags
= IORESOURCE_IRQ
,
262 static struct platform_device i2c1_device
= {
265 .resource
= rcar_i2c1_res
,
266 .num_resources
= ARRAY_SIZE(rcar_i2c1_res
),
269 static struct resource rcar_i2c2_res
[] = {
273 .flags
= IORESOURCE_MEM
,
275 .start
= gic_spi(80),
276 .flags
= IORESOURCE_IRQ
,
280 static struct platform_device i2c2_device
= {
283 .resource
= rcar_i2c2_res
,
284 .num_resources
= ARRAY_SIZE(rcar_i2c2_res
),
287 static struct resource rcar_i2c3_res
[] = {
291 .flags
= IORESOURCE_MEM
,
293 .start
= gic_spi(81),
294 .flags
= IORESOURCE_IRQ
,
298 static struct platform_device i2c3_device
= {
301 .resource
= rcar_i2c3_res
,
302 .num_resources
= ARRAY_SIZE(rcar_i2c3_res
),
305 static struct platform_device
*r8a7779_early_devices
[] __initdata
= {
320 static struct platform_device
*r8a7779_late_devices
[] __initdata
= {
323 void __init
r8a7779_add_standard_devices(void)
325 #ifdef CONFIG_CACHE_L2X0
326 /* Early BRESP enable, Shared attribute override enable, 64K*16way */
327 l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
331 r8a7779_init_pm_domains();
333 platform_add_devices(r8a7779_early_devices
,
334 ARRAY_SIZE(r8a7779_early_devices
));
335 platform_add_devices(r8a7779_late_devices
,
336 ARRAY_SIZE(r8a7779_late_devices
));
339 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
340 void __init __weak
r8a7779_register_twd(void) { }
342 void __init
r8a7779_earlytimer_init(void)
344 r8a7779_clock_init();
345 shmobile_earlytimer_init();
346 r8a7779_register_twd();
349 void __init
r8a7779_add_early_devices(void)
351 early_platform_add_devices(r8a7779_early_devices
,
352 ARRAY_SIZE(r8a7779_early_devices
));
354 /* Early serial console setup is not included here due to
355 * memory map collisions. The SCIF serial ports in r8a7779
356 * are difficult to entity map 1:1 due to collision with the
357 * virtual memory range used by the coherent DMA code on ARM.
359 * Anyone wanting to debug early can remove UPF_IOREMAP from
360 * the sh-sci serial console platform data, adjust mapbase
361 * to a static M:N virt:phys mapping that needs to be added to
362 * the mappings passed with iotable_init() above.
364 * Then add a call to shmobile_setup_console() from this function.
366 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
367 * command line in case of the marzen board.