2 * sh7377 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_intc.h>
31 #include <linux/sh_timer.h>
32 #include <mach/hardware.h>
33 #include <mach/common.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/time.h>
39 static struct map_desc sh7377_io_desc
[] __initdata
= {
40 /* create a 1:1 entity map for 0xe6xxxxxx
41 * used by CPGA, INTC and PFC.
44 .virtual = 0xe6000000,
45 .pfn
= __phys_to_pfn(0xe6000000),
47 .type
= MT_DEVICE_NONSHARED
51 void __init
sh7377_map_io(void)
53 iotable_init(sh7377_io_desc
, ARRAY_SIZE(sh7377_io_desc
));
57 static struct plat_sci_port scif0_platform_data
= {
58 .mapbase
= 0xe6c40000,
59 .flags
= UPF_BOOT_AUTOCONF
,
60 .scscr
= SCSCR_RE
| SCSCR_TE
,
61 .scbrr_algo_id
= SCBRR_ALGO_4
,
63 .irqs
= { evt2irq(0xc00), evt2irq(0xc00),
64 evt2irq(0xc00), evt2irq(0xc00) },
67 static struct platform_device scif0_device
= {
71 .platform_data
= &scif0_platform_data
,
76 static struct plat_sci_port scif1_platform_data
= {
77 .mapbase
= 0xe6c50000,
78 .flags
= UPF_BOOT_AUTOCONF
,
79 .scscr
= SCSCR_RE
| SCSCR_TE
,
80 .scbrr_algo_id
= SCBRR_ALGO_4
,
82 .irqs
= { evt2irq(0xc20), evt2irq(0xc20),
83 evt2irq(0xc20), evt2irq(0xc20) },
86 static struct platform_device scif1_device
= {
90 .platform_data
= &scif1_platform_data
,
95 static struct plat_sci_port scif2_platform_data
= {
96 .mapbase
= 0xe6c60000,
97 .flags
= UPF_BOOT_AUTOCONF
,
98 .scscr
= SCSCR_RE
| SCSCR_TE
,
99 .scbrr_algo_id
= SCBRR_ALGO_4
,
101 .irqs
= { evt2irq(0xc40), evt2irq(0xc40),
102 evt2irq(0xc40), evt2irq(0xc40) },
105 static struct platform_device scif2_device
= {
109 .platform_data
= &scif2_platform_data
,
114 static struct plat_sci_port scif3_platform_data
= {
115 .mapbase
= 0xe6c70000,
116 .flags
= UPF_BOOT_AUTOCONF
,
117 .scscr
= SCSCR_RE
| SCSCR_TE
,
118 .scbrr_algo_id
= SCBRR_ALGO_4
,
120 .irqs
= { evt2irq(0xc60), evt2irq(0xc60),
121 evt2irq(0xc60), evt2irq(0xc60) },
124 static struct platform_device scif3_device
= {
128 .platform_data
= &scif3_platform_data
,
133 static struct plat_sci_port scif4_platform_data
= {
134 .mapbase
= 0xe6c80000,
135 .flags
= UPF_BOOT_AUTOCONF
,
136 .scscr
= SCSCR_RE
| SCSCR_TE
,
137 .scbrr_algo_id
= SCBRR_ALGO_4
,
139 .irqs
= { evt2irq(0xd20), evt2irq(0xd20),
140 evt2irq(0xd20), evt2irq(0xd20) },
143 static struct platform_device scif4_device
= {
147 .platform_data
= &scif4_platform_data
,
152 static struct plat_sci_port scif5_platform_data
= {
153 .mapbase
= 0xe6cb0000,
154 .flags
= UPF_BOOT_AUTOCONF
,
155 .scscr
= SCSCR_RE
| SCSCR_TE
,
156 .scbrr_algo_id
= SCBRR_ALGO_4
,
158 .irqs
= { evt2irq(0xd40), evt2irq(0xd40),
159 evt2irq(0xd40), evt2irq(0xd40) },
162 static struct platform_device scif5_device
= {
166 .platform_data
= &scif5_platform_data
,
171 static struct plat_sci_port scif6_platform_data
= {
172 .mapbase
= 0xe6cc0000,
173 .flags
= UPF_BOOT_AUTOCONF
,
174 .scscr
= SCSCR_RE
| SCSCR_TE
,
175 .scbrr_algo_id
= SCBRR_ALGO_4
,
177 .irqs
= { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
178 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
181 static struct platform_device scif6_device
= {
185 .platform_data
= &scif6_platform_data
,
190 static struct plat_sci_port scif7_platform_data
= {
191 .mapbase
= 0xe6c30000,
192 .flags
= UPF_BOOT_AUTOCONF
,
193 .scscr
= SCSCR_RE
| SCSCR_TE
,
194 .scbrr_algo_id
= SCBRR_ALGO_4
,
196 .irqs
= { evt2irq(0xd60), evt2irq(0xd60),
197 evt2irq(0xd60), evt2irq(0xd60) },
200 static struct platform_device scif7_device
= {
204 .platform_data
= &scif7_platform_data
,
208 static struct sh_timer_config cmt10_platform_data
= {
210 .channel_offset
= 0x10,
212 .clockevent_rating
= 125,
213 .clocksource_rating
= 125,
216 static struct resource cmt10_resources
[] = {
221 .flags
= IORESOURCE_MEM
,
224 .start
= evt2irq(0xb00), /* CMT1_CMT10 */
225 .flags
= IORESOURCE_IRQ
,
229 static struct platform_device cmt10_device
= {
233 .platform_data
= &cmt10_platform_data
,
235 .resource
= cmt10_resources
,
236 .num_resources
= ARRAY_SIZE(cmt10_resources
),
240 static struct uio_info vpu_platform_data
= {
243 .irq
= intcs_evt2irq(0x980),
246 static struct resource vpu_resources
[] = {
251 .flags
= IORESOURCE_MEM
,
255 static struct platform_device vpu_device
= {
256 .name
= "uio_pdrv_genirq",
259 .platform_data
= &vpu_platform_data
,
261 .resource
= vpu_resources
,
262 .num_resources
= ARRAY_SIZE(vpu_resources
),
266 static struct uio_info veu0_platform_data
= {
269 .irq
= intcs_evt2irq(0x700),
272 static struct resource veu0_resources
[] = {
277 .flags
= IORESOURCE_MEM
,
281 static struct platform_device veu0_device
= {
282 .name
= "uio_pdrv_genirq",
285 .platform_data
= &veu0_platform_data
,
287 .resource
= veu0_resources
,
288 .num_resources
= ARRAY_SIZE(veu0_resources
),
292 static struct uio_info veu1_platform_data
= {
295 .irq
= intcs_evt2irq(0x720),
298 static struct resource veu1_resources
[] = {
303 .flags
= IORESOURCE_MEM
,
307 static struct platform_device veu1_device
= {
308 .name
= "uio_pdrv_genirq",
311 .platform_data
= &veu1_platform_data
,
313 .resource
= veu1_resources
,
314 .num_resources
= ARRAY_SIZE(veu1_resources
),
318 static struct uio_info veu2_platform_data
= {
321 .irq
= intcs_evt2irq(0x740),
324 static struct resource veu2_resources
[] = {
329 .flags
= IORESOURCE_MEM
,
333 static struct platform_device veu2_device
= {
334 .name
= "uio_pdrv_genirq",
337 .platform_data
= &veu2_platform_data
,
339 .resource
= veu2_resources
,
340 .num_resources
= ARRAY_SIZE(veu2_resources
),
344 static struct uio_info veu3_platform_data
= {
347 .irq
= intcs_evt2irq(0x760),
350 static struct resource veu3_resources
[] = {
355 .flags
= IORESOURCE_MEM
,
359 static struct platform_device veu3_device
= {
360 .name
= "uio_pdrv_genirq",
363 .platform_data
= &veu3_platform_data
,
365 .resource
= veu3_resources
,
366 .num_resources
= ARRAY_SIZE(veu3_resources
),
370 static struct uio_info jpu_platform_data
= {
373 .irq
= intcs_evt2irq(0x560),
376 static struct resource jpu_resources
[] = {
381 .flags
= IORESOURCE_MEM
,
385 static struct platform_device jpu_device
= {
386 .name
= "uio_pdrv_genirq",
389 .platform_data
= &jpu_platform_data
,
391 .resource
= jpu_resources
,
392 .num_resources
= ARRAY_SIZE(jpu_resources
),
396 static struct uio_info spu0_platform_data
= {
399 .irq
= evt2irq(0x1800),
402 static struct resource spu0_resources
[] = {
407 .flags
= IORESOURCE_MEM
,
411 static struct platform_device spu0_device
= {
412 .name
= "uio_pdrv_genirq",
415 .platform_data
= &spu0_platform_data
,
417 .resource
= spu0_resources
,
418 .num_resources
= ARRAY_SIZE(spu0_resources
),
422 static struct uio_info spu1_platform_data
= {
425 .irq
= evt2irq(0x1820),
428 static struct resource spu1_resources
[] = {
433 .flags
= IORESOURCE_MEM
,
437 static struct platform_device spu1_device
= {
438 .name
= "uio_pdrv_genirq",
441 .platform_data
= &spu1_platform_data
,
443 .resource
= spu1_resources
,
444 .num_resources
= ARRAY_SIZE(spu1_resources
),
447 static struct platform_device
*sh7377_early_devices
[] __initdata
= {
459 static struct platform_device
*sh7377_devices
[] __initdata
= {
470 void __init
sh7377_add_standard_devices(void)
472 platform_add_devices(sh7377_early_devices
,
473 ARRAY_SIZE(sh7377_early_devices
));
475 platform_add_devices(sh7377_devices
,
476 ARRAY_SIZE(sh7377_devices
));
479 static void __init
sh7377_earlytimer_init(void)
482 shmobile_earlytimer_init();
485 #define SMSTPCR3 0xe615013c
486 #define SMSTPCR3_CMT1 (1 << 29)
488 void __init
sh7377_add_early_devices(void)
490 /* enable clock to CMT1 */
491 __raw_writel(__raw_readl(SMSTPCR3
) & ~SMSTPCR3_CMT1
, SMSTPCR3
);
493 early_platform_add_devices(sh7377_early_devices
,
494 ARRAY_SIZE(sh7377_early_devices
));
496 /* setup early console here as well */
497 shmobile_setup_console();
499 /* override timer setup with soc-specific code */
500 shmobile_timer
.init
= sh7377_earlytimer_init
;