2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <mach/dma-register.h>
34 #include <mach/hardware.h>
35 #include <mach/irqs.h>
36 #include <mach/sh73a0.h>
37 #include <mach/common.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/map.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/time.h>
43 static struct map_desc sh73a0_io_desc
[] __initdata
= {
44 /* create a 1:1 entity map for 0xe6xxxxxx
45 * used by CPGA, INTC and PFC.
48 .virtual = 0xe6000000,
49 .pfn
= __phys_to_pfn(0xe6000000),
51 .type
= MT_DEVICE_NONSHARED
55 void __init
sh73a0_map_io(void)
57 iotable_init(sh73a0_io_desc
, ARRAY_SIZE(sh73a0_io_desc
));
60 static struct plat_sci_port scif0_platform_data
= {
61 .mapbase
= 0xe6c40000,
62 .flags
= UPF_BOOT_AUTOCONF
,
63 .scscr
= SCSCR_RE
| SCSCR_TE
,
64 .scbrr_algo_id
= SCBRR_ALGO_4
,
66 .irqs
= { gic_spi(72), gic_spi(72),
67 gic_spi(72), gic_spi(72) },
70 static struct platform_device scif0_device
= {
74 .platform_data
= &scif0_platform_data
,
78 static struct plat_sci_port scif1_platform_data
= {
79 .mapbase
= 0xe6c50000,
80 .flags
= UPF_BOOT_AUTOCONF
,
81 .scscr
= SCSCR_RE
| SCSCR_TE
,
82 .scbrr_algo_id
= SCBRR_ALGO_4
,
84 .irqs
= { gic_spi(73), gic_spi(73),
85 gic_spi(73), gic_spi(73) },
88 static struct platform_device scif1_device
= {
92 .platform_data
= &scif1_platform_data
,
96 static struct plat_sci_port scif2_platform_data
= {
97 .mapbase
= 0xe6c60000,
98 .flags
= UPF_BOOT_AUTOCONF
,
99 .scscr
= SCSCR_RE
| SCSCR_TE
,
100 .scbrr_algo_id
= SCBRR_ALGO_4
,
102 .irqs
= { gic_spi(74), gic_spi(74),
103 gic_spi(74), gic_spi(74) },
106 static struct platform_device scif2_device
= {
110 .platform_data
= &scif2_platform_data
,
114 static struct plat_sci_port scif3_platform_data
= {
115 .mapbase
= 0xe6c70000,
116 .flags
= UPF_BOOT_AUTOCONF
,
117 .scscr
= SCSCR_RE
| SCSCR_TE
,
118 .scbrr_algo_id
= SCBRR_ALGO_4
,
120 .irqs
= { gic_spi(75), gic_spi(75),
121 gic_spi(75), gic_spi(75) },
124 static struct platform_device scif3_device
= {
128 .platform_data
= &scif3_platform_data
,
132 static struct plat_sci_port scif4_platform_data
= {
133 .mapbase
= 0xe6c80000,
134 .flags
= UPF_BOOT_AUTOCONF
,
135 .scscr
= SCSCR_RE
| SCSCR_TE
,
136 .scbrr_algo_id
= SCBRR_ALGO_4
,
138 .irqs
= { gic_spi(78), gic_spi(78),
139 gic_spi(78), gic_spi(78) },
142 static struct platform_device scif4_device
= {
146 .platform_data
= &scif4_platform_data
,
150 static struct plat_sci_port scif5_platform_data
= {
151 .mapbase
= 0xe6cb0000,
152 .flags
= UPF_BOOT_AUTOCONF
,
153 .scscr
= SCSCR_RE
| SCSCR_TE
,
154 .scbrr_algo_id
= SCBRR_ALGO_4
,
156 .irqs
= { gic_spi(79), gic_spi(79),
157 gic_spi(79), gic_spi(79) },
160 static struct platform_device scif5_device
= {
164 .platform_data
= &scif5_platform_data
,
168 static struct plat_sci_port scif6_platform_data
= {
169 .mapbase
= 0xe6cc0000,
170 .flags
= UPF_BOOT_AUTOCONF
,
171 .scscr
= SCSCR_RE
| SCSCR_TE
,
172 .scbrr_algo_id
= SCBRR_ALGO_4
,
174 .irqs
= { gic_spi(156), gic_spi(156),
175 gic_spi(156), gic_spi(156) },
178 static struct platform_device scif6_device
= {
182 .platform_data
= &scif6_platform_data
,
186 static struct plat_sci_port scif7_platform_data
= {
187 .mapbase
= 0xe6cd0000,
188 .flags
= UPF_BOOT_AUTOCONF
,
189 .scscr
= SCSCR_RE
| SCSCR_TE
,
190 .scbrr_algo_id
= SCBRR_ALGO_4
,
192 .irqs
= { gic_spi(143), gic_spi(143),
193 gic_spi(143), gic_spi(143) },
196 static struct platform_device scif7_device
= {
200 .platform_data
= &scif7_platform_data
,
204 static struct plat_sci_port scif8_platform_data
= {
205 .mapbase
= 0xe6c30000,
206 .flags
= UPF_BOOT_AUTOCONF
,
207 .scscr
= SCSCR_RE
| SCSCR_TE
,
208 .scbrr_algo_id
= SCBRR_ALGO_4
,
210 .irqs
= { gic_spi(80), gic_spi(80),
211 gic_spi(80), gic_spi(80) },
214 static struct platform_device scif8_device
= {
218 .platform_data
= &scif8_platform_data
,
222 static struct sh_timer_config cmt10_platform_data
= {
224 .channel_offset
= 0x10,
226 .clockevent_rating
= 125,
227 .clocksource_rating
= 125,
230 static struct resource cmt10_resources
[] = {
235 .flags
= IORESOURCE_MEM
,
238 .start
= gic_spi(65),
239 .flags
= IORESOURCE_IRQ
,
243 static struct platform_device cmt10_device
= {
247 .platform_data
= &cmt10_platform_data
,
249 .resource
= cmt10_resources
,
250 .num_resources
= ARRAY_SIZE(cmt10_resources
),
254 static struct sh_timer_config tmu00_platform_data
= {
256 .channel_offset
= 0x4,
258 .clockevent_rating
= 200,
261 static struct resource tmu00_resources
[] = {
266 .flags
= IORESOURCE_MEM
,
269 .start
= intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
270 .flags
= IORESOURCE_IRQ
,
274 static struct platform_device tmu00_device
= {
278 .platform_data
= &tmu00_platform_data
,
280 .resource
= tmu00_resources
,
281 .num_resources
= ARRAY_SIZE(tmu00_resources
),
284 static struct sh_timer_config tmu01_platform_data
= {
286 .channel_offset
= 0x10,
288 .clocksource_rating
= 200,
291 static struct resource tmu01_resources
[] = {
296 .flags
= IORESOURCE_MEM
,
299 .start
= intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
300 .flags
= IORESOURCE_IRQ
,
304 static struct platform_device tmu01_device
= {
308 .platform_data
= &tmu01_platform_data
,
310 .resource
= tmu01_resources
,
311 .num_resources
= ARRAY_SIZE(tmu01_resources
),
314 static struct resource i2c0_resources
[] = {
318 .end
= 0xe6820425 - 1,
319 .flags
= IORESOURCE_MEM
,
322 .start
= gic_spi(167),
324 .flags
= IORESOURCE_IRQ
,
328 static struct resource i2c1_resources
[] = {
332 .end
= 0xe6822425 - 1,
333 .flags
= IORESOURCE_MEM
,
336 .start
= gic_spi(51),
338 .flags
= IORESOURCE_IRQ
,
342 static struct resource i2c2_resources
[] = {
346 .end
= 0xe6824425 - 1,
347 .flags
= IORESOURCE_MEM
,
350 .start
= gic_spi(171),
352 .flags
= IORESOURCE_IRQ
,
356 static struct resource i2c3_resources
[] = {
360 .end
= 0xe6826425 - 1,
361 .flags
= IORESOURCE_MEM
,
364 .start
= gic_spi(183),
366 .flags
= IORESOURCE_IRQ
,
370 static struct resource i2c4_resources
[] = {
374 .end
= 0xe6828425 - 1,
375 .flags
= IORESOURCE_MEM
,
378 .start
= gic_spi(187),
380 .flags
= IORESOURCE_IRQ
,
384 static struct platform_device i2c0_device
= {
385 .name
= "i2c-sh_mobile",
387 .resource
= i2c0_resources
,
388 .num_resources
= ARRAY_SIZE(i2c0_resources
),
391 static struct platform_device i2c1_device
= {
392 .name
= "i2c-sh_mobile",
394 .resource
= i2c1_resources
,
395 .num_resources
= ARRAY_SIZE(i2c1_resources
),
398 static struct platform_device i2c2_device
= {
399 .name
= "i2c-sh_mobile",
401 .resource
= i2c2_resources
,
402 .num_resources
= ARRAY_SIZE(i2c2_resources
),
405 static struct platform_device i2c3_device
= {
406 .name
= "i2c-sh_mobile",
408 .resource
= i2c3_resources
,
409 .num_resources
= ARRAY_SIZE(i2c3_resources
),
412 static struct platform_device i2c4_device
= {
413 .name
= "i2c-sh_mobile",
415 .resource
= i2c4_resources
,
416 .num_resources
= ARRAY_SIZE(i2c4_resources
),
419 static const struct sh_dmae_slave_config sh73a0_dmae_slaves
[] = {
421 .slave_id
= SHDMA_SLAVE_SCIF0_TX
,
423 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
426 .slave_id
= SHDMA_SLAVE_SCIF0_RX
,
428 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
431 .slave_id
= SHDMA_SLAVE_SCIF1_TX
,
433 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
436 .slave_id
= SHDMA_SLAVE_SCIF1_RX
,
438 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
441 .slave_id
= SHDMA_SLAVE_SCIF2_TX
,
443 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
446 .slave_id
= SHDMA_SLAVE_SCIF2_RX
,
448 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
451 .slave_id
= SHDMA_SLAVE_SCIF3_TX
,
453 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
456 .slave_id
= SHDMA_SLAVE_SCIF3_RX
,
458 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
461 .slave_id
= SHDMA_SLAVE_SCIF4_TX
,
463 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
466 .slave_id
= SHDMA_SLAVE_SCIF4_RX
,
468 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
471 .slave_id
= SHDMA_SLAVE_SCIF5_TX
,
473 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
476 .slave_id
= SHDMA_SLAVE_SCIF5_RX
,
478 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
481 .slave_id
= SHDMA_SLAVE_SCIF6_TX
,
483 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
486 .slave_id
= SHDMA_SLAVE_SCIF6_RX
,
488 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
491 .slave_id
= SHDMA_SLAVE_SCIF7_TX
,
493 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
496 .slave_id
= SHDMA_SLAVE_SCIF7_RX
,
498 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
501 .slave_id
= SHDMA_SLAVE_SCIF8_TX
,
503 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
506 .slave_id
= SHDMA_SLAVE_SCIF8_RX
,
508 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
511 .slave_id
= SHDMA_SLAVE_SDHI0_TX
,
513 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
516 .slave_id
= SHDMA_SLAVE_SDHI0_RX
,
518 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
521 .slave_id
= SHDMA_SLAVE_SDHI1_TX
,
523 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
526 .slave_id
= SHDMA_SLAVE_SDHI1_RX
,
528 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
531 .slave_id
= SHDMA_SLAVE_SDHI2_TX
,
533 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
536 .slave_id
= SHDMA_SLAVE_SDHI2_RX
,
538 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
541 .slave_id
= SHDMA_SLAVE_MMCIF_TX
,
543 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
546 .slave_id
= SHDMA_SLAVE_MMCIF_RX
,
548 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
553 #define DMAE_CHANNEL(_offset) \
555 .offset = _offset - 0x20, \
556 .dmars = _offset - 0x20 + 0x40, \
559 static const struct sh_dmae_channel sh73a0_dmae_channels
[] = {
560 DMAE_CHANNEL(0x8000),
561 DMAE_CHANNEL(0x8080),
562 DMAE_CHANNEL(0x8100),
563 DMAE_CHANNEL(0x8180),
564 DMAE_CHANNEL(0x8200),
565 DMAE_CHANNEL(0x8280),
566 DMAE_CHANNEL(0x8300),
567 DMAE_CHANNEL(0x8380),
568 DMAE_CHANNEL(0x8400),
569 DMAE_CHANNEL(0x8480),
570 DMAE_CHANNEL(0x8500),
571 DMAE_CHANNEL(0x8580),
572 DMAE_CHANNEL(0x8600),
573 DMAE_CHANNEL(0x8680),
574 DMAE_CHANNEL(0x8700),
575 DMAE_CHANNEL(0x8780),
576 DMAE_CHANNEL(0x8800),
577 DMAE_CHANNEL(0x8880),
578 DMAE_CHANNEL(0x8900),
579 DMAE_CHANNEL(0x8980),
582 static struct sh_dmae_pdata sh73a0_dmae_platform_data
= {
583 .slave
= sh73a0_dmae_slaves
,
584 .slave_num
= ARRAY_SIZE(sh73a0_dmae_slaves
),
585 .channel
= sh73a0_dmae_channels
,
586 .channel_num
= ARRAY_SIZE(sh73a0_dmae_channels
),
587 .ts_low_shift
= TS_LOW_SHIFT
,
588 .ts_low_mask
= TS_LOW_BIT
<< TS_LOW_SHIFT
,
589 .ts_high_shift
= TS_HI_SHIFT
,
590 .ts_high_mask
= TS_HI_BIT
<< TS_HI_SHIFT
,
591 .ts_shift
= dma_ts_shift
,
592 .ts_shift_num
= ARRAY_SIZE(dma_ts_shift
),
593 .dmaor_init
= DMAOR_DME
,
596 static struct resource sh73a0_dmae_resources
[] = {
598 /* Registers including DMAOR and channels including DMARSx */
600 .end
= 0xfe008a00 - 1,
601 .flags
= IORESOURCE_MEM
,
605 .start
= gic_spi(129),
607 .flags
= IORESOURCE_IRQ
,
610 /* IRQ for channels 0-19 */
611 .start
= gic_spi(109),
613 .flags
= IORESOURCE_IRQ
,
617 static struct platform_device dma0_device
= {
618 .name
= "sh-dma-engine",
620 .resource
= sh73a0_dmae_resources
,
621 .num_resources
= ARRAY_SIZE(sh73a0_dmae_resources
),
623 .platform_data
= &sh73a0_dmae_platform_data
,
628 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves
[] = {
630 .slave_id
= SHDMA_SLAVE_FSI2A_RX
,
632 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
633 .mid_rid
= 0xd6, /* CHECK ME */
635 .slave_id
= SHDMA_SLAVE_FSI2A_TX
,
637 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
638 .mid_rid
= 0xd5, /* CHECK ME */
640 .slave_id
= SHDMA_SLAVE_FSI2C_RX
,
642 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
643 .mid_rid
= 0xda, /* CHECK ME */
645 .slave_id
= SHDMA_SLAVE_FSI2C_TX
,
647 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
648 .mid_rid
= 0xd9, /* CHECK ME */
650 .slave_id
= SHDMA_SLAVE_FSI2B_RX
,
652 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
653 .mid_rid
= 0x8e, /* CHECK ME */
655 .slave_id
= SHDMA_SLAVE_FSI2B_TX
,
657 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
658 .mid_rid
= 0x8d, /* CHECK ME */
660 .slave_id
= SHDMA_SLAVE_FSI2D_RX
,
662 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
663 .mid_rid
= 0x9a, /* CHECK ME */
667 #define MPDMA_CHANNEL(a, b, c) \
672 .chclr_offset = (0x220 - 0x20) + a \
675 static const struct sh_dmae_channel sh73a0_mpdma_channels
[] = {
676 MPDMA_CHANNEL(0x00, 0, 0),
677 MPDMA_CHANNEL(0x10, 0, 8),
678 MPDMA_CHANNEL(0x20, 4, 0),
679 MPDMA_CHANNEL(0x30, 4, 8),
680 MPDMA_CHANNEL(0x50, 8, 0),
681 MPDMA_CHANNEL(0x70, 8, 8),
684 static struct sh_dmae_pdata sh73a0_mpdma_platform_data
= {
685 .slave
= sh73a0_mpdma_slaves
,
686 .slave_num
= ARRAY_SIZE(sh73a0_mpdma_slaves
),
687 .channel
= sh73a0_mpdma_channels
,
688 .channel_num
= ARRAY_SIZE(sh73a0_mpdma_channels
),
689 .ts_low_shift
= TS_LOW_SHIFT
,
690 .ts_low_mask
= TS_LOW_BIT
<< TS_LOW_SHIFT
,
691 .ts_high_shift
= TS_HI_SHIFT
,
692 .ts_high_mask
= TS_HI_BIT
<< TS_HI_SHIFT
,
693 .ts_shift
= dma_ts_shift
,
694 .ts_shift_num
= ARRAY_SIZE(dma_ts_shift
),
695 .dmaor_init
= DMAOR_DME
,
699 /* Resource order important! */
700 static struct resource sh73a0_mpdma_resources
[] = {
702 /* Channel registers and DMAOR */
705 .flags
= IORESOURCE_MEM
,
711 .flags
= IORESOURCE_MEM
,
715 .start
= gic_spi(181),
717 .flags
= IORESOURCE_IRQ
,
720 /* IRQ for channels 0-5 */
721 .start
= gic_spi(175),
723 .flags
= IORESOURCE_IRQ
,
727 static struct platform_device mpdma0_device
= {
728 .name
= "sh-dma-engine",
730 .resource
= sh73a0_mpdma_resources
,
731 .num_resources
= ARRAY_SIZE(sh73a0_mpdma_resources
),
733 .platform_data
= &sh73a0_mpdma_platform_data
,
737 static struct platform_device
*sh73a0_early_devices
[] __initdata
= {
752 static struct platform_device
*sh73a0_late_devices
[] __initdata
= {
762 #define SRCR2 IOMEM(0xe61580b0)
764 void __init
sh73a0_add_standard_devices(void)
766 /* Clear software reset bit on SY-DMAC module */
767 __raw_writel(__raw_readl(SRCR2
) & ~(1 << 18), SRCR2
);
769 platform_add_devices(sh73a0_early_devices
,
770 ARRAY_SIZE(sh73a0_early_devices
));
771 platform_add_devices(sh73a0_late_devices
,
772 ARRAY_SIZE(sh73a0_late_devices
));
775 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
776 void __init __weak
sh73a0_register_twd(void) { }
778 static void __init
sh73a0_earlytimer_init(void)
781 shmobile_earlytimer_init();
782 sh73a0_register_twd();
785 void __init
sh73a0_add_early_devices(void)
787 early_platform_add_devices(sh73a0_early_devices
,
788 ARRAY_SIZE(sh73a0_early_devices
));
790 /* setup early console here as well */
791 shmobile_setup_console();
793 /* override timer setup with soc-specific code */
794 shmobile_timer
.init
= sh73a0_earlytimer_init
;