arch/arm/mach-socfpga/socfpga.c

   1 /*
   2  *  Copyright (C) 2012-2015 Altera Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <linux/irqchip.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/reboot.h>
  22
  23 #include <asm/hardware/cache-l2x0.h>
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/cacheflush.h>
  27
  28 #include "core.h"
  29
  30 void __iomem *sys_manager_base_addr;
  31 void __iomem *rst_manager_base_addr;
  32 void __iomem *sdr_ctl_base_addr;
  33 unsigned long socfpga_cpu1start_addr;
  34
  35 extern void __init socfpga_reset_init(void);
  36
  37 static void __init socfpga_sysmgr_init(void)
  38 {
  39         struct device_node *np;
  40
  41         np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
  42
  43         if (of_property_read_u32(np, "cpu1-start-addr",
  44                         (u32 *) &socfpga_cpu1start_addr))
  45                 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
  46
  47         /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
  48         smp_wmb();
  49         sync_cache_w(&socfpga_cpu1start_addr);
  50
  51         sys_manager_base_addr = of_iomap(np, 0);
  52
  53         np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
  54         rst_manager_base_addr = of_iomap(np, 0);
  55
  56         np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
  57         sdr_ctl_base_addr = of_iomap(np, 0);
  58 }
  59
  60 static void __init socfpga_init_irq(void)
  61 {
  62         irqchip_init();
  63         socfpga_sysmgr_init();
  64         if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
  65                 socfpga_init_l2_ecc();
  66
  67         if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
  68                 socfpga_init_ocram_ecc();
  69         socfpga_reset_init();
  70 }
  71
  72 static void __init socfpga_arria10_init_irq(void)
  73 {
  74         irqchip_init();
  75         socfpga_sysmgr_init();
  76         if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
  77                 socfpga_init_arria10_l2_ecc();
  78         if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
  79                 socfpga_init_arria10_ocram_ecc();
  80         socfpga_reset_init();
  81 }
  82
  83 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
  84 {
  85         u32 temp;
  86
  87         temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  88
  89         if (mode == REBOOT_HARD)
  90                 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
  91         else
  92                 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
  93         writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  94 }
  95
  96 static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
  97 {
  98         u32 temp;
  99
 100         temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
 101
 102         if (mode == REBOOT_HARD)
 103                 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
 104         else
 105                 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
 106         writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
 107 }
 108
 109 static const char *altera_dt_match[] = {
 110         "altr,socfpga",
 111         NULL
 112 };
 113
 114 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
 115         .l2c_aux_val    = 0,
 116         .l2c_aux_mask   = ~0,
 117         .init_irq       = socfpga_init_irq,
 118         .restart        = socfpga_cyclone5_restart,
 119         .dt_compat      = altera_dt_match,
 120 MACHINE_END
 121
 122 static const char *altera_a10_dt_match[] = {
 123         "altr,socfpga-arria10",
 124         NULL
 125 };
 126
 127 DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
 128         .l2c_aux_val    = 0,
 129         .l2c_aux_mask   = ~0,
 130         .init_irq       = socfpga_arria10_init_irq,
 131         .restart        = socfpga_arria10_restart,
 132         .dt_compat      = altera_a10_dt_match,
 133 MACHINE_END