]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/arm/mach-spear/spear13xx.c
Merge tag 'nfs-for-3.10-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-spear / spear13xx.c
1 /*
2 * arch/arm/mach-spear13xx/spear13xx.c
3 *
4 * SPEAr13XX machines common source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #define pr_fmt(fmt) "SPEAr13xx: " fmt
15
16 #include <linux/amba/pl022.h>
17 #include <linux/clk.h>
18 #include <linux/clocksource.h>
19 #include <linux/err.h>
20 #include <linux/of.h>
21 #include <asm/hardware/cache-l2x0.h>
22 #include <asm/mach/map.h>
23 #include <mach/spear.h>
24 #include "generic.h"
25
26 void __init spear13xx_l2x0_init(void)
27 {
28 /*
29 * 512KB (64KB/way), 8-way associativity, parity supported
30 *
31 * FIXME: 9th bit, of Auxillary Controller register must be set
32 * for some spear13xx devices for stable L2 operation.
33 *
34 * Enable Early BRESP, L2 prefetch for Instruction and Data,
35 * write alloc and 'Full line of zero' options
36 *
37 */
38
39 writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
40
41 /*
42 * Program following latencies in order to make
43 * SPEAr1340 work at 600 MHz
44 */
45 writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
46 writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
47 l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
48 }
49
50 /*
51 * Following will create 16MB static virtual/physical mappings
52 * PHYSICAL VIRTUAL
53 * 0xB3000000 0xFE000000
54 * 0xE0000000 0xFD000000
55 * 0xEC000000 0xFC000000
56 * 0xED000000 0xFB000000
57 */
58 struct map_desc spear13xx_io_desc[] __initdata = {
59 {
60 .virtual = (unsigned long)VA_PERIP_GRP2_BASE,
61 .pfn = __phys_to_pfn(PERIP_GRP2_BASE),
62 .length = SZ_16M,
63 .type = MT_DEVICE
64 }, {
65 .virtual = (unsigned long)VA_PERIP_GRP1_BASE,
66 .pfn = __phys_to_pfn(PERIP_GRP1_BASE),
67 .length = SZ_16M,
68 .type = MT_DEVICE
69 }, {
70 .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE,
71 .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
72 .length = SZ_16M,
73 .type = MT_DEVICE
74 }, {
75 .virtual = (unsigned long)VA_L2CC_BASE,
76 .pfn = __phys_to_pfn(L2CC_BASE),
77 .length = SZ_4K,
78 .type = MT_DEVICE
79 },
80 };
81
82 /* This will create static memory mapping for selected devices */
83 void __init spear13xx_map_io(void)
84 {
85 iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
86 }
87
88 static void __init spear13xx_clk_init(void)
89 {
90 if (of_machine_is_compatible("st,spear1310"))
91 spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
92 else if (of_machine_is_compatible("st,spear1340"))
93 spear1340_clk_init(VA_MISC_BASE);
94 else
95 pr_err("%s: Unknown machine\n", __func__);
96 }
97
98 void __init spear13xx_timer_init(void)
99 {
100 char pclk_name[] = "osc_24m_clk";
101 struct clk *gpt_clk, *pclk;
102
103 spear13xx_clk_init();
104
105 /* get the system timer clock */
106 gpt_clk = clk_get_sys("gpt0", NULL);
107 if (IS_ERR(gpt_clk)) {
108 pr_err("%s:couldn't get clk for gpt\n", __func__);
109 BUG();
110 }
111
112 /* get the suitable parent clock for timer*/
113 pclk = clk_get(NULL, pclk_name);
114 if (IS_ERR(pclk)) {
115 pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
116 pclk_name);
117 BUG();
118 }
119
120 clk_set_parent(gpt_clk, pclk);
121 clk_put(gpt_clk);
122 clk_put(pclk);
123
124 spear_setup_of_timer();
125 clocksource_of_init();
126 }