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ARM: 6483/1: arm & sh: factorised duplicated clkdev.c
[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-tcc8k / clock.c
1 /*
2 * Lowlevel clock handling for Telechips TCC8xxx SoCs
3 *
4 * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
5 *
6 * Licensed under the terms of the GPL v2
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/spinlock.h>
15 #include <linux/clkdev.h>
16
17 #include <mach/clock.h>
18 #include <mach/irqs.h>
19 #include <mach/tcc8k-regs.h>
20
21 #include "common.h"
22
23 #define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS)
24 #define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS)
25
26 #define ACLKREF (CKC_BASE + ACLKREF_OFFS)
27 #define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS)
28 #define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS)
29 #define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS)
30 #define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS)
31 #define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS)
32 #define ACLKI2C (CKC_BASE + ACLKI2C_OFFS)
33 #define ACLKADC (CKC_BASE + ACLKADC_OFFS)
34 #define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
35 #define ACLKLCD (CKC_BASE + ACLKLCD_OFFS)
36 #define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS)
37 #define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS)
38 #define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS)
39 #define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS)
40 #define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS)
41 #define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS)
42 #define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS)
43 #define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS)
44 #define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS)
45 #define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
46 #define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
47 #define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
48 #define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
49 #define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
50 #define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
51 #define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
52
53 /* Crystal frequencies */
54 static unsigned long xi_rate, xti_rate;
55
56 static void __iomem *pll_cfg_addr(int pll)
57 {
58 switch (pll) {
59 case 0: return (CKC_BASE + PLL0CFG_OFFS);
60 case 1: return (CKC_BASE + PLL1CFG_OFFS);
61 case 2: return (CKC_BASE + PLL2CFG_OFFS);
62 default:
63 BUG();
64 }
65 }
66
67 static int pll_enable(int pll, int enable)
68 {
69 u32 reg;
70 void __iomem *addr = pll_cfg_addr(pll);
71
72 reg = __raw_readl(addr);
73 if (enable)
74 reg &= ~PLLxCFG_PD;
75 else
76 reg |= PLLxCFG_PD;
77
78 __raw_writel(reg, addr);
79 return 0;
80 }
81
82 static int xi_enable(int enable)
83 {
84 u32 reg;
85
86 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
87 if (enable)
88 reg |= CLKCTRL_XE;
89 else
90 reg &= ~CLKCTRL_XE;
91
92 __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
93 return 0;
94 }
95
96 static int root_clk_enable(enum root_clks src)
97 {
98 switch (src) {
99 case CLK_SRC_PLL0: return pll_enable(0, 1);
100 case CLK_SRC_PLL1: return pll_enable(1, 1);
101 case CLK_SRC_PLL2: return pll_enable(2, 1);
102 case CLK_SRC_XI: return xi_enable(1);
103 default:
104 BUG();
105 }
106 return 0;
107 }
108
109 static int root_clk_disable(enum root_clks root_src)
110 {
111 switch (root_src) {
112 case CLK_SRC_PLL0: return pll_enable(0, 0);
113 case CLK_SRC_PLL1: return pll_enable(1, 0);
114 case CLK_SRC_PLL2: return pll_enable(2, 0);
115 case CLK_SRC_XI: return xi_enable(0);
116 default:
117 BUG();
118 }
119 return 0;
120 }
121
122 static int enable_clk(struct clk *clk)
123 {
124 u32 reg;
125
126 if (clk->root_id != CLK_SRC_NOROOT)
127 return root_clk_enable(clk->root_id);
128
129 if (clk->aclkreg) {
130 reg = __raw_readl(clk->aclkreg);
131 reg |= ACLK_EN;
132 __raw_writel(reg, clk->aclkreg);
133 }
134 if (clk->bclkctr) {
135 reg = __raw_readl(clk->bclkctr);
136 reg |= 1 << clk->bclk_shift;
137 __raw_writel(reg, clk->bclkctr);
138 }
139 return 0;
140 }
141
142 static void disable_clk(struct clk *clk)
143 {
144 u32 reg;
145
146 if (clk->root_id != CLK_SRC_NOROOT) {
147 root_clk_disable(clk->root_id);
148 return;
149 }
150
151 if (clk->bclkctr) {
152 reg = __raw_readl(clk->bclkctr);
153 reg &= ~(1 << clk->bclk_shift);
154 __raw_writel(reg, clk->bclkctr);
155 }
156 if (clk->aclkreg) {
157 reg = __raw_readl(clk->aclkreg);
158 reg &= ~ACLK_EN;
159 __raw_writel(reg, clk->aclkreg);
160 }
161 }
162
163 static unsigned long get_rate_pll(int pll)
164 {
165 u32 reg;
166 unsigned long s, m, p;
167 void __iomem *addr = pll_cfg_addr(pll);
168
169 reg = __raw_readl(addr);
170 s = (reg >> 16) & 0x07;
171 m = (reg >> 8) & 0xff;
172 p = reg & 0x3f;
173
174 return (m * xi_rate) / (p * (1 << s));
175 }
176
177 static unsigned long get_rate_pll_div(int pll)
178 {
179 u32 reg;
180 unsigned long div = 0;
181 void __iomem *addr;
182
183 switch (pll) {
184 case 0:
185 addr = CKC_BASE + CLKDIVC0_OFFS;
186 reg = __raw_readl(addr);
187 if (reg & CLKDIVC0_P0E)
188 div = (reg >> 24) & 0x3f;
189 break;
190 case 1:
191 addr = CKC_BASE + CLKDIVC0_OFFS;
192 reg = __raw_readl(addr);
193 if (reg & CLKDIVC0_P1E)
194 div = (reg >> 16) & 0x3f;
195 break;
196 case 2:
197 addr = CKC_BASE + CLKDIVC1_OFFS;
198 reg = __raw_readl(addr);
199 if (reg & CLKDIVC1_P2E)
200 div = __raw_readl(addr) & 0x3f;
201 break;
202 }
203 return get_rate_pll(pll) / (div + 1);
204 }
205
206 static unsigned long get_rate_xi_div(void)
207 {
208 unsigned long div = 0;
209 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
210
211 if (reg & CLKDIVC0_XE)
212 div = (reg >> 8) & 0x3f;
213
214 return xi_rate / (div + 1);
215 }
216
217 static unsigned long get_rate_xti_div(void)
218 {
219 unsigned long div = 0;
220 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
221
222 if (reg & CLKDIVC0_XTE)
223 div = reg & 0x3f;
224
225 return xti_rate / (div + 1);
226 }
227
228 static unsigned long root_clk_get_rate(enum root_clks src)
229 {
230 switch (src) {
231 case CLK_SRC_PLL0: return get_rate_pll(0);
232 case CLK_SRC_PLL1: return get_rate_pll(1);
233 case CLK_SRC_PLL2: return get_rate_pll(2);
234 case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
235 case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
236 case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
237 case CLK_SRC_XI: return xi_rate;
238 case CLK_SRC_XTI: return xti_rate;
239 case CLK_SRC_XIDIV: return get_rate_xi_div();
240 case CLK_SRC_XTIDIV: return get_rate_xti_div();
241 default: return 0;
242 }
243 }
244
245 static unsigned long aclk_get_rate(struct clk *clk)
246 {
247 u32 reg;
248 unsigned long div;
249 unsigned int src;
250
251 reg = __raw_readl(clk->aclkreg);
252 div = reg & 0x0fff;
253 src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
254 return root_clk_get_rate(src) / (div + 1);
255 }
256
257 static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
258 {
259 unsigned long div, src, freq, r1, r2;
260
261 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
262 src &= CLK_SRC_MASK;
263 freq = root_clk_get_rate(src);
264 div = freq / rate + 1;
265 r1 = freq / div;
266 r2 = freq / (div + 1);
267 if (r2 >= rate)
268 return div + 1;
269 if ((rate - r2) < (r1 - rate))
270 return div + 1;
271
272 return div;
273 }
274
275 static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
276 {
277 unsigned int src;
278
279 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
280 src &= CLK_SRC_MASK;
281
282 return root_clk_get_rate(src) / aclk_best_div(clk, rate);
283 }
284
285 static int aclk_set_rate(struct clk *clk, unsigned long rate)
286 {
287 u32 reg;
288
289 reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
290 reg |= aclk_best_div(clk, rate);
291 return 0;
292 }
293
294 static unsigned long get_rate_sys(struct clk *clk)
295 {
296 unsigned int src;
297
298 src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
299 return root_clk_get_rate(src);
300 }
301
302 static unsigned long get_rate_bus(struct clk *clk)
303 {
304 unsigned int div;
305
306 div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
307 return get_rate_sys(clk) / (div + 1);
308 }
309
310 static unsigned long get_rate_cpu(struct clk *clk)
311 {
312 unsigned int reg, div, fsys, fbus;
313
314 fbus = get_rate_bus(clk);
315 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
316 if (reg & (1 << 29))
317 return fbus;
318 fsys = get_rate_sys(clk);
319 div = (reg >> 16) & 0x0f;
320 return fbus + ((fsys - fbus) * (div + 1)) / 16;
321 }
322
323 static unsigned long get_rate_root(struct clk *clk)
324 {
325 return root_clk_get_rate(clk->root_id);
326 }
327
328 static int aclk_set_parent(struct clk *clock, struct clk *parent)
329 {
330 u32 reg;
331
332 if (clock->parent == parent)
333 return 0;
334
335 clock->parent = parent;
336
337 if (!parent)
338 return 0;
339
340 if (parent->root_id == CLK_SRC_NOROOT)
341 return 0;
342 reg = __raw_readl(clock->aclkreg);
343 reg &= ~ACLK_SEL_MASK;
344 reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
345 __raw_writel(reg, clock->aclkreg);
346
347 return 0;
348 }
349
350 #define DEFINE_ROOT_CLOCK(name, ri, p) \
351 static struct clk name = { \
352 .root_id = ri, \
353 .get_rate = get_rate_root, \
354 .enable = enable_clk, \
355 .disable = disable_clk, \
356 .parent = p, \
357 };
358
359 #define DEFINE_SPECIAL_CLOCK(name, gr, p) \
360 static struct clk name = { \
361 .root_id = CLK_SRC_NOROOT, \
362 .get_rate = gr, \
363 .parent = p, \
364 };
365
366 #define DEFINE_ACLOCK(name, bc, bs, ar) \
367 static struct clk name = { \
368 .root_id = CLK_SRC_NOROOT, \
369 .bclkctr = bc, \
370 .bclk_shift = bs, \
371 .aclkreg = ar, \
372 .get_rate = aclk_get_rate, \
373 .set_rate = aclk_set_rate, \
374 .round_rate = aclk_round_rate, \
375 .enable = enable_clk, \
376 .disable = disable_clk, \
377 .set_parent = aclk_set_parent, \
378 };
379
380 #define DEFINE_BCLOCK(name, bc, bs, gr, p) \
381 static struct clk name = { \
382 .root_id = CLK_SRC_NOROOT, \
383 .bclkctr = bc, \
384 .bclk_shift = bs, \
385 .get_rate = gr, \
386 .enable = enable_clk, \
387 .disable = disable_clk, \
388 .parent = p, \
389 };
390
391 DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
392 DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
393 DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
394 DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
395 DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
396 DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
397 DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
398 DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
399 DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
400 DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
401
402 /* The following 3 clocks are special and are initialized explicitly later */
403 DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
404 DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
405 DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
406
407 DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
408 DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
409 DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
410 DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
411 DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
412 DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
413 DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
414 DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
415 DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
416 DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
417 DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
418 DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
419 DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
420 DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
421 DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
422 DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
423 DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
424 DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
425 DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
426 DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
427 DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
428 DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
429 DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
430 DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
431 DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
432 DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
433
434 DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
435 DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
436 DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
437 DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
438 DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
439 DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
440 DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
441 DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
442 DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
443 DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
444 DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
445 DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
446 DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
447 DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
448 DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
449 DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
450 DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
451 DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
452 DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
453 DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
454 DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
455 DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
456
457 #define _REGISTER_CLOCK(d, n, c) \
458 { \
459 .dev_id = d, \
460 .con_id = n, \
461 .clk = &c, \
462 },
463
464 static struct clk_lookup lookups[] = {
465 _REGISTER_CLOCK(NULL, "bus", bus)
466 _REGISTER_CLOCK(NULL, "cpu", cpu)
467 _REGISTER_CLOCK(NULL, "tct", tct)
468 _REGISTER_CLOCK(NULL, "tcx", tcx)
469 _REGISTER_CLOCK(NULL, "tcz", tcz)
470 _REGISTER_CLOCK(NULL, "ref", ref)
471 _REGISTER_CLOCK(NULL, "dai0", dai0)
472 _REGISTER_CLOCK(NULL, "pic", pic)
473 _REGISTER_CLOCK(NULL, "tc", tc)
474 _REGISTER_CLOCK(NULL, "gpio", gpio)
475 _REGISTER_CLOCK(NULL, "usbd", usbd)
476 _REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
477 _REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
478 _REGISTER_CLOCK("tcc-i2c", NULL, i2c)
479 _REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
480 _REGISTER_CLOCK(NULL, "ecc", ecc)
481 _REGISTER_CLOCK(NULL, "adc", adc)
482 _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
483 _REGISTER_CLOCK(NULL, "gdma0", gdma0)
484 _REGISTER_CLOCK(NULL, "lcd", lcd)
485 _REGISTER_CLOCK(NULL, "rtc", rtc)
486 _REGISTER_CLOCK(NULL, "nfc", nfc)
487 _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
488 _REGISTER_CLOCK(NULL, "g2d", g2d)
489 _REGISTER_CLOCK(NULL, "gdma1", gdma1)
490 _REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
491 _REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
492 _REGISTER_CLOCK(NULL, "mscl", mscl)
493 _REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
494 _REGISTER_CLOCK(NULL, "bdma", bdma)
495 _REGISTER_CLOCK(NULL, "adma0", adma0)
496 _REGISTER_CLOCK(NULL, "spdif", spdif)
497 _REGISTER_CLOCK(NULL, "scfg", scfg)
498 _REGISTER_CLOCK(NULL, "cid", cid)
499 _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
500 _REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
501 _REGISTER_CLOCK(NULL, "dai1", dai1)
502 _REGISTER_CLOCK(NULL, "adma1", adma1)
503 _REGISTER_CLOCK(NULL, "c3dec", c3dec)
504 _REGISTER_CLOCK("tcc-can.0", NULL, can0)
505 _REGISTER_CLOCK("tcc-can.1", NULL, can1)
506 _REGISTER_CLOCK(NULL, "gps", gps)
507 _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
508 _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
509 _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
510 _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
511 _REGISTER_CLOCK(NULL, "gdma2", gdma2)
512 _REGISTER_CLOCK(NULL, "gdma3", gdma3)
513 _REGISTER_CLOCK(NULL, "ddrc", ddrc)
514 _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
515 };
516
517 static struct clk *root_clk_by_index(enum root_clks src)
518 {
519 switch (src) {
520 case CLK_SRC_PLL0: return &pll0;
521 case CLK_SRC_PLL1: return &pll1;
522 case CLK_SRC_PLL2: return &pll2;
523 case CLK_SRC_PLL0DIV: return &pll0div;
524 case CLK_SRC_PLL1DIV: return &pll1div;
525 case CLK_SRC_PLL2DIV: return &pll2div;
526 case CLK_SRC_XI: return &xi;
527 case CLK_SRC_XTI: return &xti;
528 case CLK_SRC_XIDIV: return &xidiv;
529 case CLK_SRC_XTIDIV: return &xtidiv;
530 default: return NULL;
531 }
532 }
533
534 static void find_aclk_parent(struct clk *clk)
535 {
536 unsigned int src;
537 struct clk *clock;
538
539 if (!clk->aclkreg)
540 return;
541
542 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
543 src &= CLK_SRC_MASK;
544
545 clock = root_clk_by_index(src);
546 if (!clock)
547 return;
548
549 clk->parent = clock;
550 clk->set_parent = aclk_set_parent;
551 }
552
553 void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
554 {
555 int i;
556
557 xi_rate = xi_freq;
558 xti_rate = xti_freq;
559
560 /* fixup parents and add the clock */
561 for (i = 0; i < ARRAY_SIZE(lookups); i++) {
562 find_aclk_parent(lookups[i].clk);
563 clkdev_add(&lookups[i]);
564 }
565 tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);
566 }
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