arch/arm/mach-tegra/iomap.h

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@google.com>
   6  *      Erik Gilling <konkers@google.com>
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #ifndef __MACH_TEGRA_IOMAP_H
  20 #define __MACH_TEGRA_IOMAP_H
  21
  22 #include <asm/sizes.h>
  23
  24 #define TEGRA_IRAM_BASE                 0x40000000
  25 #define TEGRA_IRAM_SIZE                 SZ_256K
  26
  27 #define TEGRA_ARM_PERIF_BASE            0x50040000
  28 #define TEGRA_ARM_PERIF_SIZE            SZ_8K
  29
  30 #define TEGRA_ARM_INT_DIST_BASE         0x50041000
  31 #define TEGRA_ARM_INT_DIST_SIZE         SZ_4K
  32
  33 #define TEGRA_PRIMARY_ICTLR_BASE        0x60004000
  34 #define TEGRA_PRIMARY_ICTLR_SIZE        SZ_64
  35
  36 #define TEGRA_SECONDARY_ICTLR_BASE      0x60004100
  37 #define TEGRA_SECONDARY_ICTLR_SIZE      SZ_64
  38
  39 #define TEGRA_TERTIARY_ICTLR_BASE       0x60004200
  40 #define TEGRA_TERTIARY_ICTLR_SIZE       SZ_64
  41
  42 #define TEGRA_QUATERNARY_ICTLR_BASE     0x60004300
  43 #define TEGRA_QUATERNARY_ICTLR_SIZE     SZ_64
  44
  45 #define TEGRA_QUINARY_ICTLR_BASE        0x60004400
  46 #define TEGRA_QUINARY_ICTLR_SIZE        SZ_64
  47
  48 #define TEGRA_TMR1_BASE                 0x60005000
  49 #define TEGRA_TMR1_SIZE                 SZ_8
  50
  51 #define TEGRA_TMR2_BASE                 0x60005008
  52 #define TEGRA_TMR2_SIZE                 SZ_8
  53
  54 #define TEGRA_TMRUS_BASE                0x60005010
  55 #define TEGRA_TMRUS_SIZE                SZ_64
  56
  57 #define TEGRA_TMR3_BASE                 0x60005050
  58 #define TEGRA_TMR3_SIZE                 SZ_8
  59
  60 #define TEGRA_TMR4_BASE                 0x60005058
  61 #define TEGRA_TMR4_SIZE                 SZ_8
  62
  63 #define TEGRA_CLK_RESET_BASE            0x60006000
  64 #define TEGRA_CLK_RESET_SIZE            SZ_4K
  65
  66 #define TEGRA_FLOW_CTRL_BASE            0x60007000
  67 #define TEGRA_FLOW_CTRL_SIZE            20
  68
  69 #define TEGRA_SB_BASE                   0x6000C200
  70 #define TEGRA_SB_SIZE                   256
  71
  72 #define TEGRA_EXCEPTION_VECTORS_BASE    0x6000F000
  73 #define TEGRA_EXCEPTION_VECTORS_SIZE    SZ_4K
  74
  75 #define TEGRA_APB_MISC_BASE             0x70000000
  76 #define TEGRA_APB_MISC_SIZE             SZ_4K
  77
  78 #define TEGRA_UARTA_BASE                0x70006000
  79 #define TEGRA_UARTA_SIZE                SZ_64
  80
  81 #define TEGRA_UARTB_BASE                0x70006040
  82 #define TEGRA_UARTB_SIZE                SZ_64
  83
  84 #define TEGRA_UARTC_BASE                0x70006200
  85 #define TEGRA_UARTC_SIZE                SZ_256
  86
  87 #define TEGRA_UARTD_BASE                0x70006300
  88 #define TEGRA_UARTD_SIZE                SZ_256
  89
  90 #define TEGRA_UARTE_BASE                0x70006400
  91 #define TEGRA_UARTE_SIZE                SZ_256
  92
  93 #define TEGRA_PMC_BASE                  0x7000E400
  94 #define TEGRA_PMC_SIZE                  SZ_256
  95
  96 #define TEGRA_EMC_BASE                  0x7000F400
  97 #define TEGRA_EMC_SIZE                  SZ_1K
  98
  99 #define TEGRA_FUSE_BASE                 0x7000F800
 100 #define TEGRA_FUSE_SIZE                 SZ_1K
 101
 102 #define TEGRA_EMC0_BASE                 0x7001A000
 103 #define TEGRA_EMC0_SIZE                 SZ_2K
 104
 105 #define TEGRA_EMC1_BASE                 0x7001A800
 106 #define TEGRA_EMC1_SIZE                 SZ_2K
 107
 108 #define TEGRA124_EMC_BASE               0x7001B000
 109 #define TEGRA124_EMC_SIZE               SZ_2K
 110
 111 #define TEGRA_CSITE_BASE                0x70040000
 112 #define TEGRA_CSITE_SIZE                SZ_256K
 113
 114 /* On TEGRA, many peripherals are very closely packed in
 115  * two 256MB io windows (that actually only use about 64KB
 116  * at the start of each).
 117  *
 118  * We will just map the first 1MB of each window (to minimize
 119  * pt entries needed) and provide a macro to transform physical
 120  * io addresses to an appropriate void __iomem *.
 121  *
 122  */
 123
 124 #define IO_IRAM_PHYS    0x40000000
 125 #define IO_IRAM_VIRT    IOMEM(0xFE400000)
 126 #define IO_IRAM_SIZE    SZ_256K
 127
 128 #define IO_CPU_PHYS     0x50040000
 129 #define IO_CPU_VIRT     IOMEM(0xFE000000)
 130 #define IO_CPU_SIZE     SZ_16K
 131
 132 #define IO_PPSB_PHYS    0x60000000
 133 #define IO_PPSB_VIRT    IOMEM(0xFE200000)
 134 #define IO_PPSB_SIZE    SZ_1M
 135
 136 #define IO_APB_PHYS     0x70000000
 137 #define IO_APB_VIRT     IOMEM(0xFE300000)
 138 #define IO_APB_SIZE     SZ_1M
 139
 140 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
 141 #define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
 142
 143 #define IO_TO_VIRT(n) ( \
 144         IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?           \
 145                 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :     \
 146         IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?             \
 147                 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :       \
 148         IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?             \
 149                 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :       \
 150         IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?           \
 151                 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :     \
 152         NULL)
 153
 154 #define IO_ADDRESS(n) (IO_TO_VIRT(n))
 155
 156 #endif