arch/arm/mach-tegra/irq.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@google.com>
   6  *
   7  * Copyright (C) 2010, NVIDIA Corporation
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26
  27 #include <asm/hardware/gic.h>
  28
  29 #include <mach/iomap.h>
  30 #include <mach/legacy_irq.h>
  31 #include <mach/suspend.h>
  32
  33 #include "board.h"
  34
  35 #define PMC_CTRL                0x0
  36 #define PMC_CTRL_LATCH_WAKEUPS  (1 << 5)
  37 #define PMC_WAKE_MASK           0xc
  38 #define PMC_WAKE_LEVEL          0x10
  39 #define PMC_WAKE_STATUS         0x14
  40 #define PMC_SW_WAKE_STATUS      0x18
  41 #define PMC_DPD_SAMPLE          0x20
  42
  43 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
  44
  45 static u32 tegra_lp0_wake_enb;
  46 static u32 tegra_lp0_wake_level;
  47 static u32 tegra_lp0_wake_level_any;
  48
  49 static void (*tegra_gic_mask_irq)(struct irq_data *d);
  50 static void (*tegra_gic_unmask_irq)(struct irq_data *d);
  51 static void (*tegra_gic_ack_irq)(struct irq_data *d);
  52
  53 /* ensures that sufficient time is passed for a register write to
  54  * serialize into the 32KHz domain */
  55 static void pmc_32kwritel(u32 val, unsigned long offs)
  56 {
  57         writel(val, pmc + offs);
  58         udelay(130);
  59 }
  60
  61 int tegra_set_lp1_wake(int irq, int enable)
  62 {
  63         return tegra_legacy_irq_set_wake(irq, enable);
  64 }
  65
  66 void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
  67 {
  68         u32 temp;
  69         u32 status;
  70         u32 lvl;
  71
  72         wake_level &= wake_enb;
  73         wake_any &= wake_enb;
  74
  75         wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
  76         wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
  77
  78         wake_enb |= tegra_lp0_wake_enb;
  79
  80         pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
  81         temp = readl(pmc + PMC_CTRL);
  82         temp |= PMC_CTRL_LATCH_WAKEUPS;
  83         pmc_32kwritel(temp, PMC_CTRL);
  84         temp &= ~PMC_CTRL_LATCH_WAKEUPS;
  85         pmc_32kwritel(temp, PMC_CTRL);
  86         status = readl(pmc + PMC_SW_WAKE_STATUS);
  87         lvl = readl(pmc + PMC_WAKE_LEVEL);
  88
  89         /* flip the wakeup trigger for any-edge triggered pads
  90          * which are currently asserting as wakeups */
  91         lvl ^= status;
  92         lvl &= wake_any;
  93
  94         wake_level |= lvl;
  95
  96         writel(wake_level, pmc + PMC_WAKE_LEVEL);
  97         /* Enable DPD sample to trigger sampling pads data and direction
  98          * in which pad will be driven during lp0 mode*/
  99         writel(0x1, pmc + PMC_DPD_SAMPLE);
 100
 101         writel(wake_enb, pmc + PMC_WAKE_MASK);
 102 }
 103
 104 static void tegra_mask(struct irq_data *d)
 105 {
 106         tegra_gic_mask_irq(d);
 107         tegra_legacy_mask_irq(d->irq);
 108 }
 109
 110 static void tegra_unmask(struct irq_data *d)
 111 {
 112         tegra_gic_unmask_irq(d);
 113         tegra_legacy_unmask_irq(d->irq);
 114 }
 115
 116 static void tegra_ack(struct irq_data *d)
 117 {
 118         tegra_legacy_force_irq_clr(d->irq);
 119         tegra_gic_ack_irq(d);
 120 }
 121
 122 static int tegra_retrigger(struct irq_data *d)
 123 {
 124         tegra_legacy_force_irq_set(d->irq);
 125         return 1;
 126 }
 127
 128 static struct irq_chip tegra_irq = {
 129         .name                   = "PPI",
 130         .irq_ack                = tegra_ack,
 131         .irq_mask               = tegra_mask,
 132         .irq_unmask             = tegra_unmask,
 133         .irq_retrigger          = tegra_retrigger,
 134 };
 135
 136 void __init tegra_init_irq(void)
 137 {
 138         struct irq_chip *gic;
 139         unsigned int i;
 140         int irq;
 141
 142         tegra_init_legacy_irq();
 143
 144         gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
 145                  IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 146
 147         gic = irq_get_chip(29);
 148         tegra_gic_unmask_irq = gic->irq_unmask;
 149         tegra_gic_mask_irq = gic->irq_mask;
 150         tegra_gic_ack_irq = gic->irq_ack;
 151 #ifdef CONFIG_SMP
 152         tegra_irq.irq_set_affinity = gic->irq_set_affinity;
 153 #endif
 154
 155         for (i = 0; i < INT_MAIN_NR; i++) {
 156                 irq = INT_PRI_BASE + i;
 157                 irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
 158                 set_irq_flags(irq, IRQF_VALID);
 159         }
 160 }