2 * arch/arm/mach-tegra/pci.c
4 * PCIe host controller driver for TEGRA(2) SOCs
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
12 * Bits taken from arch/arm/mach-dove/pcie.c
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/export.h>
37 #include <asm/sizes.h>
38 #include <asm/mach/pci.h>
40 #include <mach/iomap.h>
42 #include <mach/powergate.h>
46 /* register definitions */
47 #define AFI_OFFSET 0x3800
48 #define PADS_OFFSET 0x3000
49 #define RP0_OFFSET 0x0000
50 #define RP1_OFFSET 0x1000
52 #define AFI_AXI_BAR0_SZ 0x00
53 #define AFI_AXI_BAR1_SZ 0x04
54 #define AFI_AXI_BAR2_SZ 0x08
55 #define AFI_AXI_BAR3_SZ 0x0c
56 #define AFI_AXI_BAR4_SZ 0x10
57 #define AFI_AXI_BAR5_SZ 0x14
59 #define AFI_AXI_BAR0_START 0x18
60 #define AFI_AXI_BAR1_START 0x1c
61 #define AFI_AXI_BAR2_START 0x20
62 #define AFI_AXI_BAR3_START 0x24
63 #define AFI_AXI_BAR4_START 0x28
64 #define AFI_AXI_BAR5_START 0x2c
66 #define AFI_FPCI_BAR0 0x30
67 #define AFI_FPCI_BAR1 0x34
68 #define AFI_FPCI_BAR2 0x38
69 #define AFI_FPCI_BAR3 0x3c
70 #define AFI_FPCI_BAR4 0x40
71 #define AFI_FPCI_BAR5 0x44
73 #define AFI_CACHE_BAR0_SZ 0x48
74 #define AFI_CACHE_BAR0_ST 0x4c
75 #define AFI_CACHE_BAR1_SZ 0x50
76 #define AFI_CACHE_BAR1_ST 0x54
78 #define AFI_MSI_BAR_SZ 0x60
79 #define AFI_MSI_FPCI_BAR_ST 0x64
80 #define AFI_MSI_AXI_BAR_ST 0x68
82 #define AFI_CONFIGURATION 0xac
83 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
85 #define AFI_FPCI_ERROR_MASKS 0xb0
87 #define AFI_INTR_MASK 0xb4
88 #define AFI_INTR_MASK_INT_MASK (1 << 0)
89 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
91 #define AFI_INTR_CODE 0xb8
92 #define AFI_INTR_CODE_MASK 0xf
93 #define AFI_INTR_MASTER_ABORT 4
94 #define AFI_INTR_LEGACY 6
96 #define AFI_INTR_SIGNATURE 0xbc
97 #define AFI_SM_INTR_ENABLE 0xc4
99 #define AFI_AFI_INTR_ENABLE 0xc8
100 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
101 #define AFI_INTR_EN_INI_DECERR (1 << 1)
102 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
103 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
104 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
105 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
106 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
107 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
109 #define AFI_PCIE_CONFIG 0x0f8
110 #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
111 #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
116 #define AFI_FUSE 0x104
117 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
119 #define AFI_PEX0_CTRL 0x110
120 #define AFI_PEX1_CTRL 0x118
121 #define AFI_PEX_CTRL_RST (1 << 0)
122 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
124 #define RP_VEND_XP 0x00000F00
125 #define RP_VEND_XP_DL_UP (1 << 30)
127 #define RP_LINK_CONTROL_STATUS 0x00000090
128 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
130 #define PADS_CTL_SEL 0x0000009C
132 #define PADS_CTL 0x000000A0
133 #define PADS_CTL_IDDQ_1L (1 << 0)
134 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
135 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
137 #define PADS_PLL_CTL 0x000000B8
138 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
139 #define PADS_PLL_CTL_LOCKDET (1 << 8)
140 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
141 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
142 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
143 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
144 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
145 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
146 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
148 /* PMC access is required for PCIE xclk (un)clamping */
149 #define PMC_SCRATCH42 0x144
150 #define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
152 static void __iomem
*reg_pmc_base
= IO_ADDRESS(TEGRA_PMC_BASE
);
154 #define pmc_writel(value, reg) \
155 __raw_writel(value, reg_pmc_base + (reg))
156 #define pmc_readl(reg) \
157 __raw_readl(reg_pmc_base + (reg))
160 * Tegra2 defines 1GB in the AXI address map for PCIe.
162 * That address space is split into different regions, with sizes and
163 * offsets as follows:
165 * 0x80000000 - 0x80003fff - PCI controller registers
166 * 0x80004000 - 0x80103fff - PCI configuration space
167 * 0x80104000 - 0x80203fff - PCI extended configuration space
168 * 0x80203fff - 0x803fffff - unused
169 * 0x80400000 - 0x8040ffff - downstream IO
170 * 0x80410000 - 0x8fffffff - unused
171 * 0x90000000 - 0x9fffffff - non-prefetchable memory
172 * 0xa0000000 - 0xbfffffff - prefetchable memory
174 #define PCIE_REGS_SZ SZ_16K
175 #define PCIE_CFG_OFF PCIE_REGS_SZ
176 #define PCIE_CFG_SZ SZ_1M
177 #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
178 #define PCIE_EXT_CFG_SZ SZ_1M
179 #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
181 #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
182 #define MEM_SIZE_0 SZ_128M
183 #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
184 #define MEM_SIZE_1 SZ_128M
185 #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
186 #define PREFETCH_MEM_SIZE_0 SZ_128M
187 #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
188 #define PREFETCH_MEM_SIZE_1 SZ_128M
190 #define PCIE_CONF_BUS(b) ((b) << 16)
191 #define PCIE_CONF_DEV(d) ((d) << 11)
192 #define PCIE_CONF_FUNC(f) ((f) << 8)
193 #define PCIE_CONF_REG(r) \
194 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
196 struct tegra_pcie_port
{
203 char mem_space_name
[16];
204 char prefetch_space_name
[20];
205 struct resource res
[2];
208 struct tegra_pcie_info
{
209 struct tegra_pcie_port port
[2];
213 struct resource res_mmio
;
217 struct clk
*pcie_xclk
;
221 static struct tegra_pcie_info tegra_pcie
;
223 static inline void afi_writel(u32 value
, unsigned long offset
)
225 writel(value
, offset
+ AFI_OFFSET
+ tegra_pcie
.regs
);
228 static inline u32
afi_readl(unsigned long offset
)
230 return readl(offset
+ AFI_OFFSET
+ tegra_pcie
.regs
);
233 static inline void pads_writel(u32 value
, unsigned long offset
)
235 writel(value
, offset
+ PADS_OFFSET
+ tegra_pcie
.regs
);
238 static inline u32
pads_readl(unsigned long offset
)
240 return readl(offset
+ PADS_OFFSET
+ tegra_pcie
.regs
);
243 static struct tegra_pcie_port
*bus_to_port(int bus
)
247 for (i
= tegra_pcie
.num_ports
- 1; i
>= 0; i
--) {
248 int rbus
= tegra_pcie
.port
[i
].root_bus_nr
;
249 if (rbus
!= -1 && rbus
== bus
)
253 return i
>= 0 ? tegra_pcie
.port
+ i
: NULL
;
256 static int tegra_pcie_read_conf(struct pci_bus
*bus
, unsigned int devfn
,
257 int where
, int size
, u32
*val
)
259 struct tegra_pcie_port
*pp
= bus_to_port(bus
->number
);
265 return PCIBIOS_DEVICE_NOT_FOUND
;
268 addr
= pp
->base
+ (where
& ~0x3);
270 addr
= tegra_pcie
.regs
+ (PCIE_CONF_BUS(bus
->number
) +
271 PCIE_CONF_DEV(PCI_SLOT(devfn
)) +
272 PCIE_CONF_FUNC(PCI_FUNC(devfn
)) +
273 PCIE_CONF_REG(where
));
279 *val
= (*val
>> (8 * (where
& 3))) & 0xff;
281 *val
= (*val
>> (8 * (where
& 3))) & 0xffff;
283 return PCIBIOS_SUCCESSFUL
;
286 static int tegra_pcie_write_conf(struct pci_bus
*bus
, unsigned int devfn
,
287 int where
, int size
, u32 val
)
289 struct tegra_pcie_port
*pp
= bus_to_port(bus
->number
);
297 return PCIBIOS_DEVICE_NOT_FOUND
;
299 addr
= pp
->base
+ (where
& ~0x3);
301 addr
= tegra_pcie
.regs
+ (PCIE_CONF_BUS(bus
->number
) +
302 PCIE_CONF_DEV(PCI_SLOT(devfn
)) +
303 PCIE_CONF_FUNC(PCI_FUNC(devfn
)) +
304 PCIE_CONF_REG(where
));
309 return PCIBIOS_SUCCESSFUL
;
313 mask
= ~(0xffff << ((where
& 0x3) * 8));
315 mask
= ~(0xff << ((where
& 0x3) * 8));
317 return PCIBIOS_BAD_REGISTER_NUMBER
;
319 tmp
= readl(addr
) & mask
;
320 tmp
|= val
<< ((where
& 0x3) * 8);
323 return PCIBIOS_SUCCESSFUL
;
326 static struct pci_ops tegra_pcie_ops
= {
327 .read
= tegra_pcie_read_conf
,
328 .write
= tegra_pcie_write_conf
,
331 static void __devinit
tegra_pcie_fixup_bridge(struct pci_dev
*dev
)
335 if ((dev
->class >> 16) == PCI_BASE_CLASS_BRIDGE
) {
336 pci_read_config_word(dev
, PCI_COMMAND
, ®
);
337 reg
|= (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
338 PCI_COMMAND_MASTER
| PCI_COMMAND_SERR
);
339 pci_write_config_word(dev
, PCI_COMMAND
, reg
);
342 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, tegra_pcie_fixup_bridge
);
344 /* Tegra PCIE root complex wrongly reports device class */
345 static void __devinit
tegra_pcie_fixup_class(struct pci_dev
*dev
)
347 dev
->class = PCI_CLASS_BRIDGE_PCI
<< 8;
349 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0bf0, tegra_pcie_fixup_class
);
350 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0bf1, tegra_pcie_fixup_class
);
352 /* Tegra PCIE requires relaxed ordering */
353 static void __devinit
tegra_pcie_relax_enable(struct pci_dev
*dev
)
355 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_RELAX_EN
);
357 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, tegra_pcie_relax_enable
);
359 static int tegra_pcie_setup(int nr
, struct pci_sys_data
*sys
)
361 struct tegra_pcie_port
*pp
;
363 if (nr
>= tegra_pcie
.num_ports
)
366 pp
= tegra_pcie
.port
+ nr
;
367 pp
->root_bus_nr
= sys
->busnr
;
369 pci_ioremap_io(nr
* SZ_64K
, TEGRA_PCIE_IO_BASE
);
374 snprintf(pp
->mem_space_name
, sizeof(pp
->mem_space_name
),
375 "PCIe %d MEM", pp
->index
);
376 pp
->mem_space_name
[sizeof(pp
->mem_space_name
) - 1] = 0;
377 pp
->res
[0].name
= pp
->mem_space_name
;
378 if (pp
->index
== 0) {
379 pp
->res
[0].start
= MEM_BASE_0
;
380 pp
->res
[0].end
= pp
->res
[0].start
+ MEM_SIZE_0
- 1;
382 pp
->res
[0].start
= MEM_BASE_1
;
383 pp
->res
[0].end
= pp
->res
[0].start
+ MEM_SIZE_1
- 1;
385 pp
->res
[0].flags
= IORESOURCE_MEM
;
386 if (request_resource(&iomem_resource
, &pp
->res
[0]))
387 panic("Request PCIe Memory resource failed\n");
388 pci_add_resource_offset(&sys
->resources
, &pp
->res
[0], sys
->mem_offset
);
391 * IORESOURCE_MEM | IORESOURCE_PREFETCH
393 snprintf(pp
->prefetch_space_name
, sizeof(pp
->prefetch_space_name
),
394 "PCIe %d PREFETCH MEM", pp
->index
);
395 pp
->prefetch_space_name
[sizeof(pp
->prefetch_space_name
) - 1] = 0;
396 pp
->res
[1].name
= pp
->prefetch_space_name
;
397 if (pp
->index
== 0) {
398 pp
->res
[1].start
= PREFETCH_MEM_BASE_0
;
399 pp
->res
[1].end
= pp
->res
[1].start
+ PREFETCH_MEM_SIZE_0
- 1;
401 pp
->res
[1].start
= PREFETCH_MEM_BASE_1
;
402 pp
->res
[1].end
= pp
->res
[1].start
+ PREFETCH_MEM_SIZE_1
- 1;
404 pp
->res
[1].flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
405 if (request_resource(&iomem_resource
, &pp
->res
[1]))
406 panic("Request PCIe Prefetch Memory resource failed\n");
407 pci_add_resource_offset(&sys
->resources
, &pp
->res
[1], sys
->mem_offset
);
412 static int tegra_pcie_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
414 return INT_PCIE_INTR
;
417 static struct pci_bus __init
*tegra_pcie_scan_bus(int nr
,
418 struct pci_sys_data
*sys
)
420 struct tegra_pcie_port
*pp
;
422 if (nr
>= tegra_pcie
.num_ports
)
425 pp
= tegra_pcie
.port
+ nr
;
426 pp
->root_bus_nr
= sys
->busnr
;
428 return pci_scan_root_bus(NULL
, sys
->busnr
, &tegra_pcie_ops
, sys
,
432 static struct hw_pci tegra_pcie_hw __initdata
= {
434 .setup
= tegra_pcie_setup
,
435 .scan
= tegra_pcie_scan_bus
,
436 .map_irq
= tegra_pcie_map_irq
,
440 static irqreturn_t
tegra_pcie_isr(int irq
, void *arg
)
442 const char *err_msg
[] = {
449 "Response decoding error",
450 "AXI response decoding error",
451 "Transcation timeout",
456 code
= afi_readl(AFI_INTR_CODE
) & AFI_INTR_CODE_MASK
;
457 signature
= afi_readl(AFI_INTR_SIGNATURE
);
458 afi_writel(0, AFI_INTR_CODE
);
460 if (code
== AFI_INTR_LEGACY
)
463 if (code
>= ARRAY_SIZE(err_msg
))
467 * do not pollute kernel log with master abort reports since they
468 * happen a lot during enumeration
470 if (code
== AFI_INTR_MASTER_ABORT
)
471 pr_debug("PCIE: %s, signature: %08x\n", err_msg
[code
], signature
);
473 pr_err("PCIE: %s, signature: %08x\n", err_msg
[code
], signature
);
478 static void tegra_pcie_setup_translations(void)
484 /* Bar 0: config Bar */
485 fpci_bar
= ((u32
)0xfdff << 16);
487 axi_address
= TEGRA_PCIE_BASE
+ PCIE_CFG_OFF
;
488 afi_writel(axi_address
, AFI_AXI_BAR0_START
);
489 afi_writel(size
>> 12, AFI_AXI_BAR0_SZ
);
490 afi_writel(fpci_bar
, AFI_FPCI_BAR0
);
492 /* Bar 1: extended config Bar */
493 fpci_bar
= ((u32
)0xfe1 << 20);
494 size
= PCIE_EXT_CFG_SZ
;
495 axi_address
= TEGRA_PCIE_BASE
+ PCIE_EXT_CFG_OFF
;
496 afi_writel(axi_address
, AFI_AXI_BAR1_START
);
497 afi_writel(size
>> 12, AFI_AXI_BAR1_SZ
);
498 afi_writel(fpci_bar
, AFI_FPCI_BAR1
);
500 /* Bar 2: downstream IO bar */
501 fpci_bar
= ((__u32
)0xfdfc << 16);
503 axi_address
= TEGRA_PCIE_IO_BASE
;
504 afi_writel(axi_address
, AFI_AXI_BAR2_START
);
505 afi_writel(size
>> 12, AFI_AXI_BAR2_SZ
);
506 afi_writel(fpci_bar
, AFI_FPCI_BAR2
);
508 /* Bar 3: prefetchable memory BAR */
509 fpci_bar
= (((PREFETCH_MEM_BASE_0
>> 12) & 0x0fffffff) << 4) | 0x1;
510 size
= PREFETCH_MEM_SIZE_0
+ PREFETCH_MEM_SIZE_1
;
511 axi_address
= PREFETCH_MEM_BASE_0
;
512 afi_writel(axi_address
, AFI_AXI_BAR3_START
);
513 afi_writel(size
>> 12, AFI_AXI_BAR3_SZ
);
514 afi_writel(fpci_bar
, AFI_FPCI_BAR3
);
516 /* Bar 4: non prefetchable memory BAR */
517 fpci_bar
= (((MEM_BASE_0
>> 12) & 0x0FFFFFFF) << 4) | 0x1;
518 size
= MEM_SIZE_0
+ MEM_SIZE_1
;
519 axi_address
= MEM_BASE_0
;
520 afi_writel(axi_address
, AFI_AXI_BAR4_START
);
521 afi_writel(size
>> 12, AFI_AXI_BAR4_SZ
);
522 afi_writel(fpci_bar
, AFI_FPCI_BAR4
);
524 /* Bar 5: NULL out the remaining BAR as it is not used */
528 afi_writel(axi_address
, AFI_AXI_BAR5_START
);
529 afi_writel(size
>> 12, AFI_AXI_BAR5_SZ
);
530 afi_writel(fpci_bar
, AFI_FPCI_BAR5
);
532 /* map all upstream transactions as uncached */
533 afi_writel(PHYS_OFFSET
, AFI_CACHE_BAR0_ST
);
534 afi_writel(0, AFI_CACHE_BAR0_SZ
);
535 afi_writel(0, AFI_CACHE_BAR1_ST
);
536 afi_writel(0, AFI_CACHE_BAR1_SZ
);
539 afi_writel(0, AFI_MSI_FPCI_BAR_ST
);
540 afi_writel(0, AFI_MSI_BAR_SZ
);
541 afi_writel(0, AFI_MSI_AXI_BAR_ST
);
542 afi_writel(0, AFI_MSI_BAR_SZ
);
545 static int tegra_pcie_enable_controller(void)
550 /* Enable slot clock and pulse the reset signals */
551 for (i
= 0, reg
= AFI_PEX0_CTRL
; i
< 2; i
++, reg
+= 0x8) {
552 val
= afi_readl(reg
) | AFI_PEX_CTRL_REFCLK_EN
;
553 afi_writel(val
, reg
);
554 val
&= ~AFI_PEX_CTRL_RST
;
555 afi_writel(val
, reg
);
557 val
= afi_readl(reg
) | AFI_PEX_CTRL_RST
;
558 afi_writel(val
, reg
);
561 /* Enable dual controller and both ports */
562 val
= afi_readl(AFI_PCIE_CONFIG
);
563 val
&= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE
|
564 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE
|
565 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK
);
566 val
|= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL
;
567 afi_writel(val
, AFI_PCIE_CONFIG
);
569 val
= afi_readl(AFI_FUSE
) & ~AFI_FUSE_PCIE_T0_GEN2_DIS
;
570 afi_writel(val
, AFI_FUSE
);
572 /* Initialze internal PHY, enable up to 16 PCIE lanes */
573 pads_writel(0x0, PADS_CTL_SEL
);
575 /* override IDDQ to 1 on all 4 lanes */
576 val
= pads_readl(PADS_CTL
) | PADS_CTL_IDDQ_1L
;
577 pads_writel(val
, PADS_CTL
);
580 * set up PHY PLL inputs select PLLE output as refclock,
581 * set TX ref sel to div10 (not div5)
583 val
= pads_readl(PADS_PLL_CTL
);
584 val
&= ~(PADS_PLL_CTL_REFCLK_MASK
| PADS_PLL_CTL_TXCLKREF_MASK
);
585 val
|= (PADS_PLL_CTL_REFCLK_INTERNAL_CML
| PADS_PLL_CTL_TXCLKREF_DIV10
);
586 pads_writel(val
, PADS_PLL_CTL
);
588 /* take PLL out of reset */
589 val
= pads_readl(PADS_PLL_CTL
) | PADS_PLL_CTL_RST_B4SM
;
590 pads_writel(val
, PADS_PLL_CTL
);
593 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
594 * This doesn't exist in the documentation
596 pads_writel(0xfa5cfa5c, 0xc8);
598 /* Wait for the PLL to lock */
601 val
= pads_readl(PADS_PLL_CTL
);
602 usleep_range(1000, 1000);
603 if (--timeout
== 0) {
604 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
607 } while (!(val
& PADS_PLL_CTL_LOCKDET
));
609 /* turn off IDDQ override */
610 val
= pads_readl(PADS_CTL
) & ~PADS_CTL_IDDQ_1L
;
611 pads_writel(val
, PADS_CTL
);
613 /* enable TX/RX data */
614 val
= pads_readl(PADS_CTL
);
615 val
|= (PADS_CTL_TX_DATA_EN_1L
| PADS_CTL_RX_DATA_EN_1L
);
616 pads_writel(val
, PADS_CTL
);
618 /* Take the PCIe interface module out of reset */
619 tegra_periph_reset_deassert(tegra_pcie
.pcie_xclk
);
621 /* Finally enable PCIe */
622 val
= afi_readl(AFI_CONFIGURATION
) | AFI_CONFIGURATION_EN_FPCI
;
623 afi_writel(val
, AFI_CONFIGURATION
);
625 val
= (AFI_INTR_EN_INI_SLVERR
| AFI_INTR_EN_INI_DECERR
|
626 AFI_INTR_EN_TGT_SLVERR
| AFI_INTR_EN_TGT_DECERR
|
627 AFI_INTR_EN_TGT_WRERR
| AFI_INTR_EN_DFPCI_DECERR
);
628 afi_writel(val
, AFI_AFI_INTR_ENABLE
);
629 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE
);
631 /* FIXME: No MSI for now, only INT */
632 afi_writel(AFI_INTR_MASK_INT_MASK
, AFI_INTR_MASK
);
634 /* Disable all execptions */
635 afi_writel(0, AFI_FPCI_ERROR_MASKS
);
640 static void tegra_pcie_xclk_clamp(bool clamp
)
644 reg
= pmc_readl(PMC_SCRATCH42
) & ~PMC_SCRATCH42_PCX_CLAMP
;
647 reg
|= PMC_SCRATCH42_PCX_CLAMP
;
649 pmc_writel(reg
, PMC_SCRATCH42
);
652 static void tegra_pcie_power_off(void)
654 tegra_periph_reset_assert(tegra_pcie
.pcie_xclk
);
655 tegra_periph_reset_assert(tegra_pcie
.afi_clk
);
656 tegra_periph_reset_assert(tegra_pcie
.pex_clk
);
658 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE
);
659 tegra_pcie_xclk_clamp(true);
662 static int tegra_pcie_power_regate(void)
666 tegra_pcie_power_off();
668 tegra_pcie_xclk_clamp(true);
670 tegra_periph_reset_assert(tegra_pcie
.pcie_xclk
);
671 tegra_periph_reset_assert(tegra_pcie
.afi_clk
);
673 err
= tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE
,
676 pr_err("PCIE: powerup sequence failed: %d\n", err
);
680 tegra_periph_reset_deassert(tegra_pcie
.afi_clk
);
682 tegra_pcie_xclk_clamp(false);
684 clk_prepare_enable(tegra_pcie
.afi_clk
);
685 clk_prepare_enable(tegra_pcie
.pex_clk
);
686 return clk_prepare_enable(tegra_pcie
.pll_e
);
689 static int tegra_pcie_clocks_get(void)
693 tegra_pcie
.pex_clk
= clk_get(NULL
, "pex");
694 if (IS_ERR(tegra_pcie
.pex_clk
))
695 return PTR_ERR(tegra_pcie
.pex_clk
);
697 tegra_pcie
.afi_clk
= clk_get(NULL
, "afi");
698 if (IS_ERR(tegra_pcie
.afi_clk
)) {
699 err
= PTR_ERR(tegra_pcie
.afi_clk
);
703 tegra_pcie
.pcie_xclk
= clk_get(NULL
, "pcie_xclk");
704 if (IS_ERR(tegra_pcie
.pcie_xclk
)) {
705 err
= PTR_ERR(tegra_pcie
.pcie_xclk
);
709 tegra_pcie
.pll_e
= clk_get_sys(NULL
, "pll_e");
710 if (IS_ERR(tegra_pcie
.pll_e
)) {
711 err
= PTR_ERR(tegra_pcie
.pll_e
);
718 clk_put(tegra_pcie
.pcie_xclk
);
720 clk_put(tegra_pcie
.afi_clk
);
722 clk_put(tegra_pcie
.pex_clk
);
727 static void tegra_pcie_clocks_put(void)
729 clk_put(tegra_pcie
.pll_e
);
730 clk_put(tegra_pcie
.pcie_xclk
);
731 clk_put(tegra_pcie
.afi_clk
);
732 clk_put(tegra_pcie
.pex_clk
);
735 static int __init
tegra_pcie_get_resources(void)
739 err
= tegra_pcie_clocks_get();
741 pr_err("PCIE: failed to get clocks: %d\n", err
);
745 err
= tegra_pcie_power_regate();
747 pr_err("PCIE: failed to power up: %d\n", err
);
751 tegra_pcie
.regs
= ioremap_nocache(TEGRA_PCIE_BASE
, PCIE_IOMAP_SZ
);
752 if (tegra_pcie
.regs
== NULL
) {
753 pr_err("PCIE: Failed to map PCI/AFI registers\n");
758 err
= request_irq(INT_PCIE_INTR
, tegra_pcie_isr
,
759 IRQF_SHARED
, "PCIE", &tegra_pcie
);
761 pr_err("PCIE: Failed to register IRQ: %d\n", err
);
764 set_irq_flags(INT_PCIE_INTR
, IRQF_VALID
);
769 iounmap(tegra_pcie
.regs
);
771 tegra_pcie_power_off();
773 tegra_pcie_clocks_put();
779 * FIXME: If there are no PCIe cards attached, then calling this function
780 * can result in the increase of the bootup time as there are big timeout
783 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
784 static bool tegra_pcie_check_link(struct tegra_pcie_port
*pp
, int idx
,
792 timeout
= TEGRA_PCIE_LINKUP_TIMEOUT
;
794 reg
= readl(pp
->base
+ RP_VEND_XP
);
796 if (reg
& RP_VEND_XP_DL_UP
)
804 pr_err("PCIE: port %d: link down, retrying\n", idx
);
808 timeout
= TEGRA_PCIE_LINKUP_TIMEOUT
;
810 reg
= readl(pp
->base
+ RP_LINK_CONTROL_STATUS
);
812 if (reg
& 0x20000000)
820 /* Pulse the PEX reset */
821 reg
= afi_readl(reset_reg
) | AFI_PEX_CTRL_RST
;
822 afi_writel(reg
, reset_reg
);
824 reg
= afi_readl(reset_reg
) & ~AFI_PEX_CTRL_RST
;
825 afi_writel(reg
, reset_reg
);
833 static void __init
tegra_pcie_add_port(int index
, u32 offset
, u32 reset_reg
)
835 struct tegra_pcie_port
*pp
;
837 pp
= tegra_pcie
.port
+ tegra_pcie
.num_ports
;
840 pp
->base
= tegra_pcie
.regs
+ offset
;
841 pp
->link_up
= tegra_pcie_check_link(pp
, index
, reset_reg
);
845 printk(KERN_INFO
"PCIE: port %d: link down, ignoring\n", index
);
849 tegra_pcie
.num_ports
++;
851 pp
->root_bus_nr
= -1;
852 memset(pp
->res
, 0, sizeof(pp
->res
));
855 int __init
tegra_pcie_init(bool init_port0
, bool init_port1
)
859 if (!(init_port0
|| init_port1
))
864 err
= tegra_pcie_get_resources();
868 err
= tegra_pcie_enable_controller();
872 /* setup the AFI address translations */
873 tegra_pcie_setup_translations();
876 tegra_pcie_add_port(0, RP0_OFFSET
, AFI_PEX0_CTRL
);
879 tegra_pcie_add_port(1, RP1_OFFSET
, AFI_PEX1_CTRL
);
881 pci_common_init(&tegra_pcie_hw
);