arch/arm/mach-tegra/pinmux.c

   1 /*
   2  * linux/arch/arm/mach-tegra/pinmux.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <mach/iomap.h>
  26 #include <mach/pinmux.h>
  27
  28 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
  29 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
  30 #define LPMD(reg)       (((reg) >> 4) & 0x3)
  31 #define DRVDN(reg)      (((reg) >> 12) & 0x1f)
  32 #define DRVUP(reg)      (((reg) >> 20) & 0x1f)
  33 #define SLWR(reg)       (((reg) >> 28) & 0x3)
  34 #define SLWF(reg)       (((reg) >> 30) & 0x3)
  35
  36 static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
  37 static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
  38
  39 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
  40         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
  41         [TEGRA_MUX_APB_CLK] = "APB_CLK",
  42         [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
  43         [TEGRA_MUX_CRT] = "CRT",
  44         [TEGRA_MUX_DAP1] = "DAP1",
  45         [TEGRA_MUX_DAP2] = "DAP2",
  46         [TEGRA_MUX_DAP3] = "DAP3",
  47         [TEGRA_MUX_DAP4] = "DAP4",
  48         [TEGRA_MUX_DAP5] = "DAP5",
  49         [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
  50         [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
  51         [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
  52         [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
  53         [TEGRA_MUX_GMI] = "GMI",
  54         [TEGRA_MUX_GMI_INT] = "GMI_INT",
  55         [TEGRA_MUX_HDMI] = "HDMI",
  56         [TEGRA_MUX_I2C] = "I2C",
  57         [TEGRA_MUX_I2C2] = "I2C2",
  58         [TEGRA_MUX_I2C3] = "I2C3",
  59         [TEGRA_MUX_IDE] = "IDE",
  60         [TEGRA_MUX_IRDA] = "IRDA",
  61         [TEGRA_MUX_KBC] = "KBC",
  62         [TEGRA_MUX_MIO] = "MIO",
  63         [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
  64         [TEGRA_MUX_NAND] = "NAND",
  65         [TEGRA_MUX_OSC] = "OSC",
  66         [TEGRA_MUX_OWR] = "OWR",
  67         [TEGRA_MUX_PCIE] = "PCIE",
  68         [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
  69         [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
  70         [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
  71         [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
  72         [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
  73         [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
  74         [TEGRA_MUX_PWM] = "PWM",
  75         [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
  76         [TEGRA_MUX_PWR_ON] = "PWR_ON",
  77         [TEGRA_MUX_RTCK] = "RTCK",
  78         [TEGRA_MUX_SDIO1] = "SDIO1",
  79         [TEGRA_MUX_SDIO2] = "SDIO2",
  80         [TEGRA_MUX_SDIO3] = "SDIO3",
  81         [TEGRA_MUX_SDIO4] = "SDIO4",
  82         [TEGRA_MUX_SFLASH] = "SFLASH",
  83         [TEGRA_MUX_SPDIF] = "SPDIF",
  84         [TEGRA_MUX_SPI1] = "SPI1",
  85         [TEGRA_MUX_SPI2] = "SPI2",
  86         [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
  87         [TEGRA_MUX_SPI3] = "SPI3",
  88         [TEGRA_MUX_SPI4] = "SPI4",
  89         [TEGRA_MUX_TRACE] = "TRACE",
  90         [TEGRA_MUX_TWC] = "TWC",
  91         [TEGRA_MUX_UARTA] = "UARTA",
  92         [TEGRA_MUX_UARTB] = "UARTB",
  93         [TEGRA_MUX_UARTC] = "UARTC",
  94         [TEGRA_MUX_UARTD] = "UARTD",
  95         [TEGRA_MUX_UARTE] = "UARTE",
  96         [TEGRA_MUX_ULPI] = "ULPI",
  97         [TEGRA_MUX_VI] = "VI",
  98         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
  99         [TEGRA_MUX_XIO] = "XIO",
 100         [TEGRA_MUX_SAFE] = "<safe>",
 101 };
 102
 103 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
 104         [TEGRA_DRIVE_DIV_8] = "DIV_8",
 105         [TEGRA_DRIVE_DIV_4] = "DIV_4",
 106         [TEGRA_DRIVE_DIV_2] = "DIV_2",
 107         [TEGRA_DRIVE_DIV_1] = "DIV_1",
 108 };
 109
 110 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
 111         [TEGRA_SLEW_FASTEST] = "FASTEST",
 112         [TEGRA_SLEW_FAST] = "FAST",
 113         [TEGRA_SLEW_SLOW] = "SLOW",
 114         [TEGRA_SLEW_SLOWEST] = "SLOWEST",
 115 };
 116
 117 static DEFINE_SPINLOCK(mux_lock);
 118
 119 static const char *pingroup_name(enum tegra_pingroup pg)
 120 {
 121         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
 122                 return "<UNKNOWN>";
 123
 124         return pingroups[pg].name;
 125 }
 126
 127 static const char *func_name(enum tegra_mux_func func)
 128 {
 129         if (func == TEGRA_MUX_RSVD1)
 130                 return "RSVD1";
 131
 132         if (func == TEGRA_MUX_RSVD2)
 133                 return "RSVD2";
 134
 135         if (func == TEGRA_MUX_RSVD3)
 136                 return "RSVD3";
 137
 138         if (func == TEGRA_MUX_RSVD4)
 139                 return "RSVD4";
 140
 141         if (func == TEGRA_MUX_NONE)
 142                 return "NONE";
 143
 144         if (func < 0 || func >=  TEGRA_MAX_MUX)
 145                 return "<UNKNOWN>";
 146
 147         return tegra_mux_names[func];
 148 }
 149
 150
 151 static const char *tri_name(unsigned long val)
 152 {
 153         return val ? "TRISTATE" : "NORMAL";
 154 }
 155
 156 static const char *pupd_name(unsigned long val)
 157 {
 158         switch (val) {
 159         case 0:
 160                 return "NORMAL";
 161
 162         case 1:
 163                 return "PULL_DOWN";
 164
 165         case 2:
 166                 return "PULL_UP";
 167
 168         default:
 169                 return "RSVD";
 170         }
 171 }
 172
 173
 174 static inline unsigned long pg_readl(unsigned long offset)
 175 {
 176         return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
 177 }
 178
 179 static inline void pg_writel(unsigned long value, unsigned long offset)
 180 {
 181         writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
 182 }
 183
 184 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
 185 {
 186         int mux = -1;
 187         int i;
 188         unsigned long reg;
 189         unsigned long flags;
 190         enum tegra_pingroup pg = config->pingroup;
 191         enum tegra_mux_func func = config->func;
 192
 193         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
 194                 return -ERANGE;
 195
 196         if (pingroups[pg].mux_reg < 0)
 197                 return -EINVAL;
 198
 199         if (func < 0)
 200                 return -ERANGE;
 201
 202         if (func == TEGRA_MUX_SAFE)
 203                 func = pingroups[pg].func_safe;
 204
 205         if (func & TEGRA_MUX_RSVD) {
 206                 mux = func & 0x3;
 207         } else {
 208                 for (i = 0; i < 4; i++) {
 209                         if (pingroups[pg].funcs[i] == func) {
 210                                 mux = i;
 211                                 break;
 212                         }
 213                 }
 214         }
 215
 216         if (mux < 0)
 217                 return -EINVAL;
 218
 219         spin_lock_irqsave(&mux_lock, flags);
 220
 221         reg = pg_readl(pingroups[pg].mux_reg);
 222         reg &= ~(0x3 << pingroups[pg].mux_bit);
 223         reg |= mux << pingroups[pg].mux_bit;
 224         pg_writel(reg, pingroups[pg].mux_reg);
 225
 226         spin_unlock_irqrestore(&mux_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
 232         enum tegra_tristate tristate)
 233 {
 234         unsigned long reg;
 235         unsigned long flags;
 236
 237         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
 238                 return -ERANGE;
 239
 240         if (pingroups[pg].tri_reg < 0)
 241                 return -EINVAL;
 242
 243         spin_lock_irqsave(&mux_lock, flags);
 244
 245         reg = pg_readl(pingroups[pg].tri_reg);
 246         reg &= ~(0x1 << pingroups[pg].tri_bit);
 247         if (tristate)
 248                 reg |= 1 << pingroups[pg].tri_bit;
 249         pg_writel(reg, pingroups[pg].tri_reg);
 250
 251         spin_unlock_irqrestore(&mux_lock, flags);
 252
 253         return 0;
 254 }
 255
 256 int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
 257         enum tegra_pullupdown pupd)
 258 {
 259         unsigned long reg;
 260         unsigned long flags;
 261
 262         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
 263                 return -ERANGE;
 264
 265         if (pingroups[pg].pupd_reg < 0)
 266                 return -EINVAL;
 267
 268         if (pupd != TEGRA_PUPD_NORMAL &&
 269             pupd != TEGRA_PUPD_PULL_DOWN &&
 270             pupd != TEGRA_PUPD_PULL_UP)
 271                 return -EINVAL;
 272
 273
 274         spin_lock_irqsave(&mux_lock, flags);
 275
 276         reg = pg_readl(pingroups[pg].pupd_reg);
 277         reg &= ~(0x3 << pingroups[pg].pupd_bit);
 278         reg |= pupd << pingroups[pg].pupd_bit;
 279         pg_writel(reg, pingroups[pg].pupd_reg);
 280
 281         spin_unlock_irqrestore(&mux_lock, flags);
 282
 283         return 0;
 284 }
 285
 286 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
 287 {
 288         enum tegra_pingroup pingroup = config->pingroup;
 289         enum tegra_mux_func func     = config->func;
 290         enum tegra_pullupdown pupd   = config->pupd;
 291         enum tegra_tristate tristate = config->tristate;
 292         int err;
 293
 294         if (pingroups[pingroup].mux_reg >= 0) {
 295                 err = tegra_pinmux_set_func(config);
 296                 if (err < 0)
 297                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
 298                                pingroup_name(pingroup), func_name(func), err);
 299         }
 300
 301         if (pingroups[pingroup].pupd_reg >= 0) {
 302                 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
 303                 if (err < 0)
 304                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
 305                                pingroup_name(pingroup), pupd_name(pupd), err);
 306         }
 307
 308         if (pingroups[pingroup].tri_reg >= 0) {
 309                 err = tegra_pinmux_set_tristate(pingroup, tristate);
 310                 if (err < 0)
 311                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
 312                                pingroup_name(pingroup), tri_name(func), err);
 313         }
 314 }
 315
 316 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
 317 {
 318         int i;
 319
 320         for (i = 0; i < len; i++)
 321                 tegra_pinmux_config_pingroup(&config[i]);
 322 }
 323
 324 static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
 325 {
 326         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
 327                 return "<UNKNOWN>";
 328
 329         return drive_pingroups[pg].name;
 330 }
 331
 332 static const char *enable_name(unsigned long val)
 333 {
 334         return val ? "ENABLE" : "DISABLE";
 335 }
 336
 337 static const char *drive_name(unsigned long val)
 338 {
 339         if (val >= TEGRA_MAX_DRIVE)
 340                 return "<UNKNOWN>";
 341
 342         return tegra_drive_names[val];
 343 }
 344
 345 static const char *slew_name(unsigned long val)
 346 {
 347         if (val >= TEGRA_MAX_SLEW)
 348                 return "<UNKNOWN>";
 349
 350         return tegra_slew_names[val];
 351 }
 352
 353 static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
 354         enum tegra_hsm hsm)
 355 {
 356         unsigned long flags;
 357         u32 reg;
 358         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
 359                 return -ERANGE;
 360
 361         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
 362                 return -EINVAL;
 363
 364         spin_lock_irqsave(&mux_lock, flags);
 365
 366         reg = pg_readl(drive_pingroups[pg].reg);
 367         if (hsm == TEGRA_HSM_ENABLE)
 368                 reg |= (1 << 2);
 369         else
 370                 reg &= ~(1 << 2);
 371         pg_writel(reg, drive_pingroups[pg].reg);
 372
 373         spin_unlock_irqrestore(&mux_lock, flags);
 374
 375         return 0;
 376 }
 377
 378 static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
 379         enum tegra_schmitt schmitt)
 380 {
 381         unsigned long flags;
 382         u32 reg;
 383         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
 384                 return -ERANGE;
 385
 386         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
 387                 return -EINVAL;
 388
 389         spin_lock_irqsave(&mux_lock, flags);
 390
 391         reg = pg_readl(drive_pingroups[pg].reg);
 392         if (schmitt == TEGRA_SCHMITT_ENABLE)
 393                 reg |= (1 << 3);
 394         else
 395                 reg &= ~(1 << 3);
 396         pg_writel(reg, drive_pingroups[pg].reg);
 397
 398         spin_unlock_irqrestore(&mux_lock, flags);
 399
 400         return 0;
 401 }
 402
 403 static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
 404         enum tegra_drive drive)
 405 {
 406         unsigned long flags;
 407         u32 reg;
 408         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
 409                 return -ERANGE;
 410
 411         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
 412                 return -EINVAL;
 413
 414         spin_lock_irqsave(&mux_lock, flags);
 415
 416         reg = pg_readl(drive_pingroups[pg].reg);
 417         reg &= ~(0x3 << 4);
 418         reg |= drive << 4;
 419         pg_writel(reg, drive_pingroups[pg].reg);
 420
 421         spin_unlock_irqrestore(&mux_lock, flags);
 422
 423         return 0;
 424 }
 425
 426 static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
 427         enum tegra_pull_strength pull_down)
 428 {
 429         unsigned long flags;
 430         u32 reg;
 431         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
 432                 return -ERANGE;
 433
 434         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
 435                 return -EINVAL;
 436
 437         spin_lock_irqsave(&mux_lock, flags);
 438
 439         reg = pg_readl(drive_pingroups[pg].reg);
 440         reg &= ~(0x1f << 12);
 441         reg |= pull_down << 12;
 442         pg_writel(reg, drive_pingroups[pg].reg);
 443
 444         spin_unlock_irqrestore(&mux_lock, flags);
 445
 446         return 0;
 447 }
 448
 449 static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
 450         enum tegra_pull_strength pull_up)
 451 {
 452         unsigned long flags;
 453         u32 reg;
 454         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
 455                 return -ERANGE;
 456
 457         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
 458                 return -EINVAL;
 459
 460         spin_lock_irqsave(&mux_lock, flags);
 461
 462         reg = pg_readl(drive_pingroups[pg].reg);
 463         reg &= ~(0x1f << 12);
 464         reg |= pull_up << 12;
 465         pg_writel(reg, drive_pingroups[pg].reg);
 466
 467         spin_unlock_irqrestore(&mux_lock, flags);
 468
 469         return 0;
 470 }
 471
 472 static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
 473         enum tegra_slew slew_rising)
 474 {
 475         unsigned long flags;
 476         u32 reg;
 477         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
 478                 return -ERANGE;
 479
 480         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
 481                 return -EINVAL;
 482
 483         spin_lock_irqsave(&mux_lock, flags);
 484
 485         reg = pg_readl(drive_pingroups[pg].reg);
 486         reg &= ~(0x3 << 28);
 487         reg |= slew_rising << 28;
 488         pg_writel(reg, drive_pingroups[pg].reg);
 489
 490         spin_unlock_irqrestore(&mux_lock, flags);
 491
 492         return 0;
 493 }
 494
 495 static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
 496         enum tegra_slew slew_falling)
 497 {
 498         unsigned long flags;
 499         u32 reg;
 500         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
 501                 return -ERANGE;
 502
 503         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
 504                 return -EINVAL;
 505
 506         spin_lock_irqsave(&mux_lock, flags);
 507
 508         reg = pg_readl(drive_pingroups[pg].reg);
 509         reg &= ~(0x3 << 30);
 510         reg |= slew_falling << 30;
 511         pg_writel(reg, drive_pingroups[pg].reg);
 512
 513         spin_unlock_irqrestore(&mux_lock, flags);
 514
 515         return 0;
 516 }
 517
 518 static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
 519                                           enum tegra_hsm hsm,
 520                                           enum tegra_schmitt schmitt,
 521                                           enum tegra_drive drive,
 522                                           enum tegra_pull_strength pull_down,
 523                                           enum tegra_pull_strength pull_up,
 524                                           enum tegra_slew slew_rising,
 525                                           enum tegra_slew slew_falling)
 526 {
 527         int err;
 528
 529         err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
 530         if (err < 0)
 531                 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
 532                         drive_pinmux_name(pingroup),
 533                         enable_name(hsm), err);
 534
 535         err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
 536         if (err < 0)
 537                 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
 538                         drive_pinmux_name(pingroup),
 539                         enable_name(schmitt), err);
 540
 541         err = tegra_drive_pinmux_set_drive(pingroup, drive);
 542         if (err < 0)
 543                 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
 544                         drive_pinmux_name(pingroup),
 545                         drive_name(drive), err);
 546
 547         err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
 548         if (err < 0)
 549                 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
 550                         drive_pinmux_name(pingroup),
 551                         pull_down, err);
 552
 553         err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
 554         if (err < 0)
 555                 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
 556                         drive_pinmux_name(pingroup),
 557                         pull_up, err);
 558
 559         err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
 560         if (err < 0)
 561                 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
 562                         drive_pinmux_name(pingroup),
 563                         slew_name(slew_rising), err);
 564
 565         err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
 566         if (err < 0)
 567                 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
 568                         drive_pinmux_name(pingroup),
 569                         slew_name(slew_falling), err);
 570 }
 571
 572 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
 573         int len)
 574 {
 575         int i;
 576
 577         for (i = 0; i < len; i++)
 578                 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
 579                                                      config[i].hsm,
 580                                                      config[i].schmitt,
 581                                                      config[i].drive,
 582                                                      config[i].pull_down,
 583                                                      config[i].pull_up,
 584                                                      config[i].slew_rising,
 585                                                      config[i].slew_falling);
 586 }
 587
 588 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
 589         int len)
 590 {
 591         int i;
 592         struct tegra_pingroup_config c;
 593
 594         for (i = 0; i < len; i++) {
 595                 int err;
 596                 c = config[i];
 597                 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
 598                         WARN_ON(1);
 599                         continue;
 600                 }
 601                 c.func = pingroups[c.pingroup].func_safe;
 602                 err = tegra_pinmux_set_func(&c);
 603                 if (err < 0)
 604                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
 605                                "%s to %s\n", __func__, err,
 606                                pingroup_name(c.pingroup), func_name(c.func));
 607         }
 608 }
 609
 610 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
 611         int len)
 612 {
 613         int i;
 614
 615         for (i = 0; i < len; i++) {
 616                 int err;
 617                 if (config[i].pingroup < 0 ||
 618                     config[i].pingroup >= TEGRA_MAX_PINGROUP) {
 619                         WARN_ON(1);
 620                         continue;
 621                 }
 622                 err = tegra_pinmux_set_func(&config[i]);
 623                 if (err < 0)
 624                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
 625                                "%s to %s\n", __func__, err,
 626                                pingroup_name(config[i].pingroup),
 627                                func_name(config[i].func));
 628         }
 629 }
 630
 631 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
 632         int len, enum tegra_tristate tristate)
 633 {
 634         int i;
 635         int err;
 636         enum tegra_pingroup pingroup;
 637
 638         for (i = 0; i < len; i++) {
 639                 pingroup = config[i].pingroup;
 640                 if (pingroups[pingroup].tri_reg >= 0) {
 641                         err = tegra_pinmux_set_tristate(pingroup, tristate);
 642                         if (err < 0)
 643                                 pr_err("pinmux: can't set pingroup %s tristate"
 644                                         " to %s: %d\n", pingroup_name(pingroup),
 645                                         tri_name(tristate), err);
 646                 }
 647         }
 648 }
 649
 650 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
 651         int len, enum tegra_pullupdown pupd)
 652 {
 653         int i;
 654         int err;
 655         enum tegra_pingroup pingroup;
 656
 657         for (i = 0; i < len; i++) {
 658                 pingroup = config[i].pingroup;
 659                 if (pingroups[pingroup].pupd_reg >= 0) {
 660                         err = tegra_pinmux_set_pullupdown(pingroup, pupd);
 661                         if (err < 0)
 662                                 pr_err("pinmux: can't set pingroup %s pullupdown"
 663                                         " to %s: %d\n", pingroup_name(pingroup),
 664                                         pupd_name(pupd), err);
 665                 }
 666         }
 667 }
 668
 669 static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
 670 {
 671         return 0;
 672 }
 673
 674 static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
 675         { .compatible = "nvidia,tegra20-pinmux", },
 676         { },
 677 };
 678
 679 static struct platform_driver tegra_pinmux_driver = {
 680         .driver         = {
 681                 .name   = "tegra-pinmux",
 682                 .owner  = THIS_MODULE,
 683                 .of_match_table = tegra_pinmux_of_match,
 684         },
 685         .probe          = tegra_pinmux_probe,
 686 };
 687
 688 static int __init tegra_pinmux_init(void)
 689 {
 690         return platform_driver_register(&tegra_pinmux_driver);
 691 }
 692 postcore_initcall(tegra_pinmux_init);
 693
 694 #ifdef  CONFIG_DEBUG_FS
 695
 696 #include <linux/debugfs.h>
 697 #include <linux/seq_file.h>
 698
 699 static void dbg_pad_field(struct seq_file *s, int len)
 700 {
 701         seq_putc(s, ',');
 702
 703         while (len-- > -1)
 704                 seq_putc(s, ' ');
 705 }
 706
 707 static int dbg_pinmux_show(struct seq_file *s, void *unused)
 708 {
 709         int i;
 710         int len;
 711
 712         for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
 713                 unsigned long tri;
 714                 unsigned long mux;
 715                 unsigned long pupd;
 716
 717                 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
 718                 len = strlen(pingroups[i].name);
 719                 dbg_pad_field(s, 5 - len);
 720
 721                 if (pingroups[i].mux_reg < 0) {
 722                         seq_printf(s, "TEGRA_MUX_NONE");
 723                         len = strlen("NONE");
 724                 } else {
 725                         mux = (pg_readl(pingroups[i].mux_reg) >>
 726                                pingroups[i].mux_bit) & 0x3;
 727                         if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
 728                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
 729                                 len = 5;
 730                         } else {
 731                                 seq_printf(s, "TEGRA_MUX_%s",
 732                                            tegra_mux_names[pingroups[i].funcs[mux]]);
 733                                 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
 734                         }
 735                 }
 736                 dbg_pad_field(s, 13-len);
 737
 738                 if (pingroups[i].pupd_reg < 0) {
 739                         seq_printf(s, "TEGRA_PUPD_NORMAL");
 740                         len = strlen("NORMAL");
 741                 } else {
 742                         pupd = (pg_readl(pingroups[i].pupd_reg) >>
 743                                 pingroups[i].pupd_bit) & 0x3;
 744                         seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
 745                         len = strlen(pupd_name(pupd));
 746                 }
 747                 dbg_pad_field(s, 9 - len);
 748
 749                 if (pingroups[i].tri_reg < 0) {
 750                         seq_printf(s, "TEGRA_TRI_NORMAL");
 751                 } else {
 752                         tri = (pg_readl(pingroups[i].tri_reg) >>
 753                                pingroups[i].tri_bit) & 0x1;
 754
 755                         seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
 756                 }
 757                 seq_printf(s, "},\n");
 758         }
 759         return 0;
 760 }
 761
 762 static int dbg_pinmux_open(struct inode *inode, struct file *file)
 763 {
 764         return single_open(file, dbg_pinmux_show, &inode->i_private);
 765 }
 766
 767 static const struct file_operations debug_fops = {
 768         .open           = dbg_pinmux_open,
 769         .read           = seq_read,
 770         .llseek         = seq_lseek,
 771         .release        = single_release,
 772 };
 773
 774 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
 775 {
 776         int i;
 777         int len;
 778
 779         for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
 780                 u32 reg;
 781
 782                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
 783                         drive_pingroups[i].name);
 784                 len = strlen(drive_pingroups[i].name);
 785                 dbg_pad_field(s, 7 - len);
 786
 787
 788                 reg = pg_readl(drive_pingroups[i].reg);
 789                 if (HSM_EN(reg)) {
 790                         seq_printf(s, "TEGRA_HSM_ENABLE");
 791                         len = 16;
 792                 } else {
 793                         seq_printf(s, "TEGRA_HSM_DISABLE");
 794                         len = 17;
 795                 }
 796                 dbg_pad_field(s, 17 - len);
 797
 798                 if (SCHMT_EN(reg)) {
 799                         seq_printf(s, "TEGRA_SCHMITT_ENABLE");
 800                         len = 21;
 801                 } else {
 802                         seq_printf(s, "TEGRA_SCHMITT_DISABLE");
 803                         len = 22;
 804                 }
 805                 dbg_pad_field(s, 22 - len);
 806
 807                 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
 808                 len = strlen(drive_name(LPMD(reg)));
 809                 dbg_pad_field(s, 5 - len);
 810
 811                 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
 812                 len = DRVDN(reg) < 10 ? 1 : 2;
 813                 dbg_pad_field(s, 2 - len);
 814
 815                 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
 816                 len = DRVUP(reg) < 10 ? 1 : 2;
 817                 dbg_pad_field(s, 2 - len);
 818
 819                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
 820                 len = strlen(slew_name(SLWR(reg)));
 821                 dbg_pad_field(s, 7 - len);
 822
 823                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
 824
 825                 seq_printf(s, "},\n");
 826         }
 827         return 0;
 828 }
 829
 830 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
 831 {
 832         return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
 833 }
 834
 835 static const struct file_operations debug_drive_fops = {
 836         .open           = dbg_drive_pinmux_open,
 837         .read           = seq_read,
 838         .llseek         = seq_lseek,
 839         .release        = single_release,
 840 };
 841
 842 static int __init tegra_pinmux_debuginit(void)
 843 {
 844         (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
 845                                         NULL, NULL, &debug_fops);
 846         (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
 847                                         NULL, NULL, &debug_drive_fops);
 848         return 0;
 849 }
 850 late_initcall(tegra_pinmux_debuginit);
 851 #endif