arch/arm/mach-tegra/tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * NVIDIA Tegra SoC device tree board support
   4  *
   5  * Copyright (C) 2011, 2013, NVIDIA Corporation
   6  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
   7  * Copyright (C) 2010 Google, Inc.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clk/tegra.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/kernel.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_fdt.h>
  20 #include <linux/of.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/pda_power.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/serial_8250.h>
  25 #include <linux/slab.h>
  26 #include <linux/sys_soc.h>
  27 #include <linux/usb/tegra_usb_phy.h>
  28
  29 #include <linux/firmware/trusted_foundations.h>
  30
  31 #include <soc/tegra/fuse.h>
  32 #include <soc/tegra/pmc.h>
  33
  34 #include <asm/firmware.h>
  35 #include <asm/hardware/cache-l2x0.h>
  36 #include <asm/mach/arch.h>
  37 #include <asm/mach/time.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/psci.h>
  40 #include <asm/setup.h>
  41
  42 #include "board.h"
  43 #include "common.h"
  44 #include "iomap.h"
  45 #include "pm.h"
  46 #include "reset.h"
  47 #include "sleep.h"
  48
  49 /*
  50  * Storage for debug-macro.S's state.
  51  *
  52  * This must be in .data not .bss so that it gets initialized each time the
  53  * kernel is loaded. The data is declared here rather than debug-macro.S so
  54  * that multiple inclusions of debug-macro.S point at the same data.
  55  */
  56 u32 tegra_uart_config[3] = {
  57         /* Debug UART initialization required */
  58         1,
  59         /* Debug UART physical address */
  60         0,
  61         /* Debug UART virtual address */
  62         0,
  63 };
  64
  65 static void __init tegra_init_early(void)
  66 {
  67         of_register_trusted_foundations();
  68         tegra_cpu_reset_handler_init();
  69         call_firmware_op(l2x0_init);
  70 }
  71
  72 static void __init tegra_dt_init_irq(void)
  73 {
  74         tegra_init_irq();
  75         irqchip_init();
  76 }
  77
  78 static void __init tegra_dt_init(void)
  79 {
  80         struct device *parent = tegra_soc_device_register();
  81
  82         of_platform_default_populate(NULL, NULL, parent);
  83 }
  84
  85 static void __init tegra_dt_init_late(void)
  86 {
  87         tegra_init_suspend();
  88
  89         if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
  90             of_machine_is_compatible("compal,paz00"))
  91                 tegra_paz00_wifikill_init();
  92
  93         if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
  94             of_machine_is_compatible("nvidia,tegra20"))
  95                 platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
  96
  97         if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
  98                 platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
  99
 100         if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
 101             of_machine_is_compatible("nvidia,tegra30"))
 102                 platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
 103 }
 104
 105 static const char * const tegra_dt_board_compat[] = {
 106         "nvidia,tegra124",
 107         "nvidia,tegra114",
 108         "nvidia,tegra30",
 109         "nvidia,tegra20",
 110         NULL
 111 };
 112
 113 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
 114         .l2c_aux_val    = 0x3c400000,
 115         .l2c_aux_mask   = 0xc20fc3ff,
 116         .smp            = smp_ops(tegra_smp_ops),
 117         .map_io         = tegra_map_common_io,
 118         .init_early     = tegra_init_early,
 119         .init_irq       = tegra_dt_init_irq,
 120         .init_machine   = tegra_dt_init,
 121         .init_late      = tegra_dt_init_late,
 122         .dt_compat      = tegra_dt_board_compat,
 123 MACHINE_END