2 * arch/arm/mach-tegra/tegra30_clocks.c
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
32 #include <asm/clkdev.h>
34 #include <mach/iomap.h>
38 #include "tegra_cpu_car.h"
40 #define USE_PLL_LOCK_BITS 0
42 #define RST_DEVICES_L 0x004
43 #define RST_DEVICES_H 0x008
44 #define RST_DEVICES_U 0x00C
45 #define RST_DEVICES_V 0x358
46 #define RST_DEVICES_W 0x35C
47 #define RST_DEVICES_SET_L 0x300
48 #define RST_DEVICES_CLR_L 0x304
49 #define RST_DEVICES_SET_V 0x430
50 #define RST_DEVICES_CLR_V 0x434
51 #define RST_DEVICES_NUM 5
53 #define CLK_OUT_ENB_L 0x010
54 #define CLK_OUT_ENB_H 0x014
55 #define CLK_OUT_ENB_U 0x018
56 #define CLK_OUT_ENB_V 0x360
57 #define CLK_OUT_ENB_W 0x364
58 #define CLK_OUT_ENB_SET_L 0x320
59 #define CLK_OUT_ENB_CLR_L 0x324
60 #define CLK_OUT_ENB_SET_V 0x440
61 #define CLK_OUT_ENB_CLR_V 0x444
62 #define CLK_OUT_ENB_NUM 5
64 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
65 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
67 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
68 #define PERIPH_CLK_TO_RST_REG(c) \
69 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
70 #define PERIPH_CLK_TO_RST_SET_REG(c) \
71 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
72 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
73 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
75 #define PERIPH_CLK_TO_ENB_REG(c) \
76 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
77 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
78 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
79 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
80 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
82 #define CLK_MASK_ARM 0x44
83 #define MISC_CLK_ENB 0x48
86 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
87 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
88 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
89 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
90 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
91 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
92 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
93 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
94 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
96 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
97 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
98 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
99 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
101 #define OSC_FREQ_DET 0x58
102 #define OSC_FREQ_DET_TRIG (1<<31)
104 #define OSC_FREQ_DET_STATUS 0x5C
105 #define OSC_FREQ_DET_BUSY (1<<31)
106 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
108 #define PERIPH_CLK_SOURCE_I2S1 0x100
109 #define PERIPH_CLK_SOURCE_EMC 0x19c
110 #define PERIPH_CLK_SOURCE_OSC 0x1fc
111 #define PERIPH_CLK_SOURCE_NUM1 \
112 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
114 #define PERIPH_CLK_SOURCE_G3D2 0x3b0
115 #define PERIPH_CLK_SOURCE_SE 0x42c
116 #define PERIPH_CLK_SOURCE_NUM2 \
117 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
119 #define AUDIO_DLY_CLK 0x49c
120 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
121 #define PERIPH_CLK_SOURCE_NUM3 \
122 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
124 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
125 PERIPH_CLK_SOURCE_NUM2 + \
126 PERIPH_CLK_SOURCE_NUM3)
128 #define CPU_SOFTRST_CTRL 0x380
130 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
131 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
132 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
133 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
134 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
135 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
136 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
137 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
138 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
139 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
141 #define AUDIO_SYNC_SOURCE_MASK 0x0F
142 #define AUDIO_SYNC_DISABLE_BIT 0x10
143 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
146 #define PLL_BASE_BYPASS (1<<31)
147 #define PLL_BASE_ENABLE (1<<30)
148 #define PLL_BASE_REF_ENABLE (1<<29)
149 #define PLL_BASE_OVERRIDE (1<<28)
150 #define PLL_BASE_LOCK (1<<27)
151 #define PLL_BASE_DIVP_MASK (0x7<<20)
152 #define PLL_BASE_DIVP_SHIFT 20
153 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
154 #define PLL_BASE_DIVN_SHIFT 8
155 #define PLL_BASE_DIVM_MASK (0x1F)
156 #define PLL_BASE_DIVM_SHIFT 0
158 #define PLL_OUT_RATIO_MASK (0xFF<<8)
159 #define PLL_OUT_RATIO_SHIFT 8
160 #define PLL_OUT_OVERRIDE (1<<2)
161 #define PLL_OUT_CLKEN (1<<1)
162 #define PLL_OUT_RESET_DISABLE (1<<0)
164 #define PLL_MISC(c) \
165 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
166 #define PLL_MISC_LOCK_ENABLE(c) \
167 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
169 #define PLL_MISC_DCCON_SHIFT 20
170 #define PLL_MISC_CPCON_SHIFT 8
171 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
172 #define PLL_MISC_LFCON_SHIFT 4
173 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
174 #define PLL_MISC_VCOCON_SHIFT 0
175 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
176 #define PLLD_MISC_CLKENABLE (1<<30)
178 #define PLLU_BASE_POST_DIV (1<<20)
180 #define PLLD_BASE_DSIB_MUX_SHIFT 25
181 #define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)
182 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
183 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
184 #define PLLD_MISC_DIV_RST (1<<23)
185 #define PLLD_MISC_DCCON_SHIFT 12
187 #define PLLDU_LFCON_SET_DIVN 600
189 /* FIXME: OUT_OF_TABLE_CPCON per pll */
190 #define OUT_OF_TABLE_CPCON 0x8
192 #define SUPER_CLK_MUX 0x00
193 #define SUPER_STATE_SHIFT 28
194 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
195 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
196 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
197 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
198 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
199 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
200 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
201 #define SUPER_SOURCE_MASK 0xF
202 #define SUPER_FIQ_SOURCE_SHIFT 12
203 #define SUPER_IRQ_SOURCE_SHIFT 8
204 #define SUPER_RUN_SOURCE_SHIFT 4
205 #define SUPER_IDLE_SOURCE_SHIFT 0
207 #define SUPER_CLK_DIVIDER 0x04
208 #define SUPER_CLOCK_DIV_U71_SHIFT 16
209 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
210 /* guarantees safe cpu backup */
211 #define SUPER_CLOCK_DIV_U71_MIN 0x2
213 #define BUS_CLK_DISABLE (1<<3)
214 #define BUS_CLK_DIV_MASK 0x3
217 #define PMC_CTRL_BLINK_ENB (1 << 7)
219 #define PMC_DPD_PADS_ORIDE 0x1c
220 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
222 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
223 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
224 #define PMC_BLINK_TIMER_ENB (1 << 15)
225 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
226 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
228 #define PMC_PLLP_WB0_OVERRIDE 0xf8
229 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
231 #define UTMIP_PLL_CFG2 0x488
232 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
233 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
234 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
235 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
236 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
238 #define UTMIP_PLL_CFG1 0x484
239 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
240 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
241 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
242 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
243 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
245 #define PLLE_BASE_CML_ENABLE (1<<31)
246 #define PLLE_BASE_ENABLE (1<<30)
247 #define PLLE_BASE_DIVCML_SHIFT 24
248 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
249 #define PLLE_BASE_DIVP_SHIFT 16
250 #define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
251 #define PLLE_BASE_DIVN_SHIFT 8
252 #define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
253 #define PLLE_BASE_DIVM_SHIFT 0
254 #define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
255 #define PLLE_BASE_DIV_MASK \
256 (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
257 PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
258 #define PLLE_BASE_DIV(m, n, p, cml) \
259 (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
260 ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
262 #define PLLE_MISC_SETUP_BASE_SHIFT 16
263 #define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
264 #define PLLE_MISC_READY (1<<15)
265 #define PLLE_MISC_LOCK (1<<11)
266 #define PLLE_MISC_LOCK_ENABLE (1<<9)
267 #define PLLE_MISC_SETUP_EX_SHIFT 2
268 #define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
269 #define PLLE_MISC_SETUP_MASK \
270 (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
271 #define PLLE_MISC_SETUP_VALUE \
272 ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
274 #define PLLE_SS_CTRL 0x68
275 #define PLLE_SS_INCINTRV_SHIFT 24
276 #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
277 #define PLLE_SS_INC_SHIFT 16
278 #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
279 #define PLLE_SS_MAX_SHIFT 0
280 #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
281 #define PLLE_SS_COEFFICIENTS_MASK \
282 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
283 #define PLLE_SS_COEFFICIENTS_12MHZ \
284 ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
285 (0x24<<PLLE_SS_MAX_SHIFT))
286 #define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
288 #define PLLE_AUX 0x48c
289 #define PLLE_AUX_PLLP_SEL (1<<2)
290 #define PLLE_AUX_CML_SATA_ENABLE (1<<1)
291 #define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
293 #define PMC_SATA_PWRGT 0x1ac
294 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
295 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
297 #define ROUND_DIVIDER_UP 0
298 #define ROUND_DIVIDER_DOWN 1
300 /* FIXME: recommended safety delay after lock is detected */
301 #define PLL_POST_LOCK_DELAY 100
303 /* Tegra CPU clock and reset control regs */
304 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
305 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
306 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
307 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
308 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
310 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
311 #define CPU_RESET(cpu) (0x1111ul << (cpu))
314 * Structure defining the fields for USB UTMI clocks Parameters.
316 struct utmi_clk_param
{
317 /* Oscillator Frequency in KHz */
319 /* UTMIP PLL Enable Delay Count */
320 u8 enable_delay_count
;
321 /* UTMIP PLL Stable count */
323 /* UTMIP PLL Active delay count */
324 u8 active_delay_count
;
325 /* UTMIP PLL Xtal frequency count */
329 static const struct utmi_clk_param utmi_parameters
[] = {
331 .osc_frequency
= 13000000,
332 .enable_delay_count
= 0x02,
333 .stable_count
= 0x33,
334 .active_delay_count
= 0x05,
335 .xtal_freq_count
= 0x7F
338 .osc_frequency
= 19200000,
339 .enable_delay_count
= 0x03,
340 .stable_count
= 0x4B,
341 .active_delay_count
= 0x06,
342 .xtal_freq_count
= 0xBB},
344 .osc_frequency
= 12000000,
345 .enable_delay_count
= 0x02,
346 .stable_count
= 0x2F,
347 .active_delay_count
= 0x04,
348 .xtal_freq_count
= 0x76
351 .osc_frequency
= 26000000,
352 .enable_delay_count
= 0x04,
353 .stable_count
= 0x66,
354 .active_delay_count
= 0x09,
355 .xtal_freq_count
= 0xFE
358 .osc_frequency
= 16800000,
359 .enable_delay_count
= 0x03,
360 .stable_count
= 0x41,
361 .active_delay_count
= 0x0A,
362 .xtal_freq_count
= 0xA4
366 static void __iomem
*reg_clk_base
= IO_ADDRESS(TEGRA_CLK_RESET_BASE
);
367 static void __iomem
*reg_pmc_base
= IO_ADDRESS(TEGRA_PMC_BASE
);
368 static void __iomem
*misc_gp_hidrev_base
= IO_ADDRESS(TEGRA_APB_MISC_BASE
);
370 #define MISC_GP_HIDREV 0x804
373 * Some peripheral clocks share an enable bit, so refcount the enable bits
374 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
376 static int tegra_periph_clk_enable_refcount
[CLK_OUT_ENB_NUM
* 32];
378 #define clk_writel(value, reg) \
379 __raw_writel(value, reg_clk_base + (reg))
380 #define clk_readl(reg) \
381 __raw_readl(reg_clk_base + (reg))
382 #define pmc_writel(value, reg) \
383 __raw_writel(value, reg_pmc_base + (reg))
384 #define pmc_readl(reg) \
385 __raw_readl(reg_pmc_base + (reg))
386 #define chipid_readl() \
387 __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
389 #define clk_writel_delay(value, reg) \
391 __raw_writel((value), reg_clk_base + (reg)); \
395 static inline int clk_set_div(struct clk_tegra
*c
, u32 n
)
397 struct clk
*clk
= c
->hw
.clk
;
399 return clk_set_rate(clk
,
400 (__clk_get_rate(__clk_get_parent(clk
)) + n
- 1) / n
);
403 static inline u32
periph_clk_to_reg(
404 struct clk_tegra
*c
, u32 reg_L
, u32 reg_V
, int offs
)
406 u32 reg
= c
->u
.periph
.clk_num
/ 32;
407 BUG_ON(reg
>= RST_DEVICES_NUM
);
409 reg
= reg_L
+ (reg
* offs
);
411 reg
= reg_V
+ ((reg
- 3) * offs
);
415 static unsigned long clk_measure_input_freq(void)
417 u32 clock_autodetect
;
418 clk_writel(OSC_FREQ_DET_TRIG
| 1, OSC_FREQ_DET
);
419 do {} while (clk_readl(OSC_FREQ_DET_STATUS
) & OSC_FREQ_DET_BUSY
);
420 clock_autodetect
= clk_readl(OSC_FREQ_DET_STATUS
);
421 if (clock_autodetect
>= 732 - 3 && clock_autodetect
<= 732 + 3) {
423 } else if (clock_autodetect
>= 794 - 3 && clock_autodetect
<= 794 + 3) {
425 } else if (clock_autodetect
>= 1172 - 3 && clock_autodetect
<= 1172 + 3) {
427 } else if (clock_autodetect
>= 1587 - 3 && clock_autodetect
<= 1587 + 3) {
429 } else if (clock_autodetect
>= 1025 - 3 && clock_autodetect
<= 1025 + 3) {
431 } else if (clock_autodetect
>= 2344 - 3 && clock_autodetect
<= 2344 + 3) {
433 } else if (clock_autodetect
>= 2928 - 3 && clock_autodetect
<= 2928 + 3) {
436 pr_err("%s: Unexpected clock autodetect value %d", __func__
,
443 static int clk_div71_get_divider(unsigned long parent_rate
, unsigned long rate
,
444 u32 flags
, u32 round_mode
)
446 s64 divider_u71
= parent_rate
;
450 if (!(flags
& DIV_U71_INT
))
452 if (round_mode
== ROUND_DIVIDER_UP
)
453 divider_u71
+= rate
- 1;
454 do_div(divider_u71
, rate
);
455 if (flags
& DIV_U71_INT
)
458 if (divider_u71
- 2 < 0)
461 if (divider_u71
- 2 > 255)
464 return divider_u71
- 2;
467 static int clk_div16_get_divider(unsigned long parent_rate
, unsigned long rate
)
471 divider_u16
= parent_rate
;
474 divider_u16
+= rate
- 1;
475 do_div(divider_u16
, rate
);
477 if (divider_u16
- 1 < 0)
480 if (divider_u16
- 1 > 0xFFFF)
483 return divider_u16
- 1;
486 static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw
*hw
,
487 unsigned long parent_rate
)
489 return to_clk_tegra(hw
)->fixed_rate
;
492 struct clk_ops tegra30_clk_32k_ops
= {
493 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
496 /* clk_m functions */
497 static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw
*hw
,
498 unsigned long parent_rate
)
500 if (!to_clk_tegra(hw
)->fixed_rate
)
501 to_clk_tegra(hw
)->fixed_rate
= clk_measure_input_freq();
502 return to_clk_tegra(hw
)->fixed_rate
;
505 static void tegra30_clk_m_init(struct clk_hw
*hw
)
507 u32 osc_ctrl
= clk_readl(OSC_CTRL
);
508 u32 auto_clock_control
= osc_ctrl
& ~OSC_CTRL_OSC_FREQ_MASK
;
509 u32 pll_ref_div
= osc_ctrl
& OSC_CTRL_PLL_REF_DIV_MASK
;
511 switch (to_clk_tegra(hw
)->fixed_rate
) {
513 auto_clock_control
|= OSC_CTRL_OSC_FREQ_12MHZ
;
514 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
517 auto_clock_control
|= OSC_CTRL_OSC_FREQ_13MHZ
;
518 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
521 auto_clock_control
|= OSC_CTRL_OSC_FREQ_19_2MHZ
;
522 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
525 auto_clock_control
|= OSC_CTRL_OSC_FREQ_26MHZ
;
526 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
529 auto_clock_control
|= OSC_CTRL_OSC_FREQ_16_8MHZ
;
530 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_1
);
533 auto_clock_control
|= OSC_CTRL_OSC_FREQ_38_4MHZ
;
534 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_2
);
537 auto_clock_control
|= OSC_CTRL_OSC_FREQ_48MHZ
;
538 BUG_ON(pll_ref_div
!= OSC_CTRL_PLL_REF_DIV_4
);
541 pr_err("%s: Unexpected clock rate %ld", __func__
,
542 to_clk_tegra(hw
)->fixed_rate
);
545 clk_writel(auto_clock_control
, OSC_CTRL
);
548 struct clk_ops tegra30_clk_m_ops
= {
549 .init
= tegra30_clk_m_init
,
550 .recalc_rate
= tegra30_clk_m_recalc_rate
,
553 static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw
*hw
,
554 unsigned long parent_rate
)
556 struct clk_tegra
*c
= to_clk_tegra(hw
);
557 u64 rate
= parent_rate
;
559 if (c
->mul
!= 0 && c
->div
!= 0) {
561 rate
+= c
->div
- 1; /* round up */
562 do_div(rate
, c
->div
);
568 struct clk_ops tegra_clk_m_div_ops
= {
569 .recalc_rate
= tegra30_clk_m_div_recalc_rate
,
572 /* PLL reference divider functions */
573 static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw
*hw
,
574 unsigned long parent_rate
)
576 struct clk_tegra
*c
= to_clk_tegra(hw
);
577 unsigned long rate
= parent_rate
;
578 u32 pll_ref_div
= clk_readl(OSC_CTRL
) & OSC_CTRL_PLL_REF_DIV_MASK
;
580 switch (pll_ref_div
) {
581 case OSC_CTRL_PLL_REF_DIV_1
:
584 case OSC_CTRL_PLL_REF_DIV_2
:
587 case OSC_CTRL_PLL_REF_DIV_4
:
591 pr_err("%s: Invalid pll ref divider %d", __func__
, pll_ref_div
);
596 if (c
->mul
!= 0 && c
->div
!= 0) {
598 rate
+= c
->div
- 1; /* round up */
599 do_div(rate
, c
->div
);
605 struct clk_ops tegra_pll_ref_ops
= {
606 .recalc_rate
= tegra30_pll_ref_recalc_rate
,
609 /* super clock functions */
610 /* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
611 * clock skipping super divider. We will ignore the clock skipping divider,
612 * since we can't lower the voltage when using the clock skip, but we can if
613 * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
614 * only when its parent is a fixed rate PLL, since we can't change PLL rate
617 static void tegra30_super_clk_init(struct clk_hw
*hw
)
619 struct clk_tegra
*c
= to_clk_tegra(hw
);
620 struct clk_tegra
*p
=
621 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw
->clk
)));
624 if (c
->flags
& DIV_U71
) {
625 /* Init safe 7.1 divider value (does not affect PLLX path) */
626 clk_writel(SUPER_CLOCK_DIV_U71_MIN
<< SUPER_CLOCK_DIV_U71_SHIFT
,
627 c
->reg
+ SUPER_CLK_DIVIDER
);
630 if (!(p
->flags
& PLLX
))
631 c
->div
+= SUPER_CLOCK_DIV_U71_MIN
;
633 clk_writel(0, c
->reg
+ SUPER_CLK_DIVIDER
);
636 static u8
tegra30_super_clk_get_parent(struct clk_hw
*hw
)
638 struct clk_tegra
*c
= to_clk_tegra(hw
);
643 val
= clk_readl(c
->reg
+ SUPER_CLK_MUX
);
644 BUG_ON(((val
& SUPER_STATE_MASK
) != SUPER_STATE_RUN
) &&
645 ((val
& SUPER_STATE_MASK
) != SUPER_STATE_IDLE
));
646 shift
= ((val
& SUPER_STATE_MASK
) == SUPER_STATE_IDLE
) ?
647 SUPER_IDLE_SOURCE_SHIFT
: SUPER_RUN_SOURCE_SHIFT
;
648 source
= (val
>> shift
) & SUPER_SOURCE_MASK
;
649 if (c
->flags
& DIV_2
)
650 source
|= val
& SUPER_LP_DIV2_BYPASS
;
655 static int tegra30_super_clk_set_parent(struct clk_hw
*hw
, u8 index
)
657 struct clk_tegra
*c
= to_clk_tegra(hw
);
658 struct clk_tegra
*p
=
659 to_clk_tegra(__clk_get_hw(clk_get_parent(hw
->clk
)));
663 val
= clk_readl(c
->reg
+ SUPER_CLK_MUX
);
664 BUG_ON(((val
& SUPER_STATE_MASK
) != SUPER_STATE_RUN
) &&
665 ((val
& SUPER_STATE_MASK
) != SUPER_STATE_IDLE
));
666 shift
= ((val
& SUPER_STATE_MASK
) == SUPER_STATE_IDLE
) ?
667 SUPER_IDLE_SOURCE_SHIFT
: SUPER_RUN_SOURCE_SHIFT
;
669 /* For LP mode super-clock switch between PLLX direct
670 and divided-by-2 outputs is allowed only when other
671 than PLLX clock source is current parent */
672 if ((c
->flags
& DIV_2
) && (p
->flags
& PLLX
) &&
673 ((index
^ val
) & SUPER_LP_DIV2_BYPASS
)) {
676 val
^= SUPER_LP_DIV2_BYPASS
;
677 clk_writel_delay(val
, c
->reg
);
679 val
&= ~(SUPER_SOURCE_MASK
<< shift
);
680 val
|= (index
& SUPER_SOURCE_MASK
) << shift
;
682 /* 7.1 divider for CPU super-clock does not affect
684 if (c
->flags
& DIV_U71
) {
686 if (!(p
->flags
& PLLX
)) {
687 div
= clk_readl(c
->reg
+
689 div
&= SUPER_CLOCK_DIV_U71_MASK
;
690 div
>>= SUPER_CLOCK_DIV_U71_SHIFT
;
695 clk_writel_delay(val
, c
->reg
);
701 * Do not use super clocks "skippers", since dividing using a clock skipper
702 * does not allow the voltage to be scaled down. Instead adjust the rate of
703 * the parent clock. This requires that the parent of a super clock have no
704 * other children, otherwise the rate will change underneath the other
705 * children. Special case: if fixed rate PLL is CPU super clock parent the
706 * rate of this PLL can't be changed, and it has many other children. In
707 * this case use 7.1 fractional divider to adjust the super clock rate.
709 static int tegra30_super_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
710 unsigned long parent_rate
)
712 struct clk_tegra
*c
= to_clk_tegra(hw
);
713 struct clk
*parent
= __clk_get_parent(hw
->clk
);
714 struct clk_tegra
*cparent
= to_clk_tegra(__clk_get_hw(parent
));
716 if ((c
->flags
& DIV_U71
) && (cparent
->flags
& PLL_FIXED
)) {
717 int div
= clk_div71_get_divider(parent_rate
,
718 rate
, c
->flags
, ROUND_DIVIDER_DOWN
);
719 div
= max(div
, SUPER_CLOCK_DIV_U71_MIN
);
721 clk_writel(div
<< SUPER_CLOCK_DIV_U71_SHIFT
,
722 c
->reg
+ SUPER_CLK_DIVIDER
);
730 static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw
*hw
,
731 unsigned long parent_rate
)
733 struct clk_tegra
*c
= to_clk_tegra(hw
);
734 u64 rate
= parent_rate
;
736 if (c
->mul
!= 0 && c
->div
!= 0) {
738 rate
+= c
->div
- 1; /* round up */
739 do_div(rate
, c
->div
);
745 static long tegra30_super_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
746 unsigned long *prate
)
748 struct clk_tegra
*c
= to_clk_tegra(hw
);
749 struct clk
*parent
= __clk_get_parent(hw
->clk
);
750 struct clk_tegra
*cparent
= to_clk_tegra(__clk_get_hw(parent
));
754 if ((c
->flags
& DIV_U71
) && (cparent
->flags
& PLL_FIXED
)) {
755 div
= clk_div71_get_divider(*prate
,
756 rate
, c
->flags
, ROUND_DIVIDER_DOWN
);
757 div
= max(div
, SUPER_CLOCK_DIV_U71_MIN
) + 2;
759 rate
+= div
- 1; /* round up */
760 do_div(rate
, c
->div
);
767 struct clk_ops tegra30_super_ops
= {
768 .init
= tegra30_super_clk_init
,
769 .set_parent
= tegra30_super_clk_set_parent
,
770 .get_parent
= tegra30_super_clk_get_parent
,
771 .recalc_rate
= tegra30_super_clk_recalc_rate
,
772 .round_rate
= tegra30_super_clk_round_rate
,
773 .set_rate
= tegra30_super_clk_set_rate
,
776 static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw
*hw
,
777 unsigned long parent_rate
)
779 struct clk_tegra
*c
= to_clk_tegra(hw
);
780 u64 rate
= parent_rate
;
782 if (c
->mul
!= 0 && c
->div
!= 0) {
784 rate
+= c
->div
- 1; /* round up */
785 do_div(rate
, c
->div
);
791 struct clk_ops tegra30_twd_ops
= {
792 .recalc_rate
= tegra30_twd_clk_recalc_rate
,
795 /* Blink output functions */
796 static int tegra30_blink_clk_is_enabled(struct clk_hw
*hw
)
798 struct clk_tegra
*c
= to_clk_tegra(hw
);
801 val
= pmc_readl(PMC_CTRL
);
802 c
->state
= (val
& PMC_CTRL_BLINK_ENB
) ? ON
: OFF
;
806 static int tegra30_blink_clk_enable(struct clk_hw
*hw
)
810 val
= pmc_readl(PMC_DPD_PADS_ORIDE
);
811 pmc_writel(val
| PMC_DPD_PADS_ORIDE_BLINK_ENB
, PMC_DPD_PADS_ORIDE
);
813 val
= pmc_readl(PMC_CTRL
);
814 pmc_writel(val
| PMC_CTRL_BLINK_ENB
, PMC_CTRL
);
819 static void tegra30_blink_clk_disable(struct clk_hw
*hw
)
823 val
= pmc_readl(PMC_CTRL
);
824 pmc_writel(val
& ~PMC_CTRL_BLINK_ENB
, PMC_CTRL
);
826 val
= pmc_readl(PMC_DPD_PADS_ORIDE
);
827 pmc_writel(val
& ~PMC_DPD_PADS_ORIDE_BLINK_ENB
, PMC_DPD_PADS_ORIDE
);
830 static int tegra30_blink_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
831 unsigned long parent_rate
)
833 struct clk_tegra
*c
= to_clk_tegra(hw
);
835 if (rate
>= parent_rate
) {
837 pmc_writel(0, c
->reg
);
842 on_off
= DIV_ROUND_UP(parent_rate
/ 8, rate
);
845 val
= (on_off
& PMC_BLINK_TIMER_DATA_ON_MASK
) <<
846 PMC_BLINK_TIMER_DATA_ON_SHIFT
;
847 on_off
&= PMC_BLINK_TIMER_DATA_OFF_MASK
;
848 on_off
<<= PMC_BLINK_TIMER_DATA_OFF_SHIFT
;
850 val
|= PMC_BLINK_TIMER_ENB
;
851 pmc_writel(val
, c
->reg
);
857 static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw
*hw
,
858 unsigned long parent_rate
)
860 struct clk_tegra
*c
= to_clk_tegra(hw
);
861 u64 rate
= parent_rate
;
868 val
= pmc_readl(c
->reg
);
870 if (val
& PMC_BLINK_TIMER_ENB
) {
871 on_off
= (val
>> PMC_BLINK_TIMER_DATA_ON_SHIFT
) &
872 PMC_BLINK_TIMER_DATA_ON_MASK
;
873 val
>>= PMC_BLINK_TIMER_DATA_OFF_SHIFT
;
874 val
&= PMC_BLINK_TIMER_DATA_OFF_MASK
;
876 /* each tick in the blink timer is 4 32KHz clocks */
882 if (mul
!= 0 && div
!= 0) {
884 rate
+= div
- 1; /* round up */
890 static long tegra30_blink_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
891 unsigned long *prate
)
895 long round_rate
= *prate
;
899 if (rate
>= *prate
) {
902 div
= DIV_ROUND_UP(*prate
/ 8, rate
);
907 round_rate
+= div
- 1;
908 do_div(round_rate
, div
);
913 struct clk_ops tegra30_blink_clk_ops
= {
914 .is_enabled
= tegra30_blink_clk_is_enabled
,
915 .enable
= tegra30_blink_clk_enable
,
916 .disable
= tegra30_blink_clk_disable
,
917 .recalc_rate
= tegra30_blink_clk_recalc_rate
,
918 .round_rate
= tegra30_blink_clk_round_rate
,
919 .set_rate
= tegra30_blink_clk_set_rate
,
922 static void tegra30_utmi_param_configure(struct clk_hw
*hw
)
924 unsigned long main_rate
=
925 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw
->clk
)));
929 for (i
= 0; i
< ARRAY_SIZE(utmi_parameters
); i
++) {
930 if (main_rate
== utmi_parameters
[i
].osc_frequency
)
934 if (i
>= ARRAY_SIZE(utmi_parameters
)) {
935 pr_err("%s: Unexpected main rate %lu\n", __func__
, main_rate
);
939 reg
= clk_readl(UTMIP_PLL_CFG2
);
941 /* Program UTMIP PLL stable and active counts */
942 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
943 reg
&= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
944 reg
|= UTMIP_PLL_CFG2_STABLE_COUNT(
945 utmi_parameters
[i
].stable_count
);
947 reg
&= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
949 reg
|= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
950 utmi_parameters
[i
].active_delay_count
);
952 /* Remove power downs from UTMIP PLL control bits */
953 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN
;
954 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN
;
955 reg
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN
;
957 clk_writel(reg
, UTMIP_PLL_CFG2
);
959 /* Program UTMIP PLL delay and oscillator frequency counts */
960 reg
= clk_readl(UTMIP_PLL_CFG1
);
961 reg
&= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
963 reg
|= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
964 utmi_parameters
[i
].enable_delay_count
);
966 reg
&= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
967 reg
|= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
968 utmi_parameters
[i
].xtal_freq_count
);
970 /* Remove power downs from UTMIP PLL control bits */
971 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN
;
972 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN
;
973 reg
&= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN
;
975 clk_writel(reg
, UTMIP_PLL_CFG1
);
979 static int tegra30_pll_clk_wait_for_lock(struct clk_tegra
*c
, u32 lock_reg
,
984 #if USE_PLL_LOCK_BITS
986 for (i
= 0; i
< c
->u
.pll
.lock_delay
; i
++) {
987 if (clk_readl(lock_reg
) & lock_bit
) {
988 udelay(PLL_POST_LOCK_DELAY
);
991 udelay(2); /* timeout = 2 * lock time */
993 pr_err("Timed out waiting for lock bit on pll %s",
994 __clk_get_name(hw
->clk
));
997 udelay(c
->u
.pll
.lock_delay
);
1002 static int tegra30_pll_clk_is_enabled(struct clk_hw
*hw
)
1004 struct clk_tegra
*c
= to_clk_tegra(hw
);
1005 u32 val
= clk_readl(c
->reg
+ PLL_BASE
);
1007 c
->state
= (val
& PLL_BASE_ENABLE
) ? ON
: OFF
;
1011 static void tegra30_pll_clk_init(struct clk_hw
*hw
)
1013 struct clk_tegra
*c
= to_clk_tegra(hw
);
1015 if (c
->flags
& PLLU
)
1016 tegra30_utmi_param_configure(hw
);
1019 static int tegra30_pll_clk_enable(struct clk_hw
*hw
)
1021 struct clk_tegra
*c
= to_clk_tegra(hw
);
1023 pr_debug("%s on clock %s\n", __func__
, __clk_get_name(hw
->clk
));
1025 #if USE_PLL_LOCK_BITS
1026 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1027 val
|= PLL_MISC_LOCK_ENABLE(c
);
1028 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
1030 val
= clk_readl(c
->reg
+ PLL_BASE
);
1031 val
&= ~PLL_BASE_BYPASS
;
1032 val
|= PLL_BASE_ENABLE
;
1033 clk_writel(val
, c
->reg
+ PLL_BASE
);
1035 if (c
->flags
& PLLM
) {
1036 val
= pmc_readl(PMC_PLLP_WB0_OVERRIDE
);
1037 val
|= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE
;
1038 pmc_writel(val
, PMC_PLLP_WB0_OVERRIDE
);
1041 tegra30_pll_clk_wait_for_lock(c
, c
->reg
+ PLL_BASE
, PLL_BASE_LOCK
);
1046 static void tegra30_pll_clk_disable(struct clk_hw
*hw
)
1048 struct clk_tegra
*c
= to_clk_tegra(hw
);
1050 pr_debug("%s on clock %s\n", __func__
, __clk_get_name(hw
->clk
));
1052 val
= clk_readl(c
->reg
);
1053 val
&= ~(PLL_BASE_BYPASS
| PLL_BASE_ENABLE
);
1054 clk_writel(val
, c
->reg
);
1056 if (c
->flags
& PLLM
) {
1057 val
= pmc_readl(PMC_PLLP_WB0_OVERRIDE
);
1058 val
&= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE
;
1059 pmc_writel(val
, PMC_PLLP_WB0_OVERRIDE
);
1063 static int tegra30_pll_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1064 unsigned long parent_rate
)
1066 struct clk_tegra
*c
= to_clk_tegra(hw
);
1067 u32 val
, p_div
, old_base
;
1068 unsigned long input_rate
;
1069 const struct clk_pll_freq_table
*sel
;
1070 struct clk_pll_freq_table cfg
;
1072 if (c
->flags
& PLL_FIXED
) {
1074 if (rate
!= c
->u
.pll
.fixed_rate
) {
1075 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
1076 __func__
, __clk_get_name(hw
->clk
),
1077 c
->u
.pll
.fixed_rate
, rate
);
1083 if (c
->flags
& PLLM
) {
1084 if (rate
!= __clk_get_rate(hw
->clk
)) {
1085 pr_err("%s: Can not change memory %s rate in flight\n",
1086 __func__
, __clk_get_name(hw
->clk
));
1092 input_rate
= parent_rate
;
1094 /* Check if the target rate is tabulated */
1095 for (sel
= c
->u
.pll
.freq_table
; sel
->input_rate
!= 0; sel
++) {
1096 if (sel
->input_rate
== input_rate
&& sel
->output_rate
== rate
) {
1097 if (c
->flags
& PLLU
) {
1098 BUG_ON(sel
->p
< 1 || sel
->p
> 2);
1100 p_div
= PLLU_BASE_POST_DIV
;
1103 for (val
= sel
->p
; val
> 1; val
>>= 1)
1105 p_div
<<= PLL_BASE_DIVP_SHIFT
;
1111 /* Configure out-of-table rate */
1112 if (sel
->input_rate
== 0) {
1113 unsigned long cfreq
;
1114 BUG_ON(c
->flags
& PLLU
);
1117 switch (input_rate
) {
1120 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2000000;
1123 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2600000;
1127 cfreq
= (rate
<= 1200000 * 1000) ? 1200000 : 2400000;
1130 pr_err("%s: Unexpected reference rate %lu\n",
1131 __func__
, input_rate
);
1135 /* Raise VCO to guarantee 0.5% accuracy */
1136 for (cfg
.output_rate
= rate
; cfg
.output_rate
< 200 * cfreq
;
1137 cfg
.output_rate
<<= 1)
1140 cfg
.p
= 0x1 << p_div
;
1141 cfg
.m
= input_rate
/ cfreq
;
1142 cfg
.n
= cfg
.output_rate
/ cfreq
;
1143 cfg
.cpcon
= OUT_OF_TABLE_CPCON
;
1145 if ((cfg
.m
> (PLL_BASE_DIVM_MASK
>> PLL_BASE_DIVM_SHIFT
)) ||
1146 (cfg
.n
> (PLL_BASE_DIVN_MASK
>> PLL_BASE_DIVN_SHIFT
)) ||
1147 (p_div
> (PLL_BASE_DIVP_MASK
>> PLL_BASE_DIVP_SHIFT
)) ||
1148 (cfg
.output_rate
> c
->u
.pll
.vco_max
)) {
1149 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1150 __func__
, __clk_get_name(hw
->clk
), rate
);
1153 p_div
<<= PLL_BASE_DIVP_SHIFT
;
1157 c
->div
= sel
->m
* sel
->p
;
1159 old_base
= val
= clk_readl(c
->reg
+ PLL_BASE
);
1160 val
&= ~(PLL_BASE_DIVM_MASK
| PLL_BASE_DIVN_MASK
|
1161 ((c
->flags
& PLLU
) ? PLLU_BASE_POST_DIV
: PLL_BASE_DIVP_MASK
));
1162 val
|= (sel
->m
<< PLL_BASE_DIVM_SHIFT
) |
1163 (sel
->n
<< PLL_BASE_DIVN_SHIFT
) | p_div
;
1164 if (val
== old_base
)
1167 if (c
->state
== ON
) {
1168 tegra30_pll_clk_disable(hw
);
1169 val
&= ~(PLL_BASE_BYPASS
| PLL_BASE_ENABLE
);
1171 clk_writel(val
, c
->reg
+ PLL_BASE
);
1173 if (c
->flags
& PLL_HAS_CPCON
) {
1174 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1175 val
&= ~PLL_MISC_CPCON_MASK
;
1176 val
|= sel
->cpcon
<< PLL_MISC_CPCON_SHIFT
;
1177 if (c
->flags
& (PLLU
| PLLD
)) {
1178 val
&= ~PLL_MISC_LFCON_MASK
;
1179 if (sel
->n
>= PLLDU_LFCON_SET_DIVN
)
1180 val
|= 0x1 << PLL_MISC_LFCON_SHIFT
;
1181 } else if (c
->flags
& (PLLX
| PLLM
)) {
1182 val
&= ~(0x1 << PLL_MISC_DCCON_SHIFT
);
1183 if (rate
>= (c
->u
.pll
.vco_max
>> 1))
1184 val
|= 0x1 << PLL_MISC_DCCON_SHIFT
;
1186 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
1190 tegra30_pll_clk_enable(hw
);
1192 c
->u
.pll
.fixed_rate
= rate
;
1197 static long tegra30_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1198 unsigned long *prate
)
1200 struct clk_tegra
*c
= to_clk_tegra(hw
);
1201 unsigned long input_rate
= *prate
;
1202 unsigned long output_rate
= *prate
;
1203 const struct clk_pll_freq_table
*sel
;
1204 struct clk_pll_freq_table cfg
;
1210 if (c
->flags
& PLL_FIXED
)
1211 return c
->u
.pll
.fixed_rate
;
1213 if (c
->flags
& PLLM
)
1214 return __clk_get_rate(hw
->clk
);
1217 /* Check if the target rate is tabulated */
1218 for (sel
= c
->u
.pll
.freq_table
; sel
->input_rate
!= 0; sel
++) {
1219 if (sel
->input_rate
== input_rate
&& sel
->output_rate
== rate
) {
1220 if (c
->flags
& PLLU
) {
1221 BUG_ON(sel
->p
< 1 || sel
->p
> 2);
1223 p_div
= PLLU_BASE_POST_DIV
;
1226 for (val
= sel
->p
; val
> 1; val
>>= 1)
1228 p_div
<<= PLL_BASE_DIVP_SHIFT
;
1234 if (sel
->input_rate
== 0) {
1235 unsigned long cfreq
;
1236 BUG_ON(c
->flags
& PLLU
);
1239 switch (input_rate
) {
1242 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2000000;
1245 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2600000;
1249 cfreq
= (rate
<= 1200000 * 1000) ? 1200000 : 2400000;
1252 pr_err("%s: Unexpected reference rate %lu\n",
1253 __func__
, input_rate
);
1257 /* Raise VCO to guarantee 0.5% accuracy */
1258 for (cfg
.output_rate
= rate
; cfg
.output_rate
< 200 * cfreq
;
1259 cfg
.output_rate
<<= 1)
1262 cfg
.p
= 0x1 << p_div
;
1263 cfg
.m
= input_rate
/ cfreq
;
1264 cfg
.n
= cfg
.output_rate
/ cfreq
;
1268 div
= sel
->m
* sel
->p
;
1271 output_rate
+= div
- 1; /* round up */
1272 do_div(output_rate
, div
);
1277 static unsigned long tegra30_pll_recalc_rate(struct clk_hw
*hw
,
1278 unsigned long parent_rate
)
1280 struct clk_tegra
*c
= to_clk_tegra(hw
);
1281 u64 rate
= parent_rate
;
1282 u32 val
= clk_readl(c
->reg
+ PLL_BASE
);
1284 if (c
->flags
& PLL_FIXED
&& !(val
& PLL_BASE_OVERRIDE
)) {
1285 const struct clk_pll_freq_table
*sel
;
1286 for (sel
= c
->u
.pll
.freq_table
; sel
->input_rate
!= 0; sel
++) {
1287 if (sel
->input_rate
== parent_rate
&&
1288 sel
->output_rate
== c
->u
.pll
.fixed_rate
) {
1290 c
->div
= sel
->m
* sel
->p
;
1294 pr_err("Clock %s has unknown fixed frequency\n",
1295 __clk_get_name(hw
->clk
));
1297 } else if (val
& PLL_BASE_BYPASS
) {
1301 c
->mul
= (val
& PLL_BASE_DIVN_MASK
) >> PLL_BASE_DIVN_SHIFT
;
1302 c
->div
= (val
& PLL_BASE_DIVM_MASK
) >> PLL_BASE_DIVM_SHIFT
;
1303 if (c
->flags
& PLLU
)
1304 c
->div
*= (val
& PLLU_BASE_POST_DIV
) ? 1 : 2;
1306 c
->div
*= (0x1 << ((val
& PLL_BASE_DIVP_MASK
) >>
1307 PLL_BASE_DIVP_SHIFT
));
1310 if (c
->mul
!= 0 && c
->div
!= 0) {
1312 rate
+= c
->div
- 1; /* round up */
1313 do_div(rate
, c
->div
);
1319 struct clk_ops tegra30_pll_ops
= {
1320 .is_enabled
= tegra30_pll_clk_is_enabled
,
1321 .init
= tegra30_pll_clk_init
,
1322 .enable
= tegra30_pll_clk_enable
,
1323 .disable
= tegra30_pll_clk_disable
,
1324 .recalc_rate
= tegra30_pll_recalc_rate
,
1325 .round_rate
= tegra30_pll_round_rate
,
1326 .set_rate
= tegra30_pll_clk_set_rate
,
1329 int tegra30_plld_clk_cfg_ex(struct clk_hw
*hw
,
1330 enum tegra_clk_ex_param p
, u32 setting
)
1332 struct clk_tegra
*c
= to_clk_tegra(hw
);
1336 case TEGRA_CLK_PLLD_CSI_OUT_ENB
:
1337 mask
= PLLD_BASE_CSI_CLKENABLE
;
1338 reg
= c
->reg
+ PLL_BASE
;
1340 case TEGRA_CLK_PLLD_DSI_OUT_ENB
:
1341 mask
= PLLD_MISC_DSI_CLKENABLE
;
1342 reg
= c
->reg
+ PLL_MISC(c
);
1344 case TEGRA_CLK_PLLD_MIPI_MUX_SEL
:
1345 if (!(c
->flags
& PLL_ALT_MISC_REG
)) {
1346 mask
= PLLD_BASE_DSIB_MUX_MASK
;
1347 reg
= c
->reg
+ PLL_BASE
;
1350 /* fall through - error since PLLD2 does not have MUX_SEL control */
1355 val
= clk_readl(reg
);
1360 clk_writel(val
, reg
);
1364 static int tegra30_plle_clk_is_enabled(struct clk_hw
*hw
)
1366 struct clk_tegra
*c
= to_clk_tegra(hw
);
1369 val
= clk_readl(c
->reg
+ PLL_BASE
);
1370 c
->state
= (val
& PLLE_BASE_ENABLE
) ? ON
: OFF
;
1374 static void tegra30_plle_clk_disable(struct clk_hw
*hw
)
1376 struct clk_tegra
*c
= to_clk_tegra(hw
);
1379 val
= clk_readl(c
->reg
+ PLL_BASE
);
1380 val
&= ~(PLLE_BASE_CML_ENABLE
| PLLE_BASE_ENABLE
);
1381 clk_writel(val
, c
->reg
+ PLL_BASE
);
1384 static void tegra30_plle_training(struct clk_tegra
*c
)
1388 /* PLLE is already disabled, and setup cleared;
1389 * create falling edge on PLLE IDDQ input */
1390 val
= pmc_readl(PMC_SATA_PWRGT
);
1391 val
|= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE
;
1392 pmc_writel(val
, PMC_SATA_PWRGT
);
1394 val
= pmc_readl(PMC_SATA_PWRGT
);
1395 val
|= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL
;
1396 pmc_writel(val
, PMC_SATA_PWRGT
);
1398 val
= pmc_readl(PMC_SATA_PWRGT
);
1399 val
&= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE
;
1400 pmc_writel(val
, PMC_SATA_PWRGT
);
1403 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1404 } while (!(val
& PLLE_MISC_READY
));
1407 static int tegra30_plle_configure(struct clk_hw
*hw
, bool force_training
)
1409 struct clk_tegra
*c
= to_clk_tegra(hw
);
1410 struct clk
*parent
= __clk_get_parent(hw
->clk
);
1411 const struct clk_pll_freq_table
*sel
;
1414 unsigned long rate
= c
->u
.pll
.fixed_rate
;
1415 unsigned long input_rate
= __clk_get_rate(parent
);
1417 for (sel
= c
->u
.pll
.freq_table
; sel
->input_rate
!= 0; sel
++) {
1418 if (sel
->input_rate
== input_rate
&& sel
->output_rate
== rate
)
1422 if (sel
->input_rate
== 0)
1425 /* disable PLLE, clear setup fiels */
1426 tegra30_plle_clk_disable(hw
);
1428 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1429 val
&= ~(PLLE_MISC_LOCK_ENABLE
| PLLE_MISC_SETUP_MASK
);
1430 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
1433 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1434 if (force_training
|| (!(val
& PLLE_MISC_READY
)))
1435 tegra30_plle_training(c
);
1437 /* configure dividers, setup, disable SS */
1438 val
= clk_readl(c
->reg
+ PLL_BASE
);
1439 val
&= ~PLLE_BASE_DIV_MASK
;
1440 val
|= PLLE_BASE_DIV(sel
->m
, sel
->n
, sel
->p
, sel
->cpcon
);
1441 clk_writel(val
, c
->reg
+ PLL_BASE
);
1443 c
->div
= sel
->m
* sel
->p
;
1445 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
1446 val
|= PLLE_MISC_SETUP_VALUE
;
1447 val
|= PLLE_MISC_LOCK_ENABLE
;
1448 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
1450 val
= clk_readl(PLLE_SS_CTRL
);
1451 val
|= PLLE_SS_DISABLE
;
1452 clk_writel(val
, PLLE_SS_CTRL
);
1454 /* enable and lock PLLE*/
1455 val
= clk_readl(c
->reg
+ PLL_BASE
);
1456 val
|= (PLLE_BASE_CML_ENABLE
| PLLE_BASE_ENABLE
);
1457 clk_writel(val
, c
->reg
+ PLL_BASE
);
1459 tegra30_pll_clk_wait_for_lock(c
, c
->reg
+ PLL_MISC(c
), PLLE_MISC_LOCK
);
1464 static int tegra30_plle_clk_enable(struct clk_hw
*hw
)
1466 struct clk_tegra
*c
= to_clk_tegra(hw
);
1468 return tegra30_plle_configure(hw
, !c
->set
);
1471 static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw
*hw
,
1472 unsigned long parent_rate
)
1474 struct clk_tegra
*c
= to_clk_tegra(hw
);
1475 unsigned long rate
= parent_rate
;
1478 val
= clk_readl(c
->reg
+ PLL_BASE
);
1479 c
->mul
= (val
& PLLE_BASE_DIVN_MASK
) >> PLLE_BASE_DIVN_SHIFT
;
1480 c
->div
= (val
& PLLE_BASE_DIVM_MASK
) >> PLLE_BASE_DIVM_SHIFT
;
1481 c
->div
*= (val
& PLLE_BASE_DIVP_MASK
) >> PLLE_BASE_DIVP_SHIFT
;
1483 if (c
->mul
!= 0 && c
->div
!= 0) {
1485 rate
+= c
->div
- 1; /* round up */
1486 do_div(rate
, c
->div
);
1491 struct clk_ops tegra30_plle_ops
= {
1492 .is_enabled
= tegra30_plle_clk_is_enabled
,
1493 .enable
= tegra30_plle_clk_enable
,
1494 .disable
= tegra30_plle_clk_disable
,
1495 .recalc_rate
= tegra30_plle_clk_recalc_rate
,
1498 /* Clock divider ops */
1499 static int tegra30_pll_div_clk_is_enabled(struct clk_hw
*hw
)
1501 struct clk_tegra
*c
= to_clk_tegra(hw
);
1503 if (c
->flags
& DIV_U71
) {
1504 u32 val
= clk_readl(c
->reg
);
1505 val
>>= c
->reg_shift
;
1506 c
->state
= (val
& PLL_OUT_CLKEN
) ? ON
: OFF
;
1507 if (!(val
& PLL_OUT_RESET_DISABLE
))
1515 static int tegra30_pll_div_clk_enable(struct clk_hw
*hw
)
1517 struct clk_tegra
*c
= to_clk_tegra(hw
);
1521 pr_debug("%s: %s\n", __func__
, __clk_get_name(hw
->clk
));
1522 if (c
->flags
& DIV_U71
) {
1523 val
= clk_readl(c
->reg
);
1524 new_val
= val
>> c
->reg_shift
;
1527 new_val
|= PLL_OUT_CLKEN
| PLL_OUT_RESET_DISABLE
;
1529 val
&= ~(0xFFFF << c
->reg_shift
);
1530 val
|= new_val
<< c
->reg_shift
;
1531 clk_writel_delay(val
, c
->reg
);
1533 } else if (c
->flags
& DIV_2
) {
1539 static void tegra30_pll_div_clk_disable(struct clk_hw
*hw
)
1541 struct clk_tegra
*c
= to_clk_tegra(hw
);
1545 pr_debug("%s: %s\n", __func__
, __clk_get_name(hw
->clk
));
1546 if (c
->flags
& DIV_U71
) {
1547 val
= clk_readl(c
->reg
);
1548 new_val
= val
>> c
->reg_shift
;
1551 new_val
&= ~(PLL_OUT_CLKEN
| PLL_OUT_RESET_DISABLE
);
1553 val
&= ~(0xFFFF << c
->reg_shift
);
1554 val
|= new_val
<< c
->reg_shift
;
1555 clk_writel_delay(val
, c
->reg
);
1559 static int tegra30_pll_div_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1560 unsigned long parent_rate
)
1562 struct clk_tegra
*c
= to_clk_tegra(hw
);
1567 if (c
->flags
& DIV_U71
) {
1568 divider_u71
= clk_div71_get_divider(
1569 parent_rate
, rate
, c
->flags
, ROUND_DIVIDER_UP
);
1570 if (divider_u71
>= 0) {
1571 val
= clk_readl(c
->reg
);
1572 new_val
= val
>> c
->reg_shift
;
1574 if (c
->flags
& DIV_U71_FIXED
)
1575 new_val
|= PLL_OUT_OVERRIDE
;
1576 new_val
&= ~PLL_OUT_RATIO_MASK
;
1577 new_val
|= divider_u71
<< PLL_OUT_RATIO_SHIFT
;
1579 val
&= ~(0xFFFF << c
->reg_shift
);
1580 val
|= new_val
<< c
->reg_shift
;
1581 clk_writel_delay(val
, c
->reg
);
1582 c
->div
= divider_u71
+ 2;
1584 c
->fixed_rate
= rate
;
1587 } else if (c
->flags
& DIV_2
) {
1588 c
->fixed_rate
= rate
;
1595 static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw
*hw
,
1596 unsigned long parent_rate
)
1598 struct clk_tegra
*c
= to_clk_tegra(hw
);
1599 u64 rate
= parent_rate
;
1601 if (c
->flags
& DIV_U71
) {
1603 u32 val
= clk_readl(c
->reg
);
1604 val
>>= c
->reg_shift
;
1606 divu71
= (val
& PLL_OUT_RATIO_MASK
) >> PLL_OUT_RATIO_SHIFT
;
1607 c
->div
= (divu71
+ 2);
1609 } else if (c
->flags
& DIV_2
) {
1610 if (c
->flags
& (PLLD
| PLLX
)) {
1619 if (c
->mul
!= 0 && c
->div
!= 0) {
1621 rate
+= c
->div
- 1; /* round up */
1622 do_div(rate
, c
->div
);
1628 static long tegra30_pll_div_clk_round_rate(struct clk_hw
*hw
,
1629 unsigned long rate
, unsigned long *prate
)
1631 struct clk_tegra
*c
= to_clk_tegra(hw
);
1632 unsigned long parent_rate
= __clk_get_rate(__clk_get_parent(hw
->clk
));
1636 parent_rate
= *prate
;
1638 if (c
->flags
& DIV_U71
) {
1639 divider
= clk_div71_get_divider(
1640 parent_rate
, rate
, c
->flags
, ROUND_DIVIDER_UP
);
1643 return DIV_ROUND_UP(parent_rate
* 2, divider
+ 2);
1644 } else if (c
->flags
& DIV_2
) {
1652 struct clk_ops tegra30_pll_div_ops
= {
1653 .is_enabled
= tegra30_pll_div_clk_is_enabled
,
1654 .enable
= tegra30_pll_div_clk_enable
,
1655 .disable
= tegra30_pll_div_clk_disable
,
1656 .set_rate
= tegra30_pll_div_clk_set_rate
,
1657 .recalc_rate
= tegra30_pll_div_clk_recalc_rate
,
1658 .round_rate
= tegra30_pll_div_clk_round_rate
,
1661 /* Periph clk ops */
1662 static inline u32
periph_clk_source_mask(struct clk_tegra
*c
)
1664 if (c
->flags
& MUX8
)
1666 else if (c
->flags
& MUX_PWM
)
1668 else if (c
->flags
& MUX_CLK_OUT
)
1669 return 3 << (c
->u
.periph
.clk_num
+ 4);
1670 else if (c
->flags
& PLLD
)
1671 return PLLD_BASE_DSIB_MUX_MASK
;
1676 static inline u32
periph_clk_source_shift(struct clk_tegra
*c
)
1678 if (c
->flags
& MUX8
)
1680 else if (c
->flags
& MUX_PWM
)
1682 else if (c
->flags
& MUX_CLK_OUT
)
1683 return c
->u
.periph
.clk_num
+ 4;
1684 else if (c
->flags
& PLLD
)
1685 return PLLD_BASE_DSIB_MUX_SHIFT
;
1690 static int tegra30_periph_clk_is_enabled(struct clk_hw
*hw
)
1692 struct clk_tegra
*c
= to_clk_tegra(hw
);
1695 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c
)) & PERIPH_CLK_TO_BIT(c
)))
1697 if (!(c
->flags
& PERIPH_NO_RESET
))
1698 if (clk_readl(PERIPH_CLK_TO_RST_REG(c
)) & PERIPH_CLK_TO_BIT(c
))
1703 static int tegra30_periph_clk_enable(struct clk_hw
*hw
)
1705 struct clk_tegra
*c
= to_clk_tegra(hw
);
1707 tegra_periph_clk_enable_refcount
[c
->u
.periph
.clk_num
]++;
1708 if (tegra_periph_clk_enable_refcount
[c
->u
.periph
.clk_num
] > 1)
1711 clk_writel_delay(PERIPH_CLK_TO_BIT(c
), PERIPH_CLK_TO_ENB_SET_REG(c
));
1712 if (!(c
->flags
& PERIPH_NO_RESET
) &&
1713 !(c
->flags
& PERIPH_MANUAL_RESET
)) {
1714 if (clk_readl(PERIPH_CLK_TO_RST_REG(c
)) &
1715 PERIPH_CLK_TO_BIT(c
)) {
1716 udelay(5); /* reset propagation delay */
1717 clk_writel(PERIPH_CLK_TO_BIT(c
),
1718 PERIPH_CLK_TO_RST_CLR_REG(c
));
1724 static void tegra30_periph_clk_disable(struct clk_hw
*hw
)
1726 struct clk_tegra
*c
= to_clk_tegra(hw
);
1729 tegra_periph_clk_enable_refcount
[c
->u
.periph
.clk_num
]--;
1731 if (tegra_periph_clk_enable_refcount
[c
->u
.periph
.clk_num
] > 0)
1734 /* If peripheral is in the APB bus then read the APB bus to
1735 * flush the write operation in apb bus. This will avoid the
1736 * peripheral access after disabling clock*/
1737 if (c
->flags
& PERIPH_ON_APB
)
1738 val
= chipid_readl();
1740 clk_writel_delay(PERIPH_CLK_TO_BIT(c
), PERIPH_CLK_TO_ENB_CLR_REG(c
));
1743 void tegra30_periph_clk_reset(struct clk_hw
*hw
, bool assert)
1745 struct clk_tegra
*c
= to_clk_tegra(hw
);
1748 if (!(c
->flags
& PERIPH_NO_RESET
)) {
1750 /* If peripheral is in the APB bus then read the APB
1751 * bus to flush the write operation in apb bus. This
1752 * will avoid the peripheral access after disabling
1754 if (c
->flags
& PERIPH_ON_APB
)
1755 val
= chipid_readl();
1757 clk_writel(PERIPH_CLK_TO_BIT(c
),
1758 PERIPH_CLK_TO_RST_SET_REG(c
));
1760 clk_writel(PERIPH_CLK_TO_BIT(c
),
1761 PERIPH_CLK_TO_RST_CLR_REG(c
));
1765 static int tegra30_periph_clk_set_parent(struct clk_hw
*hw
, u8 index
)
1767 struct clk_tegra
*c
= to_clk_tegra(hw
);
1770 if (!(c
->flags
& MUX
))
1771 return (index
== 0) ? 0 : (-EINVAL
);
1773 val
= clk_readl(c
->reg
);
1774 val
&= ~periph_clk_source_mask(c
);
1775 val
|= (index
<< periph_clk_source_shift(c
));
1776 clk_writel_delay(val
, c
->reg
);
1780 static u8
tegra30_periph_clk_get_parent(struct clk_hw
*hw
)
1782 struct clk_tegra
*c
= to_clk_tegra(hw
);
1783 u32 val
= clk_readl(c
->reg
);
1784 int source
= (val
& periph_clk_source_mask(c
)) >>
1785 periph_clk_source_shift(c
);
1787 if (!(c
->flags
& MUX
))
1793 static int tegra30_periph_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1794 unsigned long parent_rate
)
1796 struct clk_tegra
*c
= to_clk_tegra(hw
);
1800 if (c
->flags
& DIV_U71
) {
1801 divider
= clk_div71_get_divider(
1802 parent_rate
, rate
, c
->flags
, ROUND_DIVIDER_UP
);
1804 val
= clk_readl(c
->reg
);
1805 val
&= ~PERIPH_CLK_SOURCE_DIVU71_MASK
;
1807 if (c
->flags
& DIV_U71_UART
) {
1809 val
|= PERIPH_CLK_UART_DIV_ENB
;
1811 val
&= ~PERIPH_CLK_UART_DIV_ENB
;
1813 clk_writel_delay(val
, c
->reg
);
1814 c
->div
= divider
+ 2;
1818 } else if (c
->flags
& DIV_U16
) {
1819 divider
= clk_div16_get_divider(parent_rate
, rate
);
1821 val
= clk_readl(c
->reg
);
1822 val
&= ~PERIPH_CLK_SOURCE_DIVU16_MASK
;
1824 clk_writel_delay(val
, c
->reg
);
1825 c
->div
= divider
+ 1;
1829 } else if (parent_rate
<= rate
) {
1837 static long tegra30_periph_clk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1838 unsigned long *prate
)
1840 struct clk_tegra
*c
= to_clk_tegra(hw
);
1841 unsigned long parent_rate
= __clk_get_rate(__clk_get_parent(hw
->clk
));
1845 parent_rate
= *prate
;
1847 if (c
->flags
& DIV_U71
) {
1848 divider
= clk_div71_get_divider(
1849 parent_rate
, rate
, c
->flags
, ROUND_DIVIDER_UP
);
1853 return DIV_ROUND_UP(parent_rate
* 2, divider
+ 2);
1854 } else if (c
->flags
& DIV_U16
) {
1855 divider
= clk_div16_get_divider(parent_rate
, rate
);
1858 return DIV_ROUND_UP(parent_rate
, divider
+ 1);
1863 static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw
*hw
,
1864 unsigned long parent_rate
)
1866 struct clk_tegra
*c
= to_clk_tegra(hw
);
1867 u64 rate
= parent_rate
;
1868 u32 val
= clk_readl(c
->reg
);
1870 if (c
->flags
& DIV_U71
) {
1871 u32 divu71
= val
& PERIPH_CLK_SOURCE_DIVU71_MASK
;
1872 if ((c
->flags
& DIV_U71_UART
) &&
1873 (!(val
& PERIPH_CLK_UART_DIV_ENB
))) {
1876 if (c
->flags
& DIV_U71_IDLE
) {
1877 val
&= ~(PERIPH_CLK_SOURCE_DIVU71_MASK
<<
1878 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT
);
1879 val
|= (PERIPH_CLK_SOURCE_DIVIDLE_VAL
<<
1880 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT
);
1881 clk_writel(val
, c
->reg
);
1883 c
->div
= divu71
+ 2;
1885 } else if (c
->flags
& DIV_U16
) {
1886 u32 divu16
= val
& PERIPH_CLK_SOURCE_DIVU16_MASK
;
1887 c
->div
= divu16
+ 1;
1894 if (c
->mul
!= 0 && c
->div
!= 0) {
1896 rate
+= c
->div
- 1; /* round up */
1897 do_div(rate
, c
->div
);
1902 struct clk_ops tegra30_periph_clk_ops
= {
1903 .is_enabled
= tegra30_periph_clk_is_enabled
,
1904 .enable
= tegra30_periph_clk_enable
,
1905 .disable
= tegra30_periph_clk_disable
,
1906 .set_parent
= tegra30_periph_clk_set_parent
,
1907 .get_parent
= tegra30_periph_clk_get_parent
,
1908 .set_rate
= tegra30_periph_clk_set_rate
,
1909 .round_rate
= tegra30_periph_clk_round_rate
,
1910 .recalc_rate
= tegra30_periph_clk_recalc_rate
,
1913 static int tegra30_dsib_clk_set_parent(struct clk_hw
*hw
, u8 index
)
1915 struct clk
*d
= clk_get_sys(NULL
, "pll_d");
1916 /* The DSIB parent selection bit is in PLLD base
1917 register - can not do direct r-m-w, must be
1918 protected by PLLD lock */
1920 d
, TEGRA_CLK_PLLD_MIPI_MUX_SEL
, index
);
1925 struct clk_ops tegra30_dsib_clk_ops
= {
1926 .is_enabled
= tegra30_periph_clk_is_enabled
,
1927 .enable
= &tegra30_periph_clk_enable
,
1928 .disable
= &tegra30_periph_clk_disable
,
1929 .set_parent
= &tegra30_dsib_clk_set_parent
,
1930 .get_parent
= &tegra30_periph_clk_get_parent
,
1931 .set_rate
= &tegra30_periph_clk_set_rate
,
1932 .round_rate
= &tegra30_periph_clk_round_rate
,
1933 .recalc_rate
= &tegra30_periph_clk_recalc_rate
,
1936 /* Periph extended clock configuration ops */
1937 int tegra30_vi_clk_cfg_ex(struct clk_hw
*hw
,
1938 enum tegra_clk_ex_param p
, u32 setting
)
1940 struct clk_tegra
*c
= to_clk_tegra(hw
);
1942 if (p
== TEGRA_CLK_VI_INP_SEL
) {
1943 u32 val
= clk_readl(c
->reg
);
1944 val
&= ~PERIPH_CLK_VI_SEL_EX_MASK
;
1945 val
|= (setting
<< PERIPH_CLK_VI_SEL_EX_SHIFT
) &
1946 PERIPH_CLK_VI_SEL_EX_MASK
;
1947 clk_writel(val
, c
->reg
);
1953 int tegra30_nand_clk_cfg_ex(struct clk_hw
*hw
,
1954 enum tegra_clk_ex_param p
, u32 setting
)
1956 struct clk_tegra
*c
= to_clk_tegra(hw
);
1958 if (p
== TEGRA_CLK_NAND_PAD_DIV2_ENB
) {
1959 u32 val
= clk_readl(c
->reg
);
1961 val
|= PERIPH_CLK_NAND_DIV_EX_ENB
;
1963 val
&= ~PERIPH_CLK_NAND_DIV_EX_ENB
;
1964 clk_writel(val
, c
->reg
);
1970 int tegra30_dtv_clk_cfg_ex(struct clk_hw
*hw
,
1971 enum tegra_clk_ex_param p
, u32 setting
)
1973 struct clk_tegra
*c
= to_clk_tegra(hw
);
1975 if (p
== TEGRA_CLK_DTV_INVERT
) {
1976 u32 val
= clk_readl(c
->reg
);
1978 val
|= PERIPH_CLK_DTV_POLARITY_INV
;
1980 val
&= ~PERIPH_CLK_DTV_POLARITY_INV
;
1981 clk_writel(val
, c
->reg
);
1987 /* Output clock ops */
1989 static DEFINE_SPINLOCK(clk_out_lock
);
1991 static int tegra30_clk_out_is_enabled(struct clk_hw
*hw
)
1993 struct clk_tegra
*c
= to_clk_tegra(hw
);
1994 u32 val
= pmc_readl(c
->reg
);
1996 c
->state
= (val
& (0x1 << c
->u
.periph
.clk_num
)) ? ON
: OFF
;
2002 static int tegra30_clk_out_enable(struct clk_hw
*hw
)
2004 struct clk_tegra
*c
= to_clk_tegra(hw
);
2006 unsigned long flags
;
2008 spin_lock_irqsave(&clk_out_lock
, flags
);
2009 val
= pmc_readl(c
->reg
);
2010 val
|= (0x1 << c
->u
.periph
.clk_num
);
2011 pmc_writel(val
, c
->reg
);
2012 spin_unlock_irqrestore(&clk_out_lock
, flags
);
2017 static void tegra30_clk_out_disable(struct clk_hw
*hw
)
2019 struct clk_tegra
*c
= to_clk_tegra(hw
);
2021 unsigned long flags
;
2023 spin_lock_irqsave(&clk_out_lock
, flags
);
2024 val
= pmc_readl(c
->reg
);
2025 val
&= ~(0x1 << c
->u
.periph
.clk_num
);
2026 pmc_writel(val
, c
->reg
);
2027 spin_unlock_irqrestore(&clk_out_lock
, flags
);
2030 static int tegra30_clk_out_set_parent(struct clk_hw
*hw
, u8 index
)
2032 struct clk_tegra
*c
= to_clk_tegra(hw
);
2034 unsigned long flags
;
2036 spin_lock_irqsave(&clk_out_lock
, flags
);
2037 val
= pmc_readl(c
->reg
);
2038 val
&= ~periph_clk_source_mask(c
);
2039 val
|= (index
<< periph_clk_source_shift(c
));
2040 pmc_writel(val
, c
->reg
);
2041 spin_unlock_irqrestore(&clk_out_lock
, flags
);
2046 static u8
tegra30_clk_out_get_parent(struct clk_hw
*hw
)
2048 struct clk_tegra
*c
= to_clk_tegra(hw
);
2049 u32 val
= pmc_readl(c
->reg
);
2052 source
= (val
& periph_clk_source_mask(c
)) >>
2053 periph_clk_source_shift(c
);
2057 struct clk_ops tegra_clk_out_ops
= {
2058 .is_enabled
= tegra30_clk_out_is_enabled
,
2059 .enable
= tegra30_clk_out_enable
,
2060 .disable
= tegra30_clk_out_disable
,
2061 .set_parent
= tegra30_clk_out_set_parent
,
2062 .get_parent
= tegra30_clk_out_get_parent
,
2063 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2066 /* Clock doubler ops */
2067 static int tegra30_clk_double_is_enabled(struct clk_hw
*hw
)
2069 struct clk_tegra
*c
= to_clk_tegra(hw
);
2072 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c
)) & PERIPH_CLK_TO_BIT(c
)))
2077 static int tegra30_clk_double_set_rate(struct clk_hw
*hw
, unsigned long rate
,
2078 unsigned long parent_rate
)
2080 struct clk_tegra
*c
= to_clk_tegra(hw
);
2083 if (rate
== parent_rate
) {
2084 val
= clk_readl(c
->reg
) | (0x1 << c
->reg_shift
);
2085 clk_writel(val
, c
->reg
);
2089 } else if (rate
== 2 * parent_rate
) {
2090 val
= clk_readl(c
->reg
) & (~(0x1 << c
->reg_shift
));
2091 clk_writel(val
, c
->reg
);
2099 static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw
*hw
,
2100 unsigned long parent_rate
)
2102 struct clk_tegra
*c
= to_clk_tegra(hw
);
2103 u64 rate
= parent_rate
;
2105 u32 val
= clk_readl(c
->reg
);
2106 c
->mul
= val
& (0x1 << c
->reg_shift
) ? 1 : 2;
2109 if (c
->mul
!= 0 && c
->div
!= 0) {
2111 rate
+= c
->div
- 1; /* round up */
2112 do_div(rate
, c
->div
);
2118 static long tegra30_clk_double_round_rate(struct clk_hw
*hw
, unsigned long rate
,
2119 unsigned long *prate
)
2121 unsigned long output_rate
= *prate
;
2123 do_div(output_rate
, 2);
2127 struct clk_ops tegra30_clk_double_ops
= {
2128 .is_enabled
= tegra30_clk_double_is_enabled
,
2129 .enable
= tegra30_periph_clk_enable
,
2130 .disable
= tegra30_periph_clk_disable
,
2131 .recalc_rate
= tegra30_clk_double_recalc_rate
,
2132 .round_rate
= tegra30_clk_double_round_rate
,
2133 .set_rate
= tegra30_clk_double_set_rate
,
2136 /* Audio sync clock ops */
2137 struct clk_ops tegra_sync_source_ops
= {
2138 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2141 static int tegra30_audio_sync_clk_is_enabled(struct clk_hw
*hw
)
2143 struct clk_tegra
*c
= to_clk_tegra(hw
);
2144 u32 val
= clk_readl(c
->reg
);
2145 c
->state
= (val
& AUDIO_SYNC_DISABLE_BIT
) ? OFF
: ON
;
2149 static int tegra30_audio_sync_clk_enable(struct clk_hw
*hw
)
2151 struct clk_tegra
*c
= to_clk_tegra(hw
);
2152 u32 val
= clk_readl(c
->reg
);
2153 clk_writel((val
& (~AUDIO_SYNC_DISABLE_BIT
)), c
->reg
);
2157 static void tegra30_audio_sync_clk_disable(struct clk_hw
*hw
)
2159 struct clk_tegra
*c
= to_clk_tegra(hw
);
2160 u32 val
= clk_readl(c
->reg
);
2161 clk_writel((val
| AUDIO_SYNC_DISABLE_BIT
), c
->reg
);
2164 static int tegra30_audio_sync_clk_set_parent(struct clk_hw
*hw
, u8 index
)
2166 struct clk_tegra
*c
= to_clk_tegra(hw
);
2169 val
= clk_readl(c
->reg
);
2170 val
&= ~AUDIO_SYNC_SOURCE_MASK
;
2173 clk_writel(val
, c
->reg
);
2177 static u8
tegra30_audio_sync_clk_get_parent(struct clk_hw
*hw
)
2179 struct clk_tegra
*c
= to_clk_tegra(hw
);
2180 u32 val
= clk_readl(c
->reg
);
2183 source
= val
& AUDIO_SYNC_SOURCE_MASK
;
2187 struct clk_ops tegra30_audio_sync_clk_ops
= {
2188 .is_enabled
= tegra30_audio_sync_clk_is_enabled
,
2189 .enable
= tegra30_audio_sync_clk_enable
,
2190 .disable
= tegra30_audio_sync_clk_disable
,
2191 .set_parent
= tegra30_audio_sync_clk_set_parent
,
2192 .get_parent
= tegra30_audio_sync_clk_get_parent
,
2193 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2196 /* cml0 (pcie), and cml1 (sata) clock ops */
2197 static int tegra30_cml_clk_is_enabled(struct clk_hw
*hw
)
2199 struct clk_tegra
*c
= to_clk_tegra(hw
);
2200 u32 val
= clk_readl(c
->reg
);
2201 c
->state
= val
& (0x1 << c
->u
.periph
.clk_num
) ? ON
: OFF
;
2205 static int tegra30_cml_clk_enable(struct clk_hw
*hw
)
2207 struct clk_tegra
*c
= to_clk_tegra(hw
);
2209 u32 val
= clk_readl(c
->reg
);
2210 val
|= (0x1 << c
->u
.periph
.clk_num
);
2211 clk_writel(val
, c
->reg
);
2216 static void tegra30_cml_clk_disable(struct clk_hw
*hw
)
2218 struct clk_tegra
*c
= to_clk_tegra(hw
);
2220 u32 val
= clk_readl(c
->reg
);
2221 val
&= ~(0x1 << c
->u
.periph
.clk_num
);
2222 clk_writel(val
, c
->reg
);
2225 struct clk_ops tegra_cml_clk_ops
= {
2226 .is_enabled
= tegra30_cml_clk_is_enabled
,
2227 .enable
= tegra30_cml_clk_enable
,
2228 .disable
= tegra30_cml_clk_disable
,
2229 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2232 struct clk_ops tegra_pciex_clk_ops
= {
2233 .recalc_rate
= tegra30_clk_fixed_recalc_rate
,
2236 /* Tegra30 CPU clock and reset control functions */
2237 static void tegra30_wait_cpu_in_reset(u32 cpu
)
2242 reg
= readl(reg_clk_base
+
2243 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS
);
2245 } while (!(reg
& (1 << cpu
))); /* check CPU been reset or not */
2250 static void tegra30_put_cpu_in_reset(u32 cpu
)
2252 writel(CPU_RESET(cpu
),
2253 reg_clk_base
+ TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET
);
2257 static void tegra30_cpu_out_of_reset(u32 cpu
)
2259 writel(CPU_RESET(cpu
),
2260 reg_clk_base
+ TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR
);
2264 static void tegra30_enable_cpu_clock(u32 cpu
)
2268 writel(CPU_CLOCK(cpu
),
2269 reg_clk_base
+ TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR
);
2270 reg
= readl(reg_clk_base
+
2271 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR
);
2274 static void tegra30_disable_cpu_clock(u32 cpu
)
2279 reg
= readl(reg_clk_base
+ TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX
);
2280 writel(reg
| CPU_CLOCK(cpu
),
2281 reg_clk_base
+ TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX
);
2284 static struct tegra_cpu_car_ops tegra30_cpu_car_ops
= {
2285 .wait_for_reset
= tegra30_wait_cpu_in_reset
,
2286 .put_in_reset
= tegra30_put_cpu_in_reset
,
2287 .out_of_reset
= tegra30_cpu_out_of_reset
,
2288 .enable_clock
= tegra30_enable_cpu_clock
,
2289 .disable_clock
= tegra30_disable_cpu_clock
,
2292 void __init
tegra30_cpu_car_ops_init(void)
2294 tegra_cpu_car_ops
= &tegra30_cpu_car_ops
;