arch/arm/mach-ux500/platsmp.c

   1 /*
   2  * Copyright (C) 2002 ARM Ltd.
   3  * Copyright (C) 2008 STMicroelctronics.
   4  * Copyright (C) 2009 ST-Ericsson.
   5  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
   6  *
   7  * This file is based on arm realview platform
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/errno.h>
  15 #include <linux/delay.h>
  16 #include <linux/device.h>
  17 #include <linux/smp.h>
  18 #include <linux/io.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/smp_plat.h>
  24 #include <asm/smp_scu.h>
  25
  26 #include "setup.h"
  27
  28 #include "db8500-regs.h"
  29
  30 /* Magic triggers in backup RAM */
  31 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
  32 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
  33
  34 static void __iomem *backupram;
  35
  36 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
  37 {
  38         struct device_node *np;
  39         static void __iomem *scu_base;
  40         unsigned int ncores;
  41         int i;
  42
  43         np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
  44         if (!np) {
  45                 pr_err("No backupram base address\n");
  46                 return;
  47         }
  48         backupram = of_iomap(np, 0);
  49         of_node_put(np);
  50         if (!backupram) {
  51                 pr_err("No backupram remap\n");
  52                 return;
  53         }
  54
  55         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
  56         if (!np) {
  57                 pr_err("No SCU base address\n");
  58                 return;
  59         }
  60         scu_base = of_iomap(np, 0);
  61         of_node_put(np);
  62         if (!scu_base) {
  63                 pr_err("No SCU remap\n");
  64                 return;
  65         }
  66
  67         scu_enable(scu_base);
  68         ncores = scu_get_core_count(scu_base);
  69         for (i = 0; i < ncores; i++)
  70                 set_cpu_possible(i, true);
  71         iounmap(scu_base);
  72 }
  73
  74 static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
  75 {
  76         /*
  77          * write the address of secondary startup into the backup ram register
  78          * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
  79          * backup ram register at offset 0x1FF0, which is what boot rom code
  80          * is waiting for. This will wake up the secondary core from WFE.
  81          */
  82         writel(__pa_symbol(secondary_startup),
  83                backupram + UX500_CPU1_JUMPADDR_OFFSET);
  84         writel(0xA1FEED01,
  85                backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
  86
  87         /* make sure write buffer is drained */
  88         mb();
  89         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  90         return 0;
  91 }
  92
  93 static const struct smp_operations ux500_smp_ops __initconst = {
  94         .smp_prepare_cpus       = ux500_smp_prepare_cpus,
  95         .smp_boot_secondary     = ux500_boot_secondary,
  96 #ifdef CONFIG_HOTPLUG_CPU
  97         .cpu_die                = ux500_cpu_die,
  98 #endif
  99 };
 100 CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);