arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29 #include <linux/amba/pl061.h>
  30 #include <linux/amba/mmci.h>
  31 #include <linux/amba/pl022.h>
  32 #include <linux/io.h>
  33 #include <linux/gfp.h>
  34 #include <linux/clkdev.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/icst.h>
  41 #include <asm/hardware/vic.h>
  42 #include <asm/mach-types.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/flash.h>
  46 #include <asm/mach/irq.h>
  47 #include <asm/mach/time.h>
  48 #include <asm/mach/map.h>
  49 #include <mach/hardware.h>
  50 #include <mach/platform.h>
  51 #include <plat/timer-sp.h>
  52
  53 #include "core.h"
  54
  55 /*
  56  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  57  * is the (PA >> 12).
  58  *
  59  * Setup a VA for the Versatile Vectored Interrupt Controller.
  60  */
  61 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  62 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  63
  64 static void sic_mask_irq(unsigned int irq)
  65 {
  66         irq -= IRQ_SIC_START;
  67         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  68 }
  69
  70 static void sic_unmask_irq(unsigned int irq)
  71 {
  72         irq -= IRQ_SIC_START;
  73         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  74 }
  75
  76 static struct irq_chip sic_chip = {
  77         .name   = "SIC",
  78         .ack    = sic_mask_irq,
  79         .mask   = sic_mask_irq,
  80         .unmask = sic_unmask_irq,
  81 };
  82
  83 static void
  84 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
  85 {
  86         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  87
  88         if (status == 0) {
  89                 do_bad_IRQ(irq, desc);
  90                 return;
  91         }
  92
  93         do {
  94                 irq = ffs(status) - 1;
  95                 status &= ~(1 << irq);
  96
  97                 irq += IRQ_SIC_START;
  98
  99                 generic_handle_irq(irq);
 100         } while (status);
 101 }
 102
 103 #if 1
 104 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 105 #define IRQ_AACI        IRQ_VICSOURCE24
 106 #define IRQ_ETH         IRQ_VICSOURCE25
 107 #define PIC_MASK        0xFFD00000
 108 #else
 109 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 110 #define IRQ_AACI        IRQ_SIC_AACI
 111 #define IRQ_ETH         IRQ_SIC_ETH
 112 #define PIC_MASK        0
 113 #endif
 114
 115 void __init versatile_init_irq(void)
 116 {
 117         unsigned int i;
 118
 119         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
 120
 121         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 122
 123         /* Do second interrupt controller */
 124         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 125
 126         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 127                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 128                         set_irq_chip(i, &sic_chip);
 129                         set_irq_handler(i, handle_level_irq);
 130                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 131                 }
 132         }
 133
 134         /*
 135          * Interrupts on secondary controller from 0 to 8 are routed to
 136          * source 31 on PIC.
 137          * Interrupts from 21 to 31 are routed directly to the VIC on
 138          * the corresponding number on primary controller. This is controlled
 139          * by setting PIC_ENABLEx.
 140          */
 141         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 142 }
 143
 144 static struct map_desc versatile_io_desc[] __initdata = {
 145         {
 146                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 147                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 148                 .length         = SZ_4K,
 149                 .type           = MT_DEVICE
 150         }, {
 151                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 152                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 153                 .length         = SZ_4K,
 154                 .type           = MT_DEVICE
 155         }, {
 156                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 157                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 158                 .length         = SZ_4K,
 159                 .type           = MT_DEVICE
 160         }, {
 161                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 162                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 163                 .length         = SZ_4K * 9,
 164                 .type           = MT_DEVICE
 165         },
 166 #ifdef CONFIG_MACH_VERSATILE_AB
 167         {
 168                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 169                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 170                 .length         = SZ_4K,
 171                 .type           = MT_DEVICE
 172         }, {
 173                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 174                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 175                 .length         = SZ_64M,
 176                 .type           = MT_DEVICE
 177         },
 178 #endif
 179 #ifdef CONFIG_DEBUG_LL
 180         {
 181                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 182                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 183                 .length         = SZ_4K,
 184                 .type           = MT_DEVICE
 185         },
 186 #endif
 187 #ifdef CONFIG_PCI
 188         {
 189                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 190                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 191                 .length         = SZ_4K,
 192                 .type           = MT_DEVICE
 193         }, {
 194                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 195                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 196                 .length         = VERSATILE_PCI_BASE_SIZE,
 197                 .type           = MT_DEVICE
 198         }, {
 199                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 200                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 201                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 202                 .type           = MT_DEVICE
 203         },
 204 #if 0
 205         {
 206                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 207                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 208                 .length         = SZ_16M,
 209                 .type           = MT_DEVICE
 210         }, {
 211                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 212                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 213                 .length         = SZ_16M,
 214                 .type           = MT_DEVICE
 215         }, {
 216                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 217                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 218                 .length         = SZ_16M,
 219                 .type           = MT_DEVICE
 220         },
 221 #endif
 222 #endif
 223 };
 224
 225 void __init versatile_map_io(void)
 226 {
 227         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 228 }
 229
 230
 231 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 232
 233 static int versatile_flash_init(void)
 234 {
 235         u32 val;
 236
 237         val = __raw_readl(VERSATILE_FLASHCTRL);
 238         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 239         __raw_writel(val, VERSATILE_FLASHCTRL);
 240
 241         return 0;
 242 }
 243
 244 static void versatile_flash_exit(void)
 245 {
 246         u32 val;
 247
 248         val = __raw_readl(VERSATILE_FLASHCTRL);
 249         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 250         __raw_writel(val, VERSATILE_FLASHCTRL);
 251 }
 252
 253 static void versatile_flash_set_vpp(int on)
 254 {
 255         u32 val;
 256
 257         val = __raw_readl(VERSATILE_FLASHCTRL);
 258         if (on)
 259                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 260         else
 261                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 262         __raw_writel(val, VERSATILE_FLASHCTRL);
 263 }
 264
 265 static struct flash_platform_data versatile_flash_data = {
 266         .map_name               = "cfi_probe",
 267         .width                  = 4,
 268         .init                   = versatile_flash_init,
 269         .exit                   = versatile_flash_exit,
 270         .set_vpp                = versatile_flash_set_vpp,
 271 };
 272
 273 static struct resource versatile_flash_resource = {
 274         .start                  = VERSATILE_FLASH_BASE,
 275         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 276         .flags                  = IORESOURCE_MEM,
 277 };
 278
 279 static struct platform_device versatile_flash_device = {
 280         .name                   = "armflash",
 281         .id                     = 0,
 282         .dev                    = {
 283                 .platform_data  = &versatile_flash_data,
 284         },
 285         .num_resources          = 1,
 286         .resource               = &versatile_flash_resource,
 287 };
 288
 289 static struct resource smc91x_resources[] = {
 290         [0] = {
 291                 .start          = VERSATILE_ETH_BASE,
 292                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 293                 .flags          = IORESOURCE_MEM,
 294         },
 295         [1] = {
 296                 .start          = IRQ_ETH,
 297                 .end            = IRQ_ETH,
 298                 .flags          = IORESOURCE_IRQ,
 299         },
 300 };
 301
 302 static struct platform_device smc91x_device = {
 303         .name           = "smc91x",
 304         .id             = 0,
 305         .num_resources  = ARRAY_SIZE(smc91x_resources),
 306         .resource       = smc91x_resources,
 307 };
 308
 309 static struct resource versatile_i2c_resource = {
 310         .start                  = VERSATILE_I2C_BASE,
 311         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 312         .flags                  = IORESOURCE_MEM,
 313 };
 314
 315 static struct platform_device versatile_i2c_device = {
 316         .name                   = "versatile-i2c",
 317         .id                     = 0,
 318         .num_resources          = 1,
 319         .resource               = &versatile_i2c_resource,
 320 };
 321
 322 static struct i2c_board_info versatile_i2c_board_info[] = {
 323         {
 324                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 325         },
 326 };
 327
 328 static int __init versatile_i2c_init(void)
 329 {
 330         return i2c_register_board_info(0, versatile_i2c_board_info,
 331                                        ARRAY_SIZE(versatile_i2c_board_info));
 332 }
 333 arch_initcall(versatile_i2c_init);
 334
 335 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 336
 337 unsigned int mmc_status(struct device *dev)
 338 {
 339         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 340         u32 mask;
 341
 342         if (adev->res.start == VERSATILE_MMCI0_BASE)
 343                 mask = 1;
 344         else
 345                 mask = 2;
 346
 347         return readl(VERSATILE_SYSMCI) & mask;
 348 }
 349
 350 static struct mmci_platform_data mmc0_plat_data = {
 351         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 352         .status         = mmc_status,
 353         .gpio_wp        = -1,
 354         .gpio_cd        = -1,
 355 };
 356
 357 static struct resource char_lcd_resources[] = {
 358         {
 359                 .start = VERSATILE_CHAR_LCD_BASE,
 360                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
 361                 .flags = IORESOURCE_MEM,
 362         },
 363 };
 364
 365 static struct platform_device char_lcd_device = {
 366         .name           =       "arm-charlcd",
 367         .id             =       -1,
 368         .num_resources  =       ARRAY_SIZE(char_lcd_resources),
 369         .resource       =       char_lcd_resources,
 370 };
 371
 372 /*
 373  * Clock handling
 374  */
 375 static const struct icst_params versatile_oscvco_params = {
 376         .ref            = 24000000,
 377         .vco_max        = ICST307_VCO_MAX,
 378         .vco_min        = ICST307_VCO_MIN,
 379         .vd_min         = 4 + 8,
 380         .vd_max         = 511 + 8,
 381         .rd_min         = 1 + 2,
 382         .rd_max         = 127 + 2,
 383         .s2div          = icst307_s2div,
 384         .idx2s          = icst307_idx2s,
 385 };
 386
 387 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 388 {
 389         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 390         u32 val;
 391
 392         val = readl(clk->vcoreg) & ~0x7ffff;
 393         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 394
 395         writel(0xa05f, sys_lock);
 396         writel(val, clk->vcoreg);
 397         writel(0, sys_lock);
 398 }
 399
 400 static const struct clk_ops osc4_clk_ops = {
 401         .round  = icst_clk_round,
 402         .set    = icst_clk_set,
 403         .setvco = versatile_oscvco_set,
 404 };
 405
 406 static struct clk osc4_clk = {
 407         .ops    = &osc4_clk_ops,
 408         .params = &versatile_oscvco_params,
 409 };
 410
 411 /*
 412  * These are fixed clocks.
 413  */
 414 static struct clk ref24_clk = {
 415         .rate   = 24000000,
 416 };
 417
 418 static struct clk dummy_apb_pclk;
 419
 420 static struct clk_lookup lookups[] = {
 421         {       /* AMBA bus clock */
 422                 .con_id         = "apb_pclk",
 423                 .clk            = &dummy_apb_pclk,
 424         }, {    /* UART0 */
 425                 .dev_id         = "dev:f1",
 426                 .clk            = &ref24_clk,
 427         }, {    /* UART1 */
 428                 .dev_id         = "dev:f2",
 429                 .clk            = &ref24_clk,
 430         }, {    /* UART2 */
 431                 .dev_id         = "dev:f3",
 432                 .clk            = &ref24_clk,
 433         }, {    /* UART3 */
 434                 .dev_id         = "fpga:09",
 435                 .clk            = &ref24_clk,
 436         }, {    /* KMI0 */
 437                 .dev_id         = "fpga:06",
 438                 .clk            = &ref24_clk,
 439         }, {    /* KMI1 */
 440                 .dev_id         = "fpga:07",
 441                 .clk            = &ref24_clk,
 442         }, {    /* MMC0 */
 443                 .dev_id         = "fpga:05",
 444                 .clk            = &ref24_clk,
 445         }, {    /* MMC1 */
 446                 .dev_id         = "fpga:0b",
 447                 .clk            = &ref24_clk,
 448         }, {    /* SSP */
 449                 .dev_id         = "dev:f4",
 450                 .clk            = &ref24_clk,
 451         }, {    /* CLCD */
 452                 .dev_id         = "dev:20",
 453                 .clk            = &osc4_clk,
 454         }
 455 };
 456
 457 /*
 458  * CLCD support.
 459  */
 460 #define SYS_CLCD_MODE_MASK      (3 << 0)
 461 #define SYS_CLCD_MODE_888       (0 << 0)
 462 #define SYS_CLCD_MODE_5551      (1 << 0)
 463 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 464 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 465 #define SYS_CLCD_NLCDIOON       (1 << 2)
 466 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 467 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 468 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 469 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 470 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 471 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 472 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 473 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 474
 475 static struct clcd_panel vga = {
 476         .mode           = {
 477                 .name           = "VGA",
 478                 .refresh        = 60,
 479                 .xres           = 640,
 480                 .yres           = 480,
 481                 .pixclock       = 39721,
 482                 .left_margin    = 40,
 483                 .right_margin   = 24,
 484                 .upper_margin   = 32,
 485                 .lower_margin   = 11,
 486                 .hsync_len      = 96,
 487                 .vsync_len      = 2,
 488                 .sync           = 0,
 489                 .vmode          = FB_VMODE_NONINTERLACED,
 490         },
 491         .width          = -1,
 492         .height         = -1,
 493         .tim2           = TIM2_BCD | TIM2_IPC,
 494         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 495         .bpp            = 16,
 496 };
 497
 498 static struct clcd_panel sanyo_3_8_in = {
 499         .mode           = {
 500                 .name           = "Sanyo QVGA",
 501                 .refresh        = 116,
 502                 .xres           = 320,
 503                 .yres           = 240,
 504                 .pixclock       = 100000,
 505                 .left_margin    = 6,
 506                 .right_margin   = 6,
 507                 .upper_margin   = 5,
 508                 .lower_margin   = 5,
 509                 .hsync_len      = 6,
 510                 .vsync_len      = 6,
 511                 .sync           = 0,
 512                 .vmode          = FB_VMODE_NONINTERLACED,
 513         },
 514         .width          = -1,
 515         .height         = -1,
 516         .tim2           = TIM2_BCD,
 517         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 518         .bpp            = 16,
 519 };
 520
 521 static struct clcd_panel sanyo_2_5_in = {
 522         .mode           = {
 523                 .name           = "Sanyo QVGA Portrait",
 524                 .refresh        = 116,
 525                 .xres           = 240,
 526                 .yres           = 320,
 527                 .pixclock       = 100000,
 528                 .left_margin    = 20,
 529                 .right_margin   = 10,
 530                 .upper_margin   = 2,
 531                 .lower_margin   = 2,
 532                 .hsync_len      = 10,
 533                 .vsync_len      = 2,
 534                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 535                 .vmode          = FB_VMODE_NONINTERLACED,
 536         },
 537         .width          = -1,
 538         .height         = -1,
 539         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 540         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 541         .bpp            = 16,
 542 };
 543
 544 static struct clcd_panel epson_2_2_in = {
 545         .mode           = {
 546                 .name           = "Epson QCIF",
 547                 .refresh        = 390,
 548                 .xres           = 176,
 549                 .yres           = 220,
 550                 .pixclock       = 62500,
 551                 .left_margin    = 3,
 552                 .right_margin   = 2,
 553                 .upper_margin   = 1,
 554                 .lower_margin   = 0,
 555                 .hsync_len      = 3,
 556                 .vsync_len      = 2,
 557                 .sync           = 0,
 558                 .vmode          = FB_VMODE_NONINTERLACED,
 559         },
 560         .width          = -1,
 561         .height         = -1,
 562         .tim2           = TIM2_BCD | TIM2_IPC,
 563         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 564         .bpp            = 16,
 565 };
 566
 567 /*
 568  * Detect which LCD panel is connected, and return the appropriate
 569  * clcd_panel structure.  Note: we do not have any information on
 570  * the required timings for the 8.4in panel, so we presently assume
 571  * VGA timings.
 572  */
 573 static struct clcd_panel *versatile_clcd_panel(void)
 574 {
 575         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 576         struct clcd_panel *panel = &vga;
 577         u32 val;
 578
 579         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 580         if (val == SYS_CLCD_ID_SANYO_3_8)
 581                 panel = &sanyo_3_8_in;
 582         else if (val == SYS_CLCD_ID_SANYO_2_5)
 583                 panel = &sanyo_2_5_in;
 584         else if (val == SYS_CLCD_ID_EPSON_2_2)
 585                 panel = &epson_2_2_in;
 586         else if (val == SYS_CLCD_ID_VGA)
 587                 panel = &vga;
 588         else {
 589                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 590                         val);
 591                 panel = &vga;
 592         }
 593
 594         return panel;
 595 }
 596
 597 /*
 598  * Disable all display connectors on the interface module.
 599  */
 600 static void versatile_clcd_disable(struct clcd_fb *fb)
 601 {
 602         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 603         u32 val;
 604
 605         val = readl(sys_clcd);
 606         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 607         writel(val, sys_clcd);
 608
 609 #ifdef CONFIG_MACH_VERSATILE_AB
 610         /*
 611          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 612          */
 613         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 614                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 615                 unsigned long ctrl;
 616
 617                 ctrl = readl(versatile_ib2_ctrl);
 618                 ctrl &= ~0x01;
 619                 writel(ctrl, versatile_ib2_ctrl);
 620         }
 621 #endif
 622 }
 623
 624 /*
 625  * Enable the relevant connector on the interface module.
 626  */
 627 static void versatile_clcd_enable(struct clcd_fb *fb)
 628 {
 629         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 630         u32 val;
 631
 632         val = readl(sys_clcd);
 633         val &= ~SYS_CLCD_MODE_MASK;
 634
 635         switch (fb->fb.var.green.length) {
 636         case 5:
 637                 val |= SYS_CLCD_MODE_5551;
 638                 break;
 639         case 6:
 640                 val |= SYS_CLCD_MODE_565_RLSB;
 641                 break;
 642         case 8:
 643                 val |= SYS_CLCD_MODE_888;
 644                 break;
 645         }
 646
 647         /*
 648          * Set the MUX
 649          */
 650         writel(val, sys_clcd);
 651
 652         /*
 653          * And now enable the PSUs
 654          */
 655         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 656         writel(val, sys_clcd);
 657
 658 #ifdef CONFIG_MACH_VERSATILE_AB
 659         /*
 660          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 661          */
 662         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 663                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 664                 unsigned long ctrl;
 665
 666                 ctrl = readl(versatile_ib2_ctrl);
 667                 ctrl |= 0x01;
 668                 writel(ctrl, versatile_ib2_ctrl);
 669         }
 670 #endif
 671 }
 672
 673 static unsigned long framesize = SZ_1M;
 674
 675 static int versatile_clcd_setup(struct clcd_fb *fb)
 676 {
 677         dma_addr_t dma;
 678
 679         fb->panel               = versatile_clcd_panel();
 680
 681         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 682                                                     &dma, GFP_KERNEL);
 683         if (!fb->fb.screen_base) {
 684                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 685                 return -ENOMEM;
 686         }
 687
 688         fb->fb.fix.smem_start   = dma;
 689         fb->fb.fix.smem_len     = framesize;
 690
 691         return 0;
 692 }
 693
 694 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 695 {
 696         return dma_mmap_writecombine(&fb->dev->dev, vma,
 697                                      fb->fb.screen_base,
 698                                      fb->fb.fix.smem_start,
 699                                      fb->fb.fix.smem_len);
 700 }
 701
 702 static void versatile_clcd_remove(struct clcd_fb *fb)
 703 {
 704         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 705                               fb->fb.screen_base, fb->fb.fix.smem_start);
 706 }
 707
 708 static struct clcd_board clcd_plat_data = {
 709         .name           = "Versatile",
 710         .check          = clcdfb_check,
 711         .decode         = clcdfb_decode,
 712         .disable        = versatile_clcd_disable,
 713         .enable         = versatile_clcd_enable,
 714         .setup          = versatile_clcd_setup,
 715         .mmap           = versatile_clcd_mmap,
 716         .remove         = versatile_clcd_remove,
 717 };
 718
 719 static struct pl061_platform_data gpio0_plat_data = {
 720         .gpio_base      = 0,
 721         .irq_base       = IRQ_GPIO0_START,
 722 };
 723
 724 static struct pl061_platform_data gpio1_plat_data = {
 725         .gpio_base      = 8,
 726         .irq_base       = IRQ_GPIO1_START,
 727 };
 728
 729 static struct pl022_ssp_controller ssp0_plat_data = {
 730         .bus_id = 0,
 731         .enable_dma = 0,
 732         .num_chipselect = 1,
 733 };
 734
 735 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 736 #define AACI_DMA        { 0x80, 0x81 }
 737 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 738 #define MMCI0_DMA       { 0x84, 0 }
 739 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 740 #define KMI0_DMA        { 0, 0 }
 741 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 742 #define KMI1_DMA        { 0, 0 }
 743
 744 /*
 745  * These devices are connected directly to the multi-layer AHB switch
 746  */
 747 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 748 #define SMC_DMA         { 0, 0 }
 749 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 750 #define MPMC_DMA        { 0, 0 }
 751 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 752 #define CLCD_DMA        { 0, 0 }
 753 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 754 #define DMAC_DMA        { 0, 0 }
 755
 756 /*
 757  * These devices are connected via the core APB bridge
 758  */
 759 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 760 #define SCTL_DMA        { 0, 0 }
 761 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 762 #define WATCHDOG_DMA    { 0, 0 }
 763 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 764 #define GPIO0_DMA       { 0, 0 }
 765 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 766 #define GPIO1_DMA       { 0, 0 }
 767 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 768 #define RTC_DMA         { 0, 0 }
 769
 770 /*
 771  * These devices are connected via the DMA APB bridge
 772  */
 773 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 774 #define SCI_DMA         { 7, 6 }
 775 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 776 #define UART0_DMA       { 15, 14 }
 777 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 778 #define UART1_DMA       { 13, 12 }
 779 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 780 #define UART2_DMA       { 11, 10 }
 781 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 782 #define SSP_DMA         { 9, 8 }
 783
 784 /* FPGA Primecells */
 785 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 786 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 787 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 788 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 789
 790 /* DevChip Primecells */
 791 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 792 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 793 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 794 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 795 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 796 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 797 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 798 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 799 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 800 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 801 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 802 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 803 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 804 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 805
 806 static struct amba_device *amba_devs[] __initdata = {
 807         &dmac_device,
 808         &uart0_device,
 809         &uart1_device,
 810         &uart2_device,
 811         &smc_device,
 812         &mpmc_device,
 813         &clcd_device,
 814         &sctl_device,
 815         &wdog_device,
 816         &gpio0_device,
 817         &gpio1_device,
 818         &rtc_device,
 819         &sci0_device,
 820         &ssp0_device,
 821         &aaci_device,
 822         &mmc0_device,
 823         &kmi0_device,
 824         &kmi1_device,
 825 };
 826
 827 #ifdef CONFIG_LEDS
 828 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 829
 830 static void versatile_leds_event(led_event_t ledevt)
 831 {
 832         unsigned long flags;
 833         u32 val;
 834
 835         local_irq_save(flags);
 836         val = readl(VA_LEDS_BASE);
 837
 838         switch (ledevt) {
 839         case led_idle_start:
 840                 val = val & ~VERSATILE_SYS_LED0;
 841                 break;
 842
 843         case led_idle_end:
 844                 val = val | VERSATILE_SYS_LED0;
 845                 break;
 846
 847         case led_timer:
 848                 val = val ^ VERSATILE_SYS_LED1;
 849                 break;
 850
 851         case led_halted:
 852                 val = 0;
 853                 break;
 854
 855         default:
 856                 break;
 857         }
 858
 859         writel(val, VA_LEDS_BASE);
 860         local_irq_restore(flags);
 861 }
 862 #endif  /* CONFIG_LEDS */
 863
 864 void __init versatile_init(void)
 865 {
 866         int i;
 867
 868         osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
 869
 870         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 871
 872         platform_device_register(&versatile_flash_device);
 873         platform_device_register(&versatile_i2c_device);
 874         platform_device_register(&smc91x_device);
 875         platform_device_register(&char_lcd_device);
 876
 877         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 878                 struct amba_device *d = amba_devs[i];
 879                 amba_device_register(d, &iomem_resource);
 880         }
 881
 882 #ifdef CONFIG_LEDS
 883         leds_event = versatile_leds_event;
 884 #endif
 885 }
 886
 887 /*
 888  * Where is the timer (VA)?
 889  */
 890 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 891 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 892 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 893 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 894
 895 /*
 896  * Set up timer interrupt, and return the current time in seconds.
 897  */
 898 static void __init versatile_timer_init(void)
 899 {
 900         u32 val;
 901
 902         /*
 903          * set clock frequency:
 904          *      VERSATILE_REFCLK is 32KHz
 905          *      VERSATILE_TIMCLK is 1MHz
 906          */
 907         val = readl(__io_address(VERSATILE_SCTL_BASE));
 908         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 909                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 910                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 911                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 912                __io_address(VERSATILE_SCTL_BASE));
 913
 914         /*
 915          * Initialise to a known state (all timers off)
 916          */
 917         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 918         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 919         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 920         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 921
 922         sp804_clocksource_init(TIMER3_VA_BASE);
 923         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
 924 }
 925
 926 struct sys_timer versatile_timer = {
 927         .init           = versatile_timer_init,
 928 };
 929