2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/amba/pl061.h>
30 #include <linux/amba/mmci.h>
31 #include <linux/amba/pl022.h>
33 #include <linux/gfp.h>
34 #include <linux/clkdev.h>
36 #include <asm/system.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/hardware/icst.h>
41 #include <asm/hardware/vic.h>
42 #include <asm/mach-types.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/flash.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/map.h>
49 #include <mach/hardware.h>
50 #include <mach/platform.h>
51 #include <asm/hardware/timer-sp.h>
53 #include <plat/clcd.h>
54 #include <plat/fpga-irq.h>
55 #include <plat/sched_clock.h>
60 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
63 * Setup a VA for the Versatile Vectored Interrupt Controller.
65 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
66 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
68 static struct fpga_irq_data sic_irq
= {
70 .irq_start
= IRQ_SIC_START
,
75 #define IRQ_MMCI0A IRQ_VICSOURCE22
76 #define IRQ_AACI IRQ_VICSOURCE24
77 #define IRQ_ETH IRQ_VICSOURCE25
78 #define PIC_MASK 0xFFD00000
80 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
81 #define IRQ_AACI IRQ_SIC_AACI
82 #define IRQ_ETH IRQ_SIC_ETH
86 void __init
versatile_init_irq(void)
88 vic_init(VA_VIC_BASE
, IRQ_VIC_START
, ~0, 0);
90 writel(~0, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
92 fpga_irq_init(IRQ_VICSOURCE31
, ~PIC_MASK
, &sic_irq
);
95 * Interrupts on secondary controller from 0 to 8 are routed to
97 * Interrupts from 21 to 31 are routed directly to the VIC on
98 * the corresponding number on primary controller. This is controlled
99 * by setting PIC_ENABLEx.
101 writel(PIC_MASK
, VA_SIC_BASE
+ SIC_INT_PIC_ENABLE
);
104 static struct map_desc versatile_io_desc
[] __initdata
= {
106 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE
),
107 .pfn
= __phys_to_pfn(VERSATILE_SYS_BASE
),
111 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE
),
112 .pfn
= __phys_to_pfn(VERSATILE_SIC_BASE
),
116 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE
),
117 .pfn
= __phys_to_pfn(VERSATILE_VIC_BASE
),
121 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE
),
122 .pfn
= __phys_to_pfn(VERSATILE_SCTL_BASE
),
126 #ifdef CONFIG_MACH_VERSATILE_AB
128 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE
),
129 .pfn
= __phys_to_pfn(VERSATILE_GPIO0_BASE
),
133 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE
),
134 .pfn
= __phys_to_pfn(VERSATILE_IB2_BASE
),
139 #ifdef CONFIG_DEBUG_LL
141 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE
),
142 .pfn
= __phys_to_pfn(VERSATILE_UART0_BASE
),
149 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE
),
150 .pfn
= __phys_to_pfn(VERSATILE_PCI_CORE_BASE
),
154 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE
,
155 .pfn
= __phys_to_pfn(VERSATILE_PCI_BASE
),
156 .length
= VERSATILE_PCI_BASE_SIZE
,
159 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE
,
160 .pfn
= __phys_to_pfn(VERSATILE_PCI_CFG_BASE
),
161 .length
= VERSATILE_PCI_CFG_BASE_SIZE
,
166 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0
,
167 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0
),
171 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1
,
172 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1
),
176 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2
,
177 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2
),
185 void __init
versatile_map_io(void)
187 iotable_init(versatile_io_desc
, ARRAY_SIZE(versatile_io_desc
));
191 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
193 static int versatile_flash_init(void)
197 val
= __raw_readl(VERSATILE_FLASHCTRL
);
198 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
199 __raw_writel(val
, VERSATILE_FLASHCTRL
);
204 static void versatile_flash_exit(void)
208 val
= __raw_readl(VERSATILE_FLASHCTRL
);
209 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
210 __raw_writel(val
, VERSATILE_FLASHCTRL
);
213 static void versatile_flash_set_vpp(int on
)
217 val
= __raw_readl(VERSATILE_FLASHCTRL
);
219 val
|= VERSATILE_FLASHPROG_FLVPPEN
;
221 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
222 __raw_writel(val
, VERSATILE_FLASHCTRL
);
225 static struct flash_platform_data versatile_flash_data
= {
226 .map_name
= "cfi_probe",
228 .init
= versatile_flash_init
,
229 .exit
= versatile_flash_exit
,
230 .set_vpp
= versatile_flash_set_vpp
,
233 static struct resource versatile_flash_resource
= {
234 .start
= VERSATILE_FLASH_BASE
,
235 .end
= VERSATILE_FLASH_BASE
+ VERSATILE_FLASH_SIZE
- 1,
236 .flags
= IORESOURCE_MEM
,
239 static struct platform_device versatile_flash_device
= {
243 .platform_data
= &versatile_flash_data
,
246 .resource
= &versatile_flash_resource
,
249 static struct resource smc91x_resources
[] = {
251 .start
= VERSATILE_ETH_BASE
,
252 .end
= VERSATILE_ETH_BASE
+ SZ_64K
- 1,
253 .flags
= IORESOURCE_MEM
,
258 .flags
= IORESOURCE_IRQ
,
262 static struct platform_device smc91x_device
= {
265 .num_resources
= ARRAY_SIZE(smc91x_resources
),
266 .resource
= smc91x_resources
,
269 static struct resource versatile_i2c_resource
= {
270 .start
= VERSATILE_I2C_BASE
,
271 .end
= VERSATILE_I2C_BASE
+ SZ_4K
- 1,
272 .flags
= IORESOURCE_MEM
,
275 static struct platform_device versatile_i2c_device
= {
276 .name
= "versatile-i2c",
279 .resource
= &versatile_i2c_resource
,
282 static struct i2c_board_info versatile_i2c_board_info
[] = {
284 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
288 static int __init
versatile_i2c_init(void)
290 return i2c_register_board_info(0, versatile_i2c_board_info
,
291 ARRAY_SIZE(versatile_i2c_board_info
));
293 arch_initcall(versatile_i2c_init
);
295 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
297 unsigned int mmc_status(struct device
*dev
)
299 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
302 if (adev
->res
.start
== VERSATILE_MMCI0_BASE
)
307 return readl(VERSATILE_SYSMCI
) & mask
;
310 static struct mmci_platform_data mmc0_plat_data
= {
311 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
312 .status
= mmc_status
,
317 static struct resource chalcd_resources
[] = {
319 .start
= VERSATILE_CHAR_LCD_BASE
,
320 .end
= (VERSATILE_CHAR_LCD_BASE
+ SZ_4K
- 1),
321 .flags
= IORESOURCE_MEM
,
325 static struct platform_device char_lcd_device
= {
326 .name
= "arm-charlcd",
328 .num_resources
= ARRAY_SIZE(char_lcd_resources
),
329 .resource
= char_lcd_resources
,
335 static const struct icst_params versatile_oscvco_params
= {
337 .vco_max
= ICST307_VCO_MAX
,
338 .vco_min
= ICST307_VCO_MIN
,
343 .s2div
= icst307_s2div
,
344 .idx2s
= icst307_idx2s
,
347 static void versatile_oscvco_set(struct clk
*clk
, struct icst_vco vco
)
349 void __iomem
*sys_lock
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_LOCK_OFFSET
;
352 val
= readl(clk
->vcoreg
) & ~0x7ffff;
353 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
355 writel(0xa05f, sys_lock
);
356 writel(val
, clk
->vcoreg
);
360 static const struct clk_ops osc4_clk_ops
= {
361 .round
= icst_clk_round
,
363 .setvco
= versatile_oscvco_set
,
366 static struct clk osc4_clk
= {
367 .ops
= &osc4_clk_ops
,
368 .params
= &versatile_oscvco_params
,
372 * These are fixed clocks.
374 static struct clk ref24_clk
= {
378 static struct clk dummy_apb_pclk
;
380 static struct clk_lookup lookups
[] = {
381 { /* AMBA bus clock */
382 .con_id
= "apb_pclk",
383 .clk
= &dummy_apb_pclk
,
420 #define SYS_CLCD_MODE_MASK (3 << 0)
421 #define SYS_CLCD_MODE_888 (0 << 0)
422 #define SYS_CLCD_MODE_5551 (1 << 0)
423 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
424 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
425 #define SYS_CLCD_NLCDIOON (1 << 2)
426 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
427 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
428 #define SYS_CLCD_ID_MASK (0x1f << 8)
429 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
430 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
431 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
432 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
433 #define SYS_CLCD_ID_VGA (0x1f << 8)
435 static bool is_sanyo_2_5_lcd
;
438 * Disable all display connectors on the interface module.
440 static void versatile_clcd_disable(struct clcd_fb
*fb
)
442 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
445 val
= readl(sys_clcd
);
446 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
447 writel(val
, sys_clcd
);
449 #ifdef CONFIG_MACH_VERSATILE_AB
451 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
453 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd
) {
454 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
457 ctrl
= readl(versatile_ib2_ctrl
);
459 writel(ctrl
, versatile_ib2_ctrl
);
465 * Enable the relevant connector on the interface module.
467 static void versatile_clcd_enable(struct clcd_fb
*fb
)
469 struct fb_var_screeninfo
*var
= &fb
->fb
.var
;
470 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
473 val
= readl(sys_clcd
);
474 val
&= ~SYS_CLCD_MODE_MASK
;
476 switch (var
->green
.length
) {
478 val
|= SYS_CLCD_MODE_5551
;
481 if (var
->red
.offset
== 0)
482 val
|= SYS_CLCD_MODE_565_RLSB
;
484 val
|= SYS_CLCD_MODE_565_BLSB
;
487 val
|= SYS_CLCD_MODE_888
;
494 writel(val
, sys_clcd
);
497 * And now enable the PSUs
499 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
500 writel(val
, sys_clcd
);
502 #ifdef CONFIG_MACH_VERSATILE_AB
504 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
506 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd
) {
507 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
510 ctrl
= readl(versatile_ib2_ctrl
);
512 writel(ctrl
, versatile_ib2_ctrl
);
518 * Detect which LCD panel is connected, and return the appropriate
519 * clcd_panel structure. Note: we do not have any information on
520 * the required timings for the 8.4in panel, so we presently assume
523 static int versatile_clcd_setup(struct clcd_fb
*fb
)
525 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
526 const char *panel_name
;
529 is_sanyo_2_5_lcd
= false;
531 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
532 if (val
== SYS_CLCD_ID_SANYO_3_8
)
533 panel_name
= "Sanyo TM38QV67A02A";
534 else if (val
== SYS_CLCD_ID_SANYO_2_5
) {
535 panel_name
= "Sanyo QVGA Portrait";
536 is_sanyo_2_5_lcd
= true;
537 } else if (val
== SYS_CLCD_ID_EPSON_2_2
)
538 panel_name
= "Epson L2F50113T00";
539 else if (val
== SYS_CLCD_ID_VGA
)
542 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
547 fb
->panel
= versatile_clcd_get_panel(panel_name
);
551 return versatile_clcd_setup_dma(fb
, SZ_1M
);
554 static void versatile_clcd_decode(struct clcd_fb
*fb
, struct clcd_regs
*regs
)
556 clcdfb_decode(fb
, regs
);
558 /* Always clear BGR for RGB565: we do the routing externally */
559 if (fb
->fb
.var
.green
.length
== 6)
560 regs
->cntl
&= ~CNTL_BGR
;
563 static struct clcd_board clcd_plat_data
= {
565 .caps
= CLCD_CAP_5551
| CLCD_CAP_565
| CLCD_CAP_888
,
566 .check
= clcdfb_check
,
567 .decode
= versatile_clcd_decode
,
568 .disable
= versatile_clcd_disable
,
569 .enable
= versatile_clcd_enable
,
570 .setup
= versatile_clcd_setup
,
571 .mmap
= versatile_clcd_mmap_dma
,
572 .remove
= versatile_clcd_remove_dma
,
575 static struct pl061_platform_data gpio0_plat_data
= {
577 .irq_base
= IRQ_GPIO0_START
,
580 static struct pl061_platform_data gpio1_plat_data
= {
582 .irq_base
= IRQ_GPIO1_START
,
585 static struct pl022_ssp_controller ssp0_plat_data
= {
591 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
592 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
593 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
594 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
597 * These devices are connected directly to the multi-layer AHB switch
599 #define SMC_IRQ { NO_IRQ, NO_IRQ }
600 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
601 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
602 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
605 * These devices are connected via the core APB bridge
607 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
608 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
609 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
610 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
611 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
614 * These devices are connected via the DMA APB bridge
616 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
617 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
618 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
619 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
620 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
622 /* FPGA Primecells */
623 AMBA_DEVICE(aaci
, "fpga:04", AACI
, NULL
);
624 AMBA_DEVICE(mmc0
, "fpga:05", MMCI0
, &mmc0_plat_data
);
625 AMBA_DEVICE(kmi0
, "fpga:06", KMI0
, NULL
);
626 AMBA_DEVICE(kmi1
, "fpga:07", KMI1
, NULL
);
628 /* DevChip Primecells */
629 AMBA_DEVICE(smc
, "dev:00", SMC
, NULL
);
630 AMBA_DEVICE(mpmc
, "dev:10", MPMC
, NULL
);
631 AMBA_DEVICE(clcd
, "dev:20", CLCD
, &clcd_plat_data
);
632 AMBA_DEVICE(dmac
, "dev:30", DMAC
, NULL
);
633 AMBA_DEVICE(sctl
, "dev:e0", SCTL
, NULL
);
634 AMBA_DEVICE(wdog
, "dev:e1", WATCHDOG
, NULL
);
635 AMBA_DEVICE(gpio0
, "dev:e4", GPIO0
, &gpio0_plat_data
);
636 AMBA_DEVICE(gpio1
, "dev:e5", GPIO1
, &gpio1_plat_data
);
637 AMBA_DEVICE(rtc
, "dev:e8", RTC
, NULL
);
638 AMBA_DEVICE(sci0
, "dev:f0", SCI
, NULL
);
639 AMBA_DEVICE(uart0
, "dev:f1", UART0
, NULL
);
640 AMBA_DEVICE(uart1
, "dev:f2", UART1
, NULL
);
641 AMBA_DEVICE(uart2
, "dev:f3", UART2
, NULL
);
642 AMBA_DEVICE(ssp0
, "dev:f4", SSP
, &ssp0_plat_data
);
644 static struct amba_device
*amba_devs
[] __initdata
= {
666 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
668 static void versatile_leds_event(led_event_t ledevt
)
673 local_irq_save(flags
);
674 val
= readl(VA_LEDS_BASE
);
678 val
= val
& ~VERSATILE_SYS_LED0
;
682 val
= val
| VERSATILE_SYS_LED0
;
686 val
= val
^ VERSATILE_SYS_LED1
;
697 writel(val
, VA_LEDS_BASE
);
698 local_irq_restore(flags
);
700 #endif /* CONFIG_LEDS */
702 /* Early initializations */
703 void __init
versatile_init_early(void)
705 void __iomem
*sys
= __io_address(VERSATILE_SYS_BASE
);
707 osc4_clk
.vcoreg
= sys
+ VERSATILE_SYS_OSCCLCD_OFFSET
;
708 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));
710 versatile_sched_clock_init(sys
+ VERSATILE_SYS_24MHz_OFFSET
, 24000000);
713 void __init
versatile_init(void)
717 platform_device_register(&versatile_flash_device
);
718 platform_device_register(&versatile_i2c_device
);
719 platform_device_register(&smc91x_device
);
720 platform_device_register(&char_lcd_device
);
722 for (i
= 0; i
< ARRAY_SIZE(amba_devs
); i
++) {
723 struct amba_device
*d
= amba_devs
[i
];
724 amba_device_register(d
, &iomem_resource
);
728 leds_event
= versatile_leds_event
;
733 * Where is the timer (VA)?
735 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
736 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
737 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
738 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
741 * Set up timer interrupt, and return the current time in seconds.
743 static void __init
versatile_timer_init(void)
748 * set clock frequency:
749 * VERSATILE_REFCLK is 32KHz
750 * VERSATILE_TIMCLK is 1MHz
752 val
= readl(__io_address(VERSATILE_SCTL_BASE
));
753 writel((VERSATILE_TIMCLK
<< VERSATILE_TIMER1_EnSel
) |
754 (VERSATILE_TIMCLK
<< VERSATILE_TIMER2_EnSel
) |
755 (VERSATILE_TIMCLK
<< VERSATILE_TIMER3_EnSel
) |
756 (VERSATILE_TIMCLK
<< VERSATILE_TIMER4_EnSel
) | val
,
757 __io_address(VERSATILE_SCTL_BASE
));
760 * Initialise to a known state (all timers off)
762 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
763 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
764 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
765 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
767 sp804_clocksource_init(TIMER3_VA_BASE
);
768 sp804_clockevents_init(TIMER0_VA_BASE
, IRQ_TIMERINT0_1
);
771 struct sys_timer versatile_timer
= {
772 .init
= versatile_timer_init
,