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Merge branch 'tegra/cleanup' into next/cleanup
[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-versatile / core.c
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/irqdomain.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/clcd.h>
32 #include <linux/amba/pl061.h>
33 #include <linux/amba/mmci.h>
34 #include <linux/amba/pl022.h>
35 #include <linux/io.h>
36 #include <linux/gfp.h>
37 #include <linux/clkdev.h>
38 #include <linux/mtd/physmap.h>
39
40 #include <asm/system.h>
41 #include <asm/irq.h>
42 #include <asm/leds.h>
43 #include <asm/hardware/arm_timer.h>
44 #include <asm/hardware/icst.h>
45 #include <asm/hardware/vic.h>
46 #include <asm/mach-types.h>
47
48 #include <asm/mach/arch.h>
49 #include <asm/mach/irq.h>
50 #include <asm/mach/time.h>
51 #include <asm/mach/map.h>
52 #include <mach/hardware.h>
53 #include <mach/platform.h>
54 #include <asm/hardware/timer-sp.h>
55
56 #include <plat/clcd.h>
57 #include <plat/fpga-irq.h>
58 #include <plat/sched_clock.h>
59
60 #include "core.h"
61
62 /*
63 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
64 * is the (PA >> 12).
65 *
66 * Setup a VA for the Versatile Vectored Interrupt Controller.
67 */
68 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
69 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
70
71 static struct fpga_irq_data sic_irq = {
72 .base = VA_SIC_BASE,
73 .irq_start = IRQ_SIC_START,
74 .chip.name = "SIC",
75 };
76
77 #if 1
78 #define IRQ_MMCI0A IRQ_VICSOURCE22
79 #define IRQ_AACI IRQ_VICSOURCE24
80 #define IRQ_ETH IRQ_VICSOURCE25
81 #define PIC_MASK 0xFFD00000
82 #else
83 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
84 #define IRQ_AACI IRQ_SIC_AACI
85 #define IRQ_ETH IRQ_SIC_ETH
86 #define PIC_MASK 0
87 #endif
88
89 /* Lookup table for finding a DT node that represents the vic instance */
90 static const struct of_device_id vic_of_match[] __initconst = {
91 { .compatible = "arm,versatile-vic", },
92 {}
93 };
94
95 static const struct of_device_id sic_of_match[] __initconst = {
96 { .compatible = "arm,versatile-sic", },
97 {}
98 };
99
100 void __init versatile_init_irq(void)
101 {
102 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
103 irq_domain_generate_simple(vic_of_match, VERSATILE_VIC_BASE, IRQ_VIC_START);
104
105 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
106
107 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
108 irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
109
110 /*
111 * Interrupts on secondary controller from 0 to 8 are routed to
112 * source 31 on PIC.
113 * Interrupts from 21 to 31 are routed directly to the VIC on
114 * the corresponding number on primary controller. This is controlled
115 * by setting PIC_ENABLEx.
116 */
117 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
118 }
119
120 static struct map_desc versatile_io_desc[] __initdata = {
121 {
122 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
123 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
124 .length = SZ_4K,
125 .type = MT_DEVICE
126 }, {
127 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
128 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
129 .length = SZ_4K,
130 .type = MT_DEVICE
131 }, {
132 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
133 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
134 .length = SZ_4K,
135 .type = MT_DEVICE
136 }, {
137 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
138 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
139 .length = SZ_4K * 9,
140 .type = MT_DEVICE
141 },
142 #ifdef CONFIG_MACH_VERSATILE_AB
143 {
144 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
145 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
146 .length = SZ_64M,
147 .type = MT_DEVICE
148 },
149 #endif
150 #ifdef CONFIG_DEBUG_LL
151 {
152 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
153 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
154 .length = SZ_4K,
155 .type = MT_DEVICE
156 },
157 #endif
158 #ifdef CONFIG_PCI
159 {
160 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
161 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
162 .length = SZ_4K,
163 .type = MT_DEVICE
164 }, {
165 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
166 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
167 .length = VERSATILE_PCI_BASE_SIZE,
168 .type = MT_DEVICE
169 }, {
170 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
171 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
172 .length = VERSATILE_PCI_CFG_BASE_SIZE,
173 .type = MT_DEVICE
174 },
175 #if 0
176 {
177 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
178 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
179 .length = SZ_16M,
180 .type = MT_DEVICE
181 }, {
182 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
183 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
184 .length = SZ_16M,
185 .type = MT_DEVICE
186 }, {
187 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
188 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
189 .length = SZ_16M,
190 .type = MT_DEVICE
191 },
192 #endif
193 #endif
194 };
195
196 void __init versatile_map_io(void)
197 {
198 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
199 }
200
201
202 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
203
204 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
205 {
206 u32 val;
207
208 val = __raw_readl(VERSATILE_FLASHCTRL);
209 if (on)
210 val |= VERSATILE_FLASHPROG_FLVPPEN;
211 else
212 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
213 __raw_writel(val, VERSATILE_FLASHCTRL);
214 }
215
216 static struct physmap_flash_data versatile_flash_data = {
217 .width = 4,
218 .set_vpp = versatile_flash_set_vpp,
219 };
220
221 static struct resource versatile_flash_resource = {
222 .start = VERSATILE_FLASH_BASE,
223 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
224 .flags = IORESOURCE_MEM,
225 };
226
227 static struct platform_device versatile_flash_device = {
228 .name = "physmap-flash",
229 .id = 0,
230 .dev = {
231 .platform_data = &versatile_flash_data,
232 },
233 .num_resources = 1,
234 .resource = &versatile_flash_resource,
235 };
236
237 static struct resource smc91x_resources[] = {
238 [0] = {
239 .start = VERSATILE_ETH_BASE,
240 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
241 .flags = IORESOURCE_MEM,
242 },
243 [1] = {
244 .start = IRQ_ETH,
245 .end = IRQ_ETH,
246 .flags = IORESOURCE_IRQ,
247 },
248 };
249
250 static struct platform_device smc91x_device = {
251 .name = "smc91x",
252 .id = 0,
253 .num_resources = ARRAY_SIZE(smc91x_resources),
254 .resource = smc91x_resources,
255 };
256
257 static struct resource versatile_i2c_resource = {
258 .start = VERSATILE_I2C_BASE,
259 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
260 .flags = IORESOURCE_MEM,
261 };
262
263 static struct platform_device versatile_i2c_device = {
264 .name = "versatile-i2c",
265 .id = 0,
266 .num_resources = 1,
267 .resource = &versatile_i2c_resource,
268 };
269
270 static struct i2c_board_info versatile_i2c_board_info[] = {
271 {
272 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
273 },
274 };
275
276 static int __init versatile_i2c_init(void)
277 {
278 return i2c_register_board_info(0, versatile_i2c_board_info,
279 ARRAY_SIZE(versatile_i2c_board_info));
280 }
281 arch_initcall(versatile_i2c_init);
282
283 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
284
285 unsigned int mmc_status(struct device *dev)
286 {
287 struct amba_device *adev = container_of(dev, struct amba_device, dev);
288 u32 mask;
289
290 if (adev->res.start == VERSATILE_MMCI0_BASE)
291 mask = 1;
292 else
293 mask = 2;
294
295 return readl(VERSATILE_SYSMCI) & mask;
296 }
297
298 static struct mmci_platform_data mmc0_plat_data = {
299 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
300 .status = mmc_status,
301 .gpio_wp = -1,
302 .gpio_cd = -1,
303 };
304
305 static struct resource char_lcd_resources[] = {
306 {
307 .start = VERSATILE_CHAR_LCD_BASE,
308 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
309 .flags = IORESOURCE_MEM,
310 },
311 };
312
313 static struct platform_device char_lcd_device = {
314 .name = "arm-charlcd",
315 .id = -1,
316 .num_resources = ARRAY_SIZE(char_lcd_resources),
317 .resource = char_lcd_resources,
318 };
319
320 /*
321 * Clock handling
322 */
323 static const struct icst_params versatile_oscvco_params = {
324 .ref = 24000000,
325 .vco_max = ICST307_VCO_MAX,
326 .vco_min = ICST307_VCO_MIN,
327 .vd_min = 4 + 8,
328 .vd_max = 511 + 8,
329 .rd_min = 1 + 2,
330 .rd_max = 127 + 2,
331 .s2div = icst307_s2div,
332 .idx2s = icst307_idx2s,
333 };
334
335 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
336 {
337 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
338 u32 val;
339
340 val = readl(clk->vcoreg) & ~0x7ffff;
341 val |= vco.v | (vco.r << 9) | (vco.s << 16);
342
343 writel(0xa05f, sys_lock);
344 writel(val, clk->vcoreg);
345 writel(0, sys_lock);
346 }
347
348 static const struct clk_ops osc4_clk_ops = {
349 .round = icst_clk_round,
350 .set = icst_clk_set,
351 .setvco = versatile_oscvco_set,
352 };
353
354 static struct clk osc4_clk = {
355 .ops = &osc4_clk_ops,
356 .params = &versatile_oscvco_params,
357 };
358
359 /*
360 * These are fixed clocks.
361 */
362 static struct clk ref24_clk = {
363 .rate = 24000000,
364 };
365
366 static struct clk sp804_clk = {
367 .rate = 1000000,
368 };
369
370 static struct clk dummy_apb_pclk;
371
372 static struct clk_lookup lookups[] = {
373 { /* AMBA bus clock */
374 .con_id = "apb_pclk",
375 .clk = &dummy_apb_pclk,
376 }, { /* UART0 */
377 .dev_id = "dev:f1",
378 .clk = &ref24_clk,
379 }, { /* UART1 */
380 .dev_id = "dev:f2",
381 .clk = &ref24_clk,
382 }, { /* UART2 */
383 .dev_id = "dev:f3",
384 .clk = &ref24_clk,
385 }, { /* UART3 */
386 .dev_id = "fpga:09",
387 .clk = &ref24_clk,
388 }, { /* KMI0 */
389 .dev_id = "fpga:06",
390 .clk = &ref24_clk,
391 }, { /* KMI1 */
392 .dev_id = "fpga:07",
393 .clk = &ref24_clk,
394 }, { /* MMC0 */
395 .dev_id = "fpga:05",
396 .clk = &ref24_clk,
397 }, { /* MMC1 */
398 .dev_id = "fpga:0b",
399 .clk = &ref24_clk,
400 }, { /* SSP */
401 .dev_id = "dev:f4",
402 .clk = &ref24_clk,
403 }, { /* CLCD */
404 .dev_id = "dev:20",
405 .clk = &osc4_clk,
406 }, { /* SP804 timers */
407 .dev_id = "sp804",
408 .clk = &sp804_clk,
409 },
410 };
411
412 /*
413 * CLCD support.
414 */
415 #define SYS_CLCD_MODE_MASK (3 << 0)
416 #define SYS_CLCD_MODE_888 (0 << 0)
417 #define SYS_CLCD_MODE_5551 (1 << 0)
418 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
419 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
420 #define SYS_CLCD_NLCDIOON (1 << 2)
421 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
422 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
423 #define SYS_CLCD_ID_MASK (0x1f << 8)
424 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
425 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
426 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
427 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
428 #define SYS_CLCD_ID_VGA (0x1f << 8)
429
430 static bool is_sanyo_2_5_lcd;
431
432 /*
433 * Disable all display connectors on the interface module.
434 */
435 static void versatile_clcd_disable(struct clcd_fb *fb)
436 {
437 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
438 u32 val;
439
440 val = readl(sys_clcd);
441 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
442 writel(val, sys_clcd);
443
444 #ifdef CONFIG_MACH_VERSATILE_AB
445 /*
446 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
447 */
448 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
449 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
450 unsigned long ctrl;
451
452 ctrl = readl(versatile_ib2_ctrl);
453 ctrl &= ~0x01;
454 writel(ctrl, versatile_ib2_ctrl);
455 }
456 #endif
457 }
458
459 /*
460 * Enable the relevant connector on the interface module.
461 */
462 static void versatile_clcd_enable(struct clcd_fb *fb)
463 {
464 struct fb_var_screeninfo *var = &fb->fb.var;
465 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
466 u32 val;
467
468 val = readl(sys_clcd);
469 val &= ~SYS_CLCD_MODE_MASK;
470
471 switch (var->green.length) {
472 case 5:
473 val |= SYS_CLCD_MODE_5551;
474 break;
475 case 6:
476 if (var->red.offset == 0)
477 val |= SYS_CLCD_MODE_565_RLSB;
478 else
479 val |= SYS_CLCD_MODE_565_BLSB;
480 break;
481 case 8:
482 val |= SYS_CLCD_MODE_888;
483 break;
484 }
485
486 /*
487 * Set the MUX
488 */
489 writel(val, sys_clcd);
490
491 /*
492 * And now enable the PSUs
493 */
494 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
495 writel(val, sys_clcd);
496
497 #ifdef CONFIG_MACH_VERSATILE_AB
498 /*
499 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
500 */
501 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
502 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
503 unsigned long ctrl;
504
505 ctrl = readl(versatile_ib2_ctrl);
506 ctrl |= 0x01;
507 writel(ctrl, versatile_ib2_ctrl);
508 }
509 #endif
510 }
511
512 /*
513 * Detect which LCD panel is connected, and return the appropriate
514 * clcd_panel structure. Note: we do not have any information on
515 * the required timings for the 8.4in panel, so we presently assume
516 * VGA timings.
517 */
518 static int versatile_clcd_setup(struct clcd_fb *fb)
519 {
520 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
521 const char *panel_name;
522 u32 val;
523
524 is_sanyo_2_5_lcd = false;
525
526 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
527 if (val == SYS_CLCD_ID_SANYO_3_8)
528 panel_name = "Sanyo TM38QV67A02A";
529 else if (val == SYS_CLCD_ID_SANYO_2_5) {
530 panel_name = "Sanyo QVGA Portrait";
531 is_sanyo_2_5_lcd = true;
532 } else if (val == SYS_CLCD_ID_EPSON_2_2)
533 panel_name = "Epson L2F50113T00";
534 else if (val == SYS_CLCD_ID_VGA)
535 panel_name = "VGA";
536 else {
537 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
538 val);
539 panel_name = "VGA";
540 }
541
542 fb->panel = versatile_clcd_get_panel(panel_name);
543 if (!fb->panel)
544 return -EINVAL;
545
546 return versatile_clcd_setup_dma(fb, SZ_1M);
547 }
548
549 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
550 {
551 clcdfb_decode(fb, regs);
552
553 /* Always clear BGR for RGB565: we do the routing externally */
554 if (fb->fb.var.green.length == 6)
555 regs->cntl &= ~CNTL_BGR;
556 }
557
558 static struct clcd_board clcd_plat_data = {
559 .name = "Versatile",
560 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
561 .check = clcdfb_check,
562 .decode = versatile_clcd_decode,
563 .disable = versatile_clcd_disable,
564 .enable = versatile_clcd_enable,
565 .setup = versatile_clcd_setup,
566 .mmap = versatile_clcd_mmap_dma,
567 .remove = versatile_clcd_remove_dma,
568 };
569
570 static struct pl061_platform_data gpio0_plat_data = {
571 .gpio_base = 0,
572 .irq_base = IRQ_GPIO0_START,
573 };
574
575 static struct pl061_platform_data gpio1_plat_data = {
576 .gpio_base = 8,
577 .irq_base = IRQ_GPIO1_START,
578 };
579
580 static struct pl022_ssp_controller ssp0_plat_data = {
581 .bus_id = 0,
582 .enable_dma = 0,
583 .num_chipselect = 1,
584 };
585
586 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
587 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
588 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
589 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
590
591 /*
592 * These devices are connected directly to the multi-layer AHB switch
593 */
594 #define SMC_IRQ { NO_IRQ, NO_IRQ }
595 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
596 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
597 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
598
599 /*
600 * These devices are connected via the core APB bridge
601 */
602 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
603 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
604 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
605 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
606 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
607
608 /*
609 * These devices are connected via the DMA APB bridge
610 */
611 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
612 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
613 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
614 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
615 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
616
617 /* FPGA Primecells */
618 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
619 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
620 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
621 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
622
623 /* DevChip Primecells */
624 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
625 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
626 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
627 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
628 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
629 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
630 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
631 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
632 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
633 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
634 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
635 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
636 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
637 AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
638
639 static struct amba_device *amba_devs[] __initdata = {
640 &dmac_device,
641 &uart0_device,
642 &uart1_device,
643 &uart2_device,
644 &smc_device,
645 &mpmc_device,
646 &clcd_device,
647 &sctl_device,
648 &wdog_device,
649 &gpio0_device,
650 &gpio1_device,
651 &rtc_device,
652 &sci0_device,
653 &ssp0_device,
654 &aaci_device,
655 &mmc0_device,
656 &kmi0_device,
657 &kmi1_device,
658 };
659
660 #ifdef CONFIG_OF
661 /*
662 * Lookup table for attaching a specific name and platform_data pointer to
663 * devices as they get created by of_platform_populate(). Ideally this table
664 * would not exist, but the current clock implementation depends on some devices
665 * having a specific name.
666 */
667 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
668 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
670 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
672 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
673
674 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
677 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
678 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
679
680 #if 0
681 /*
682 * These entries are unnecessary because no clocks referencing
683 * them. I've left them in for now as place holders in case
684 * any of them need to be added back, but they should be
685 * removed before actually committing this patch. --gcl
686 */
687 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
688 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
689 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
690 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
691 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
692
693 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
694 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
695 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
696 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
697 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
698 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
699 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
700 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
701 #endif
702 {}
703 };
704 #endif
705
706 #ifdef CONFIG_LEDS
707 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
708
709 static void versatile_leds_event(led_event_t ledevt)
710 {
711 unsigned long flags;
712 u32 val;
713
714 local_irq_save(flags);
715 val = readl(VA_LEDS_BASE);
716
717 switch (ledevt) {
718 case led_idle_start:
719 val = val & ~VERSATILE_SYS_LED0;
720 break;
721
722 case led_idle_end:
723 val = val | VERSATILE_SYS_LED0;
724 break;
725
726 case led_timer:
727 val = val ^ VERSATILE_SYS_LED1;
728 break;
729
730 case led_halted:
731 val = 0;
732 break;
733
734 default:
735 break;
736 }
737
738 writel(val, VA_LEDS_BASE);
739 local_irq_restore(flags);
740 }
741 #endif /* CONFIG_LEDS */
742
743 /* Early initializations */
744 void __init versatile_init_early(void)
745 {
746 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
747
748 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
749 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
750
751 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
752 }
753
754 void __init versatile_init(void)
755 {
756 int i;
757
758 platform_device_register(&versatile_flash_device);
759 platform_device_register(&versatile_i2c_device);
760 platform_device_register(&smc91x_device);
761 platform_device_register(&char_lcd_device);
762
763 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
764 struct amba_device *d = amba_devs[i];
765 amba_device_register(d, &iomem_resource);
766 }
767
768 #ifdef CONFIG_LEDS
769 leds_event = versatile_leds_event;
770 #endif
771 }
772
773 /*
774 * Where is the timer (VA)?
775 */
776 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
777 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
778 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
779 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
780
781 /*
782 * Set up timer interrupt, and return the current time in seconds.
783 */
784 static void __init versatile_timer_init(void)
785 {
786 u32 val;
787
788 /*
789 * set clock frequency:
790 * VERSATILE_REFCLK is 32KHz
791 * VERSATILE_TIMCLK is 1MHz
792 */
793 val = readl(__io_address(VERSATILE_SCTL_BASE));
794 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
795 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
796 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
797 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
798 __io_address(VERSATILE_SCTL_BASE));
799
800 /*
801 * Initialise to a known state (all timers off)
802 */
803 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
804 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
805 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
806 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
807
808 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
809 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
810 }
811
812 struct sys_timer versatile_timer = {
813 .init = versatile_timer_init,
814 };
815
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