1 // SPDX-License-Identifier: GPL-2.0-only
3 * This file contains Xilinx specific SMP code, used to start up
4 * the second processor.
6 * Copyright (C) 2011-2013 Xilinx
8 * based on linux/arch/arm/mach-realview/platsmp.c
10 * Copyright (C) 2002 ARM Ltd.
13 #include <linux/export.h>
14 #include <linux/jiffies.h>
15 #include <linux/init.h>
17 #include <asm/cacheflush.h>
18 #include <asm/smp_scu.h>
19 #include <linux/irqchip/arm-gic.h>
23 * Store number of cores in the system
24 * Because of scu_get_core_count() must be in __init section and can't
25 * be called from zynq_cpun_start() because it is not in __init section.
29 int zynq_cpun_start(u32 address
, int cpu
)
31 u32 trampoline_code_size
= &zynq_secondary_trampoline_end
-
32 &zynq_secondary_trampoline
;
34 /* MS: Expectation that SLCR are directly map and accessible */
35 /* Not possible to jump to non aligned address */
36 if (!(address
& 3) && (!address
|| (address
>= trampoline_code_size
))) {
37 /* Store pointer to ioremap area which points to address 0x0 */
38 static u8 __iomem
*zero
;
39 u32 trampoline_size
= &zynq_secondary_trampoline_jump
-
40 &zynq_secondary_trampoline
;
42 zynq_slcr_cpu_stop(cpu
);
44 if (__pa(PAGE_OFFSET
)) {
45 zero
= ioremap(0, trampoline_code_size
);
47 pr_warn("BOOTUP jump vectors not accessible\n");
51 zero
= (__force u8 __iomem
*)PAGE_OFFSET
;
55 * This is elegant way how to jump to any address
56 * 0x0: Load address at 0x8 to r0
57 * 0x4: Jump by mov instruction
58 * 0x8: Jumping address
60 memcpy_toio(zero
, &zynq_secondary_trampoline
,
62 writel(address
, zero
+ trampoline_size
);
65 outer_flush_range(0, trampoline_code_size
);
68 if (__pa(PAGE_OFFSET
))
71 zynq_slcr_cpu_start(cpu
);
76 pr_warn("Can't start CPU%d: Wrong starting address %x\n", cpu
, address
);
80 EXPORT_SYMBOL(zynq_cpun_start
);
82 static int zynq_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
84 return zynq_cpun_start(__pa_symbol(secondary_startup
), cpu
);
88 * Initialise the CPU possible map early - this describes the CPUs
89 * which may be present or become present in the system.
91 static void __init
zynq_smp_init_cpus(void)
95 ncores
= scu_get_core_count(zynq_scu_base
);
97 for (i
= 0; i
< ncores
&& i
< CONFIG_NR_CPUS
; i
++)
98 set_cpu_possible(i
, true);
101 static void __init
zynq_smp_prepare_cpus(unsigned int max_cpus
)
103 scu_enable(zynq_scu_base
);
107 * zynq_secondary_init - Initialize secondary CPU cores
108 * @cpu: CPU that is initialized
110 * This function is in the hotplug path. Don't move it into the
113 static void zynq_secondary_init(unsigned int cpu
)
118 #ifdef CONFIG_HOTPLUG_CPU
119 static int zynq_cpu_kill(unsigned cpu
)
121 unsigned long timeout
= jiffies
+ msecs_to_jiffies(50);
123 while (zynq_slcr_cpu_state_read(cpu
))
124 if (time_after(jiffies
, timeout
))
127 zynq_slcr_cpu_stop(cpu
);
132 * zynq_cpu_die - Let a CPU core die
135 * Platform-specific code to shutdown a CPU.
136 * Called with IRQs disabled on the dying CPU.
138 static void zynq_cpu_die(unsigned int cpu
)
140 zynq_slcr_cpu_state_write(cpu
, true);
143 * there is no power-control hardware on this platform, so all
144 * we can do is put the core into WFI; this is safe as the calling
145 * code will have already disabled interrupts
152 const struct smp_operations zynq_smp_ops __initconst
= {
153 .smp_init_cpus
= zynq_smp_init_cpus
,
154 .smp_prepare_cpus
= zynq_smp_prepare_cpus
,
155 .smp_boot_secondary
= zynq_boot_secondary
,
156 .smp_secondary_init
= zynq_secondary_init
,
157 #ifdef CONFIG_HOTPLUG_CPU
158 .cpu_die
= zynq_cpu_die
,
159 .cpu_kill
= zynq_cpu_kill
,