arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 config CPU_32
   4         bool
   5         default y
   6
   7 # Select CPU types depending on the architecture selected.  This selects
   8 # which CPUs we support in the kernel image, and the compiler instruction
   9 # optimiser behaviour.
  10
  11 # ARM610
  12 config CPU_ARM610
  13         bool "Support ARM610 processor"
  14         depends on ARCH_RPC
  15         select CPU_32v3
  16         select CPU_CACHE_V3
  17         select CPU_CACHE_VIVT
  18         select CPU_CP15_MMU
  19         select CPU_COPY_V3 if MMU
  20         select CPU_TLB_V3 if MMU
  21         select CPU_PABRT_NOIFAR
  22         help
  23           The ARM610 is the successor to the ARM3 processor
  24           and was produced by VLSI Technology Inc.
  25
  26           Say Y if you want support for the ARM610 processor.
  27           Otherwise, say N.
  28
  29 # ARM7TDMI
  30 config CPU_ARM7TDMI
  31         bool "Support ARM7TDMI processor"
  32         depends on !MMU
  33         select CPU_32v4T
  34         select CPU_ABRT_LV4T
  35         select CPU_PABRT_NOIFAR
  36         select CPU_CACHE_V4
  37         help
  38           A 32-bit RISC microprocessor based on the ARM7 processor core
  39           which has no memory control unit and cache.
  40
  41           Say Y if you want support for the ARM7TDMI processor.
  42           Otherwise, say N.
  43
  44 # ARM710
  45 config CPU_ARM710
  46         bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  47         default y if ARCH_CLPS7500
  48         select CPU_32v3
  49         select CPU_CACHE_V3
  50         select CPU_CACHE_VIVT
  51         select CPU_CP15_MMU
  52         select CPU_COPY_V3 if MMU
  53         select CPU_TLB_V3 if MMU
  54         select CPU_PABRT_NOIFAR
  55         help
  56           A 32-bit RISC microprocessor based on the ARM7 processor core
  57           designed by Advanced RISC Machines Ltd. The ARM710 is the
  58           successor to the ARM610 processor. It was released in
  59           July 1994 by VLSI Technology Inc.
  60
  61           Say Y if you want support for the ARM710 processor.
  62           Otherwise, say N.
  63
  64 # ARM720T
  65 config CPU_ARM720T
  66         bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  67         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  68         select CPU_32v4T
  69         select CPU_ABRT_LV4T
  70         select CPU_PABRT_NOIFAR
  71         select CPU_CACHE_V4
  72         select CPU_CACHE_VIVT
  73         select CPU_CP15_MMU
  74         select CPU_COPY_V4WT if MMU
  75         select CPU_TLB_V4WT if MMU
  76         help
  77           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  78           MMU built around an ARM7TDMI core.
  79
  80           Say Y if you want support for the ARM720T processor.
  81           Otherwise, say N.
  82
  83 # ARM740T
  84 config CPU_ARM740T
  85         bool "Support ARM740T processor" if ARCH_INTEGRATOR
  86         depends on !MMU
  87         select CPU_32v4T
  88         select CPU_ABRT_LV4T
  89         select CPU_PABRT_NOIFAR
  90         select CPU_CACHE_V3     # although the core is v4t
  91         select CPU_CP15_MPU
  92         help
  93           A 32-bit RISC processor with 8KB cache or 4KB variants,
  94           write buffer and MPU(Protection Unit) built around
  95           an ARM7TDMI core.
  96
  97           Say Y if you want support for the ARM740T processor.
  98           Otherwise, say N.
  99
 100 # ARM9TDMI
 101 config CPU_ARM9TDMI
 102         bool "Support ARM9TDMI processor"
 103         depends on !MMU
 104         select CPU_32v4T
 105         select CPU_ABRT_NOMMU
 106         select CPU_PABRT_NOIFAR
 107         select CPU_CACHE_V4
 108         help
 109           A 32-bit RISC microprocessor based on the ARM9 processor core
 110           which has no memory control unit and cache.
 111
 112           Say Y if you want support for the ARM9TDMI processor.
 113           Otherwise, say N.
 114
 115 # ARM920T
 116 config CPU_ARM920T
 117         bool "Support ARM920T processor"
 118         depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
 119         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
 120         select CPU_32v4T
 121         select CPU_ABRT_EV4T
 122         select CPU_PABRT_NOIFAR
 123         select CPU_CACHE_V4WT
 124         select CPU_CACHE_VIVT
 125         select CPU_CP15_MMU
 126         select CPU_COPY_V4WB if MMU
 127         select CPU_TLB_V4WBI if MMU
 128         help
 129           The ARM920T is licensed to be produced by numerous vendors,
 130           and is used in the Maverick EP9312 and the Samsung S3C2410.
 131
 132           More information on the Maverick EP9312 at
 133           <http://linuxdevices.com/products/PD2382866068.html>.
 134
 135           Say Y if you want support for the ARM920T processor.
 136           Otherwise, say N.
 137
 138 # ARM922T
 139 config CPU_ARM922T
 140         bool "Support ARM922T processor" if ARCH_INTEGRATOR
 141         depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
 142         default y if ARCH_LH7A40X || ARCH_KS8695
 143         select CPU_32v4T
 144         select CPU_ABRT_EV4T
 145         select CPU_PABRT_NOIFAR
 146         select CPU_CACHE_V4WT
 147         select CPU_CACHE_VIVT
 148         select CPU_CP15_MMU
 149         select CPU_COPY_V4WB if MMU
 150         select CPU_TLB_V4WBI if MMU
 151         help
 152           The ARM922T is a version of the ARM920T, but with smaller
 153           instruction and data caches. It is used in Altera's
 154           Excalibur XA device family and Micrel's KS8695 Centaur.
 155
 156           Say Y if you want support for the ARM922T processor.
 157           Otherwise, say N.
 158
 159 # ARM925T
 160 config CPU_ARM925T
 161         bool "Support ARM925T processor" if ARCH_OMAP1
 162         depends on ARCH_OMAP15XX
 163         default y if ARCH_OMAP15XX
 164         select CPU_32v4T
 165         select CPU_ABRT_EV4T
 166         select CPU_PABRT_NOIFAR
 167         select CPU_CACHE_V4WT
 168         select CPU_CACHE_VIVT
 169         select CPU_CP15_MMU
 170         select CPU_COPY_V4WB if MMU
 171         select CPU_TLB_V4WBI if MMU
 172         help
 173           The ARM925T is a mix between the ARM920T and ARM926T, but with
 174           different instruction and data caches. It is used in TI's OMAP
 175           device family.
 176
 177           Say Y if you want support for the ARM925T processor.
 178           Otherwise, say N.
 179
 180 # ARM926T
 181 config CPU_ARM926T
 182         bool "Support ARM926T processor"
 183         depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
 184                 MACH_VERSATILE_AB || ARCH_OMAP730 || \
 185                 ARCH_OMAP16XX || MACH_REALVIEW_EB || \
 186                 ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
 187                 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
 188                 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
 189                 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
 190                 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
 191         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
 192                 ARCH_OMAP730 || ARCH_OMAP16XX || \
 193                 ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
 194                 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
 195                 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
 196                 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
 197                 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
 198         select CPU_32v5
 199         select CPU_ABRT_EV5TJ
 200         select CPU_PABRT_NOIFAR
 201         select CPU_CACHE_VIVT
 202         select CPU_CP15_MMU
 203         select CPU_COPY_V4WB if MMU
 204         select CPU_TLB_V4WBI if MMU
 205         help
 206           This is a variant of the ARM920.  It has slightly different
 207           instruction sequences for cache and TLB operations.  Curiously,
 208           there is no documentation on it at the ARM corporate website.
 209
 210           Say Y if you want support for the ARM926T processor.
 211           Otherwise, say N.
 212
 213 # ARM940T
 214 config CPU_ARM940T
 215         bool "Support ARM940T processor" if ARCH_INTEGRATOR
 216         depends on !MMU
 217         select CPU_32v4T
 218         select CPU_ABRT_NOMMU
 219         select CPU_PABRT_NOIFAR
 220         select CPU_CACHE_VIVT
 221         select CPU_CP15_MPU
 222         help
 223           ARM940T is a member of the ARM9TDMI family of general-
 224           purpose microprocessors with MPU and separate 4KB
 225           instruction and 4KB data cases, each with a 4-word line
 226           length.
 227
 228           Say Y if you want support for the ARM940T processor.
 229           Otherwise, say N.
 230
 231 # ARM946E-S
 232 config CPU_ARM946E
 233         bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
 234         depends on !MMU
 235         select CPU_32v5
 236         select CPU_ABRT_NOMMU
 237         select CPU_PABRT_NOIFAR
 238         select CPU_CACHE_VIVT
 239         select CPU_CP15_MPU
 240         help
 241           ARM946E-S is a member of the ARM9E-S family of high-
 242           performance, 32-bit system-on-chip processor solutions.
 243           The TCM and ARMv5TE 32-bit instruction set is supported.
 244
 245           Say Y if you want support for the ARM946E-S processor.
 246           Otherwise, say N.
 247
 248 # ARM1020 - needs validating
 249 config CPU_ARM1020
 250         bool "Support ARM1020T (rev 0) processor"
 251         depends on ARCH_INTEGRATOR
 252         select CPU_32v5
 253         select CPU_ABRT_EV4T
 254         select CPU_PABRT_NOIFAR
 255         select CPU_CACHE_V4WT
 256         select CPU_CACHE_VIVT
 257         select CPU_CP15_MMU
 258         select CPU_COPY_V4WB if MMU
 259         select CPU_TLB_V4WBI if MMU
 260         help
 261           The ARM1020 is the 32K cached version of the ARM10 processor,
 262           with an addition of a floating-point unit.
 263
 264           Say Y if you want support for the ARM1020 processor.
 265           Otherwise, say N.
 266
 267 # ARM1020E - needs validating
 268 config CPU_ARM1020E
 269         bool "Support ARM1020E processor"
 270         depends on ARCH_INTEGRATOR
 271         select CPU_32v5
 272         select CPU_ABRT_EV4T
 273         select CPU_PABRT_NOIFAR
 274         select CPU_CACHE_V4WT
 275         select CPU_CACHE_VIVT
 276         select CPU_CP15_MMU
 277         select CPU_COPY_V4WB if MMU
 278         select CPU_TLB_V4WBI if MMU
 279         depends on n
 280
 281 # ARM1022E
 282 config CPU_ARM1022
 283         bool "Support ARM1022E processor"
 284         depends on ARCH_INTEGRATOR
 285         select CPU_32v5
 286         select CPU_ABRT_EV4T
 287         select CPU_PABRT_NOIFAR
 288         select CPU_CACHE_VIVT
 289         select CPU_CP15_MMU
 290         select CPU_COPY_V4WB if MMU # can probably do better
 291         select CPU_TLB_V4WBI if MMU
 292         help
 293           The ARM1022E is an implementation of the ARMv5TE architecture
 294           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 295           embedded trace macrocell, and a floating-point unit.
 296
 297           Say Y if you want support for the ARM1022E processor.
 298           Otherwise, say N.
 299
 300 # ARM1026EJ-S
 301 config CPU_ARM1026
 302         bool "Support ARM1026EJ-S processor"
 303         depends on ARCH_INTEGRATOR
 304         select CPU_32v5
 305         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 306         select CPU_PABRT_NOIFAR
 307         select CPU_CACHE_VIVT
 308         select CPU_CP15_MMU
 309         select CPU_COPY_V4WB if MMU # can probably do better
 310         select CPU_TLB_V4WBI if MMU
 311         help
 312           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 313           based upon the ARM10 integer core.
 314
 315           Say Y if you want support for the ARM1026EJ-S processor.
 316           Otherwise, say N.
 317
 318 # SA110
 319 config CPU_SA110
 320         bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
 321         default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
 322         select CPU_32v3 if ARCH_RPC
 323         select CPU_32v4 if !ARCH_RPC
 324         select CPU_ABRT_EV4
 325         select CPU_PABRT_NOIFAR
 326         select CPU_CACHE_V4WB
 327         select CPU_CACHE_VIVT
 328         select CPU_CP15_MMU
 329         select CPU_COPY_V4WB if MMU
 330         select CPU_TLB_V4WB if MMU
 331         help
 332           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 333           is available at five speeds ranging from 100 MHz to 233 MHz.
 334           More information is available at
 335           <http://developer.intel.com/design/strong/sa110.htm>.
 336
 337           Say Y if you want support for the SA-110 processor.
 338           Otherwise, say N.
 339
 340 # SA1100
 341 config CPU_SA1100
 342         bool
 343         depends on ARCH_SA1100
 344         default y
 345         select CPU_32v4
 346         select CPU_ABRT_EV4
 347         select CPU_PABRT_NOIFAR
 348         select CPU_CACHE_V4WB
 349         select CPU_CACHE_VIVT
 350         select CPU_CP15_MMU
 351         select CPU_TLB_V4WB if MMU
 352
 353 # XScale
 354 config CPU_XSCALE
 355         bool
 356         depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
 357         default y
 358         select CPU_32v5
 359         select CPU_ABRT_EV5T
 360         select CPU_PABRT_NOIFAR
 361         select CPU_CACHE_VIVT
 362         select CPU_CP15_MMU
 363         select CPU_TLB_V4WBI if MMU
 364
 365 # XScale Core Version 3
 366 config CPU_XSC3
 367         bool
 368         depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
 369         default y
 370         select CPU_32v5
 371         select CPU_ABRT_EV5T
 372         select CPU_PABRT_NOIFAR
 373         select CPU_CACHE_VIVT
 374         select CPU_CP15_MMU
 375         select CPU_TLB_V4WBI if MMU
 376         select IO_36
 377
 378 # Feroceon
 379 config CPU_FEROCEON
 380         bool
 381         depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
 382         default y
 383         select CPU_32v5
 384         select CPU_ABRT_EV5T
 385         select CPU_PABRT_NOIFAR
 386         select CPU_CACHE_VIVT
 387         select CPU_CP15_MMU
 388         select CPU_COPY_FEROCEON if MMU
 389         select CPU_TLB_FEROCEON if MMU
 390
 391 config CPU_FEROCEON_OLD_ID
 392         bool "Accept early Feroceon cores with an ARM926 ID"
 393         depends on CPU_FEROCEON && !CPU_ARM926T
 394         default y
 395         help
 396           This enables the usage of some old Feroceon cores
 397           for which the CPU ID is equal to the ARM926 ID.
 398           Relevant for Feroceon-1850 and early Feroceon-2850.
 399
 400 # ARMv6
 401 config CPU_V6
 402         bool "Support ARM V6 processor"
 403         depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
 404         default y if ARCH_MX3
 405         default y if ARCH_MSM
 406         select CPU_32v6
 407         select CPU_ABRT_EV6
 408         select CPU_PABRT_NOIFAR
 409         select CPU_CACHE_V6
 410         select CPU_CACHE_VIPT
 411         select CPU_CP15_MMU
 412         select CPU_HAS_ASID if MMU
 413         select CPU_COPY_V6 if MMU
 414         select CPU_TLB_V6 if MMU
 415
 416 # ARMv6k
 417 config CPU_32v6K
 418         bool "Support ARM V6K processor extensions" if !SMP
 419         depends on CPU_V6
 420         default y if SMP && !ARCH_MX3
 421         help
 422           Say Y here if your ARMv6 processor supports the 'K' extension.
 423           This enables the kernel to use some instructions not present
 424           on previous processors, and as such a kernel build with this
 425           enabled will not boot on processors with do not support these
 426           instructions.
 427
 428 # ARMv7
 429 config CPU_V7
 430         bool "Support ARM V7 processor"
 431         depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3
 432         select CPU_32v6K
 433         select CPU_32v7
 434         select CPU_ABRT_EV7
 435         select CPU_PABRT_IFAR
 436         select CPU_CACHE_V7
 437         select CPU_CACHE_VIPT
 438         select CPU_CP15_MMU
 439         select CPU_HAS_ASID if MMU
 440         select CPU_COPY_V6 if MMU
 441         select CPU_TLB_V7 if MMU
 442
 443 # Figure out what processor architecture version we should be using.
 444 # This defines the compiler instruction set which depends on the machine type.
 445 config CPU_32v3
 446         bool
 447         select TLS_REG_EMUL if SMP || !MMU
 448         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 449
 450 config CPU_32v4
 451         bool
 452         select TLS_REG_EMUL if SMP || !MMU
 453         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 454
 455 config CPU_32v4T
 456         bool
 457         select TLS_REG_EMUL if SMP || !MMU
 458         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 459
 460 config CPU_32v5
 461         bool
 462         select TLS_REG_EMUL if SMP || !MMU
 463         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 464
 465 config CPU_32v6
 466         bool
 467         select TLS_REG_EMUL if !CPU_32v6K && !MMU
 468
 469 config CPU_32v7
 470         bool
 471
 472 # The abort model
 473 config CPU_ABRT_NOMMU
 474         bool
 475
 476 config CPU_ABRT_EV4
 477         bool
 478
 479 config CPU_ABRT_EV4T
 480         bool
 481
 482 config CPU_ABRT_LV4T
 483         bool
 484
 485 config CPU_ABRT_EV5T
 486         bool
 487
 488 config CPU_ABRT_EV5TJ
 489         bool
 490
 491 config CPU_ABRT_EV6
 492         bool
 493
 494 config CPU_ABRT_EV7
 495         bool
 496
 497 config CPU_PABRT_IFAR
 498         bool
 499
 500 config CPU_PABRT_NOIFAR
 501         bool
 502
 503 # The cache model
 504 config CPU_CACHE_V3
 505         bool
 506
 507 config CPU_CACHE_V4
 508         bool
 509
 510 config CPU_CACHE_V4WT
 511         bool
 512
 513 config CPU_CACHE_V4WB
 514         bool
 515
 516 config CPU_CACHE_V6
 517         bool
 518
 519 config CPU_CACHE_V7
 520         bool
 521
 522 config CPU_CACHE_VIVT
 523         bool
 524
 525 config CPU_CACHE_VIPT
 526         bool
 527
 528 if MMU
 529 # The copy-page model
 530 config CPU_COPY_V3
 531         bool
 532
 533 config CPU_COPY_V4WT
 534         bool
 535
 536 config CPU_COPY_V4WB
 537         bool
 538
 539 config CPU_COPY_FEROCEON
 540         bool
 541
 542 config CPU_COPY_V6
 543         bool
 544
 545 # This selects the TLB model
 546 config CPU_TLB_V3
 547         bool
 548         help
 549           ARM Architecture Version 3 TLB.
 550
 551 config CPU_TLB_V4WT
 552         bool
 553         help
 554           ARM Architecture Version 4 TLB with writethrough cache.
 555
 556 config CPU_TLB_V4WB
 557         bool
 558         help
 559           ARM Architecture Version 4 TLB with writeback cache.
 560
 561 config CPU_TLB_V4WBI
 562         bool
 563         help
 564           ARM Architecture Version 4 TLB with writeback cache and invalidate
 565           instruction cache entry.
 566
 567 config CPU_TLB_FEROCEON
 568         bool
 569         help
 570           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 571
 572 config CPU_TLB_V6
 573         bool
 574
 575 config CPU_TLB_V7
 576         bool
 577
 578 endif
 579
 580 config CPU_HAS_ASID
 581         bool
 582         help
 583           This indicates whether the CPU has the ASID register; used to
 584           tag TLB and possibly cache entries.
 585
 586 config CPU_CP15
 587         bool
 588         help
 589           Processor has the CP15 register.
 590
 591 config CPU_CP15_MMU
 592         bool
 593         select CPU_CP15
 594         help
 595           Processor has the CP15 register, which has MMU related registers.
 596
 597 config CPU_CP15_MPU
 598         bool
 599         select CPU_CP15
 600         help
 601           Processor has the CP15 register, which has MPU related registers.
 602
 603 #
 604 # CPU supports 36-bit I/O
 605 #
 606 config IO_36
 607         bool
 608
 609 comment "Processor Features"
 610
 611 config ARM_THUMB
 612         bool "Support Thumb user binaries"
 613         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
 614         default y
 615         help
 616           Say Y if you want to include kernel support for running user space
 617           Thumb binaries.
 618
 619           The Thumb instruction set is a compressed form of the standard ARM
 620           instruction set resulting in smaller binaries at the expense of
 621           slightly less efficient code.
 622
 623           If you don't know what this all is, saying Y is a safe choice.
 624
 625 config ARM_THUMBEE
 626         bool "Enable ThumbEE CPU extension"
 627         depends on CPU_V7
 628         help
 629           Say Y here if you have a CPU with the ThumbEE extension and code to
 630           make use of it. Say N for code that can run on CPUs without ThumbEE.
 631
 632 config CPU_BIG_ENDIAN
 633         bool "Build big-endian kernel"
 634         depends on ARCH_SUPPORTS_BIG_ENDIAN
 635         help
 636           Say Y if you plan on running a kernel in big-endian mode.
 637           Note that your board must be properly built and your board
 638           port must properly enable any big-endian related features
 639           of your chipset/board/processor.
 640
 641 config CPU_HIGH_VECTOR
 642         depends on !MMU && CPU_CP15 && !CPU_ARM740T
 643         bool "Select the High exception vector"
 644         default n
 645         help
 646           Say Y here to select high exception vector(0xFFFF0000~).
 647           The exception vector can be vary depending on the platform
 648           design in nommu mode. If your platform needs to select
 649           high exception vector, say Y.
 650           Otherwise or if you are unsure, say N, and the low exception
 651           vector (0x00000000~) will be used.
 652
 653 config CPU_ICACHE_DISABLE
 654         bool "Disable I-Cache (I-bit)"
 655         depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 656         help
 657           Say Y here to disable the processor instruction cache. Unless
 658           you have a reason not to or are unsure, say N.
 659
 660 config CPU_DCACHE_DISABLE
 661         bool "Disable D-Cache (C-bit)"
 662         depends on CPU_CP15
 663         help
 664           Say Y here to disable the processor data cache. Unless
 665           you have a reason not to or are unsure, say N.
 666
 667 config CPU_DCACHE_SIZE
 668         hex
 669         depends on CPU_ARM740T || CPU_ARM946E
 670         default 0x00001000 if CPU_ARM740T
 671         default 0x00002000 # default size for ARM946E-S
 672         help
 673           Some cores are synthesizable to have various sized cache. For
 674           ARM946E-S case, it can vary from 0KB to 1MB.
 675           To support such cache operations, it is efficient to know the size
 676           before compile time.
 677           If your SoC is configured to have a different size, define the value
 678           here with proper conditions.
 679
 680 config CPU_DCACHE_WRITETHROUGH
 681         bool "Force write through D-cache"
 682         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
 683         default y if CPU_ARM925T
 684         help
 685           Say Y here to use the data cache in writethrough mode. Unless you
 686           specifically require this or are unsure, say N.
 687
 688 config CPU_CACHE_ROUND_ROBIN
 689         bool "Round robin I and D cache replacement algorithm"
 690         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 691         help
 692           Say Y here to use the predictable round-robin cache replacement
 693           policy.  Unless you specifically require this or are unsure, say N.
 694
 695 config CPU_BPREDICT_DISABLE
 696         bool "Disable branch prediction"
 697         depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
 698         help
 699           Say Y here to disable branch prediction.  If unsure, say N.
 700
 701 config TLS_REG_EMUL
 702         bool
 703         help
 704           An SMP system using a pre-ARMv6 processor (there are apparently
 705           a few prototypes like that in existence) and therefore access to
 706           that required register must be emulated.
 707
 708 config HAS_TLS_REG
 709         bool
 710         depends on !TLS_REG_EMUL
 711         default y if SMP || CPU_32v7
 712         help
 713           This selects support for the CP15 thread register.
 714           It is defined to be available on some ARMv6 processors (including
 715           all SMP capable ARMv6's) or later processors.  User space may
 716           assume directly accessing that register and always obtain the
 717           expected value only on ARMv7 and above.
 718
 719 config NEEDS_SYSCALL_FOR_CMPXCHG
 720         bool
 721         help
 722           SMP on a pre-ARMv6 processor?  Well OK then.
 723           Forget about fast user space cmpxchg support.
 724           It is just not possible.
 725
 726 config OUTER_CACHE
 727         bool
 728         default n
 729
 730 config CACHE_FEROCEON_L2
 731         bool "Enable the Feroceon L2 cache controller"
 732         depends on ARCH_KIRKWOOD || ARCH_MV78XX0
 733         default y
 734         select OUTER_CACHE
 735         help
 736           This option enables the Feroceon L2 cache controller.
 737
 738 config CACHE_FEROCEON_L2_WRITETHROUGH
 739         bool "Force Feroceon L2 cache write through"
 740         depends on CACHE_FEROCEON_L2
 741         default n
 742         help
 743           Say Y here to use the Feroceon L2 cache in writethrough mode.
 744           Unless you specifically require this, say N for writeback mode.
 745
 746 config CACHE_L2X0
 747         bool "Enable the L2x0 outer cache controller"
 748         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP
 749         default y
 750         select OUTER_CACHE
 751         help
 752           This option enables the L2x0 PrimeCell.
 753
 754 config CACHE_XSC3L2
 755         bool "Enable the L2 cache on XScale3"
 756         depends on CPU_XSC3
 757         default y
 758         select OUTER_CACHE
 759         help
 760           This option enables the L2 cache on XScale3.