1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor"
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
21 select CPU_PABRT_NOIFAR
23 The ARM610 is the successor to the ARM3 processor
24 and was produced by VLSI Technology Inc.
26 Say Y if you want support for the ARM610 processor.
31 bool "Support ARM7TDMI processor"
35 select CPU_PABRT_NOIFAR
38 A 32-bit RISC microprocessor based on the ARM7 processor core
39 which has no memory control unit and cache.
41 Say Y if you want support for the ARM7TDMI processor.
46 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
47 default y if ARCH_CLPS7500
52 select CPU_COPY_V3 if MMU
53 select CPU_TLB_V3 if MMU
54 select CPU_PABRT_NOIFAR
56 A 32-bit RISC microprocessor based on the ARM7 processor core
57 designed by Advanced RISC Machines Ltd. The ARM710 is the
58 successor to the ARM610 processor. It was released in
59 July 1994 by VLSI Technology Inc.
61 Say Y if you want support for the ARM710 processor.
66 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
67 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
70 select CPU_PABRT_NOIFAR
74 select CPU_COPY_V4WT if MMU
75 select CPU_TLB_V4WT if MMU
77 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
78 MMU built around an ARM7TDMI core.
80 Say Y if you want support for the ARM720T processor.
85 bool "Support ARM740T processor" if ARCH_INTEGRATOR
89 select CPU_PABRT_NOIFAR
90 select CPU_CACHE_V3 # although the core is v4t
93 A 32-bit RISC processor with 8KB cache or 4KB variants,
94 write buffer and MPU(Protection Unit) built around
97 Say Y if you want support for the ARM740T processor.
102 bool "Support ARM9TDMI processor"
105 select CPU_ABRT_NOMMU
106 select CPU_PABRT_NOIFAR
109 A 32-bit RISC microprocessor based on the ARM9 processor core
110 which has no memory control unit and cache.
112 Say Y if you want support for the ARM9TDMI processor.
117 bool "Support ARM920T processor"
118 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
119 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
122 select CPU_PABRT_NOIFAR
123 select CPU_CACHE_V4WT
124 select CPU_CACHE_VIVT
126 select CPU_COPY_V4WB if MMU
127 select CPU_TLB_V4WBI if MMU
129 The ARM920T is licensed to be produced by numerous vendors,
130 and is used in the Maverick EP9312 and the Samsung S3C2410.
132 More information on the Maverick EP9312 at
133 <http://linuxdevices.com/products/PD2382866068.html>.
135 Say Y if you want support for the ARM920T processor.
140 bool "Support ARM922T processor" if ARCH_INTEGRATOR
141 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
142 default y if ARCH_LH7A40X || ARCH_KS8695
145 select CPU_PABRT_NOIFAR
146 select CPU_CACHE_V4WT
147 select CPU_CACHE_VIVT
149 select CPU_COPY_V4WB if MMU
150 select CPU_TLB_V4WBI if MMU
152 The ARM922T is a version of the ARM920T, but with smaller
153 instruction and data caches. It is used in Altera's
154 Excalibur XA device family and Micrel's KS8695 Centaur.
156 Say Y if you want support for the ARM922T processor.
161 bool "Support ARM925T processor" if ARCH_OMAP1
162 depends on ARCH_OMAP15XX
163 default y if ARCH_OMAP15XX
166 select CPU_PABRT_NOIFAR
167 select CPU_CACHE_V4WT
168 select CPU_CACHE_VIVT
170 select CPU_COPY_V4WB if MMU
171 select CPU_TLB_V4WBI if MMU
173 The ARM925T is a mix between the ARM920T and ARM926T, but with
174 different instruction and data caches. It is used in TI's OMAP
177 Say Y if you want support for the ARM925T processor.
182 bool "Support ARM926T processor"
183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
184 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
186 select CPU_ABRT_EV5TJ
187 select CPU_PABRT_NOIFAR
188 select CPU_CACHE_VIVT
190 select CPU_COPY_V4WB if MMU
191 select CPU_TLB_V4WBI if MMU
193 This is a variant of the ARM920. It has slightly different
194 instruction sequences for cache and TLB operations. Curiously,
195 there is no documentation on it at the ARM corporate website.
197 Say Y if you want support for the ARM926T processor.
202 bool "Support ARM940T processor" if ARCH_INTEGRATOR
205 select CPU_ABRT_NOMMU
206 select CPU_PABRT_NOIFAR
207 select CPU_CACHE_VIVT
210 ARM940T is a member of the ARM9TDMI family of general-
211 purpose microprocessors with MPU and separate 4KB
212 instruction and 4KB data cases, each with a 4-word line
215 Say Y if you want support for the ARM940T processor.
220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
223 select CPU_ABRT_NOMMU
224 select CPU_PABRT_NOIFAR
225 select CPU_CACHE_VIVT
228 ARM946E-S is a member of the ARM9E-S family of high-
229 performance, 32-bit system-on-chip processor solutions.
230 The TCM and ARMv5TE 32-bit instruction set is supported.
232 Say Y if you want support for the ARM946E-S processor.
235 # ARM1020 - needs validating
237 bool "Support ARM1020T (rev 0) processor"
238 depends on ARCH_INTEGRATOR
241 select CPU_PABRT_NOIFAR
242 select CPU_CACHE_V4WT
243 select CPU_CACHE_VIVT
245 select CPU_COPY_V4WB if MMU
246 select CPU_TLB_V4WBI if MMU
248 The ARM1020 is the 32K cached version of the ARM10 processor,
249 with an addition of a floating-point unit.
251 Say Y if you want support for the ARM1020 processor.
254 # ARM1020E - needs validating
256 bool "Support ARM1020E processor"
257 depends on ARCH_INTEGRATOR
260 select CPU_PABRT_NOIFAR
261 select CPU_CACHE_V4WT
262 select CPU_CACHE_VIVT
264 select CPU_COPY_V4WB if MMU
265 select CPU_TLB_V4WBI if MMU
270 bool "Support ARM1022E processor"
271 depends on ARCH_INTEGRATOR
274 select CPU_PABRT_NOIFAR
275 select CPU_CACHE_VIVT
277 select CPU_COPY_V4WB if MMU # can probably do better
278 select CPU_TLB_V4WBI if MMU
280 The ARM1022E is an implementation of the ARMv5TE architecture
281 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
282 embedded trace macrocell, and a floating-point unit.
284 Say Y if you want support for the ARM1022E processor.
289 bool "Support ARM1026EJ-S processor"
290 depends on ARCH_INTEGRATOR
292 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
293 select CPU_PABRT_NOIFAR
294 select CPU_CACHE_VIVT
296 select CPU_COPY_V4WB if MMU # can probably do better
297 select CPU_TLB_V4WBI if MMU
299 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
300 based upon the ARM10 integer core.
302 Say Y if you want support for the ARM1026EJ-S processor.
307 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
308 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
309 select CPU_32v3 if ARCH_RPC
310 select CPU_32v4 if !ARCH_RPC
312 select CPU_PABRT_NOIFAR
313 select CPU_CACHE_V4WB
314 select CPU_CACHE_VIVT
316 select CPU_COPY_V4WB if MMU
317 select CPU_TLB_V4WB if MMU
319 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
320 is available at five speeds ranging from 100 MHz to 233 MHz.
321 More information is available at
322 <http://developer.intel.com/design/strong/sa110.htm>.
324 Say Y if you want support for the SA-110 processor.
330 depends on ARCH_SA1100
334 select CPU_PABRT_NOIFAR
335 select CPU_CACHE_V4WB
336 select CPU_CACHE_VIVT
338 select CPU_TLB_V4WB if MMU
343 depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
347 select CPU_PABRT_NOIFAR
348 select CPU_CACHE_VIVT
350 select CPU_TLB_V4WBI if MMU
352 # XScale Core Version 3
355 depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
359 select CPU_PABRT_NOIFAR
360 select CPU_CACHE_VIVT
362 select CPU_TLB_V4WBI if MMU
368 depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
372 select CPU_PABRT_NOIFAR
373 select CPU_CACHE_VIVT
375 select CPU_COPY_FEROCEON if MMU
376 select CPU_TLB_FEROCEON if MMU
378 config CPU_FEROCEON_OLD_ID
379 bool "Accept early Feroceon cores with an ARM926 ID"
380 depends on CPU_FEROCEON && !CPU_ARM926T
383 This enables the usage of some old Feroceon cores
384 for which the CPU ID is equal to the ARM926 ID.
385 Relevant for Feroceon-1850 and early Feroceon-2850.
389 bool "Support ARM V6 processor"
390 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
391 default y if ARCH_MX3
392 default y if ARCH_MSM7X00A
395 select CPU_PABRT_NOIFAR
397 select CPU_CACHE_VIPT
399 select CPU_HAS_ASID if MMU
400 select CPU_COPY_V6 if MMU
401 select CPU_TLB_V6 if MMU
405 bool "Support ARM V6K processor extensions" if !SMP
407 default y if SMP && !ARCH_MX3
409 Say Y here if your ARMv6 processor supports the 'K' extension.
410 This enables the kernel to use some instructions not present
411 on previous processors, and as such a kernel build with this
412 enabled will not boot on processors with do not support these
417 bool "Support ARM V7 processor"
418 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
422 select CPU_PABRT_IFAR
424 select CPU_CACHE_VIPT
426 select CPU_HAS_ASID if MMU
427 select CPU_COPY_V6 if MMU
428 select CPU_TLB_V7 if MMU
430 # Figure out what processor architecture version we should be using.
431 # This defines the compiler instruction set which depends on the machine type.
434 select TLS_REG_EMUL if SMP || !MMU
435 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
439 select TLS_REG_EMUL if SMP || !MMU
440 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444 select TLS_REG_EMUL if SMP || !MMU
445 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
449 select TLS_REG_EMUL if SMP || !MMU
450 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
454 select TLS_REG_EMUL if !CPU_32v6K && !MMU
460 config CPU_ABRT_NOMMU
475 config CPU_ABRT_EV5TJ
484 config CPU_PABRT_IFAR
487 config CPU_PABRT_NOIFAR
497 config CPU_CACHE_V4WT
500 config CPU_CACHE_V4WB
509 config CPU_CACHE_VIVT
512 config CPU_CACHE_VIPT
516 # The copy-page model
526 config CPU_COPY_FEROCEON
532 # This selects the TLB model
536 ARM Architecture Version 3 TLB.
541 ARM Architecture Version 4 TLB with writethrough cache.
546 ARM Architecture Version 4 TLB with writeback cache.
551 ARM Architecture Version 4 TLB with writeback cache and invalidate
552 instruction cache entry.
554 config CPU_TLB_FEROCEON
557 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
570 This indicates whether the CPU has the ASID register; used to
571 tag TLB and possibly cache entries.
576 Processor has the CP15 register.
582 Processor has the CP15 register, which has MMU related registers.
588 Processor has the CP15 register, which has MPU related registers.
591 # CPU supports 36-bit I/O
596 comment "Processor Features"
599 bool "Support Thumb user binaries"
600 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
603 Say Y if you want to include kernel support for running user space
606 The Thumb instruction set is a compressed form of the standard ARM
607 instruction set resulting in smaller binaries at the expense of
608 slightly less efficient code.
610 If you don't know what this all is, saying Y is a safe choice.
613 bool "Enable ThumbEE CPU extension"
616 Say Y here if you have a CPU with the ThumbEE extension and code to
617 make use of it. Say N for code that can run on CPUs without ThumbEE.
619 config CPU_BIG_ENDIAN
620 bool "Build big-endian kernel"
621 depends on ARCH_SUPPORTS_BIG_ENDIAN
623 Say Y if you plan on running a kernel in big-endian mode.
624 Note that your board must be properly built and your board
625 port must properly enable any big-endian related features
626 of your chipset/board/processor.
628 config CPU_HIGH_VECTOR
629 depends on !MMU && CPU_CP15 && !CPU_ARM740T
630 bool "Select the High exception vector"
633 Say Y here to select high exception vector(0xFFFF0000~).
634 The exception vector can be vary depending on the platform
635 design in nommu mode. If your platform needs to select
636 high exception vector, say Y.
637 Otherwise or if you are unsure, say N, and the low exception
638 vector (0x00000000~) will be used.
640 config CPU_ICACHE_DISABLE
641 bool "Disable I-Cache (I-bit)"
642 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
644 Say Y here to disable the processor instruction cache. Unless
645 you have a reason not to or are unsure, say N.
647 config CPU_DCACHE_DISABLE
648 bool "Disable D-Cache (C-bit)"
651 Say Y here to disable the processor data cache. Unless
652 you have a reason not to or are unsure, say N.
654 config CPU_DCACHE_SIZE
656 depends on CPU_ARM740T || CPU_ARM946E
657 default 0x00001000 if CPU_ARM740T
658 default 0x00002000 # default size for ARM946E-S
660 Some cores are synthesizable to have various sized cache. For
661 ARM946E-S case, it can vary from 0KB to 1MB.
662 To support such cache operations, it is efficient to know the size
664 If your SoC is configured to have a different size, define the value
665 here with proper conditions.
667 config CPU_DCACHE_WRITETHROUGH
668 bool "Force write through D-cache"
669 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
670 default y if CPU_ARM925T
672 Say Y here to use the data cache in writethrough mode. Unless you
673 specifically require this or are unsure, say N.
675 config CPU_CACHE_ROUND_ROBIN
676 bool "Round robin I and D cache replacement algorithm"
677 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
679 Say Y here to use the predictable round-robin cache replacement
680 policy. Unless you specifically require this or are unsure, say N.
682 config CPU_BPREDICT_DISABLE
683 bool "Disable branch prediction"
684 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
686 Say Y here to disable branch prediction. If unsure, say N.
691 An SMP system using a pre-ARMv6 processor (there are apparently
692 a few prototypes like that in existence) and therefore access to
693 that required register must be emulated.
697 depends on !TLS_REG_EMUL
698 default y if SMP || CPU_32v7
700 This selects support for the CP15 thread register.
701 It is defined to be available on some ARMv6 processors (including
702 all SMP capable ARMv6's) or later processors. User space may
703 assume directly accessing that register and always obtain the
704 expected value only on ARMv7 and above.
706 config NEEDS_SYSCALL_FOR_CMPXCHG
709 SMP on a pre-ARMv6 processor? Well OK then.
710 Forget about fast user space cmpxchg support.
711 It is just not possible.
717 config CACHE_FEROCEON_L2
718 bool "Enable the Feroceon L2 cache controller"
719 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
723 This option enables the Feroceon L2 cache controller.
726 bool "Enable the L2x0 outer cache controller"
727 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
731 This option enables the L2x0 PrimeCell.