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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - arch/arm/mm/cache-l2x0.c
2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
4 * Copyright (C) 2007 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
26 #define CACHE_LINE_SIZE 32
28 static void __iomem
*l2x0_base
;
29 static DEFINE_SPINLOCK(l2x0_lock
);
30 static uint32_t l2x0_way_mask
; /* Bitmask of active ways */
32 static inline void cache_wait_way(void __iomem
*reg
, unsigned long mask
)
34 /* wait for cache operation by line or way to complete */
35 while (readl_relaxed(reg
) & mask
)
39 #ifdef CONFIG_CACHE_PL310
40 static inline void cache_wait(void __iomem
*reg
, unsigned long mask
)
42 /* cache operations by line are atomic on PL310 */
45 #define cache_wait cache_wait_way
48 static inline void cache_sync(void)
50 void __iomem
*base
= l2x0_base
;
51 writel_relaxed(0, base
+ L2X0_CACHE_SYNC
);
52 cache_wait(base
+ L2X0_CACHE_SYNC
, 1);
55 static inline void l2x0_clean_line(unsigned long addr
)
57 void __iomem
*base
= l2x0_base
;
58 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
59 writel_relaxed(addr
, base
+ L2X0_CLEAN_LINE_PA
);
62 static inline void l2x0_inv_line(unsigned long addr
)
64 void __iomem
*base
= l2x0_base
;
65 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
66 writel_relaxed(addr
, base
+ L2X0_INV_LINE_PA
);
69 #ifdef CONFIG_PL310_ERRATA_588369
70 static void debug_writel(unsigned long val
)
72 extern void omap_smc1(u32 fn
, u32 arg
);
75 * Texas Instrument secure monitor api to modify the
76 * PL310 Debug Control Register.
78 omap_smc1(0x100, val
);
81 static inline void l2x0_flush_line(unsigned long addr
)
83 void __iomem
*base
= l2x0_base
;
85 /* Clean by PA followed by Invalidate by PA */
86 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
87 writel_relaxed(addr
, base
+ L2X0_CLEAN_LINE_PA
);
88 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
89 writel_relaxed(addr
, base
+ L2X0_INV_LINE_PA
);
93 /* Optimised out for non-errata case */
94 static inline void debug_writel(unsigned long val
)
98 static inline void l2x0_flush_line(unsigned long addr
)
100 void __iomem
*base
= l2x0_base
;
101 cache_wait(base
+ L2X0_CLEAN_INV_LINE_PA
, 1);
102 writel_relaxed(addr
, base
+ L2X0_CLEAN_INV_LINE_PA
);
106 static void l2x0_cache_sync(void)
110 spin_lock_irqsave(&l2x0_lock
, flags
);
112 spin_unlock_irqrestore(&l2x0_lock
, flags
);
115 static void l2x0_flush_all(void)
120 spin_lock_irqsave(&l2x0_lock
, flags
);
121 writel_relaxed(l2x0_way_mask
, l2x0_base
+ L2X0_CLEAN_INV_WAY
);
122 cache_wait_way(l2x0_base
+ L2X0_CLEAN_INV_WAY
, l2x0_way_mask
);
124 spin_unlock_irqrestore(&l2x0_lock
, flags
);
127 static void l2x0_inv_all(void)
131 /* invalidate all ways */
132 spin_lock_irqsave(&l2x0_lock
, flags
);
133 /* Invalidating when L2 is enabled is a nono */
134 BUG_ON(readl(l2x0_base
+ L2X0_CTRL
) & 1);
135 writel_relaxed(l2x0_way_mask
, l2x0_base
+ L2X0_INV_WAY
);
136 cache_wait_way(l2x0_base
+ L2X0_INV_WAY
, l2x0_way_mask
);
138 spin_unlock_irqrestore(&l2x0_lock
, flags
);
141 static void l2x0_inv_range(unsigned long start
, unsigned long end
)
143 void __iomem
*base
= l2x0_base
;
146 spin_lock_irqsave(&l2x0_lock
, flags
);
147 if (start
& (CACHE_LINE_SIZE
- 1)) {
148 start
&= ~(CACHE_LINE_SIZE
- 1);
150 l2x0_flush_line(start
);
152 start
+= CACHE_LINE_SIZE
;
155 if (end
& (CACHE_LINE_SIZE
- 1)) {
156 end
&= ~(CACHE_LINE_SIZE
- 1);
158 l2x0_flush_line(end
);
162 while (start
< end
) {
163 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
165 while (start
< blk_end
) {
166 l2x0_inv_line(start
);
167 start
+= CACHE_LINE_SIZE
;
171 spin_unlock_irqrestore(&l2x0_lock
, flags
);
172 spin_lock_irqsave(&l2x0_lock
, flags
);
175 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
177 spin_unlock_irqrestore(&l2x0_lock
, flags
);
180 static void l2x0_clean_range(unsigned long start
, unsigned long end
)
182 void __iomem
*base
= l2x0_base
;
185 spin_lock_irqsave(&l2x0_lock
, flags
);
186 start
&= ~(CACHE_LINE_SIZE
- 1);
187 while (start
< end
) {
188 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
190 while (start
< blk_end
) {
191 l2x0_clean_line(start
);
192 start
+= CACHE_LINE_SIZE
;
196 spin_unlock_irqrestore(&l2x0_lock
, flags
);
197 spin_lock_irqsave(&l2x0_lock
, flags
);
200 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
202 spin_unlock_irqrestore(&l2x0_lock
, flags
);
205 static void l2x0_flush_range(unsigned long start
, unsigned long end
)
207 void __iomem
*base
= l2x0_base
;
210 spin_lock_irqsave(&l2x0_lock
, flags
);
211 start
&= ~(CACHE_LINE_SIZE
- 1);
212 while (start
< end
) {
213 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
216 while (start
< blk_end
) {
217 l2x0_flush_line(start
);
218 start
+= CACHE_LINE_SIZE
;
223 spin_unlock_irqrestore(&l2x0_lock
, flags
);
224 spin_lock_irqsave(&l2x0_lock
, flags
);
227 cache_wait(base
+ L2X0_CLEAN_INV_LINE_PA
, 1);
229 spin_unlock_irqrestore(&l2x0_lock
, flags
);
232 static void l2x0_disable(void)
236 spin_lock_irqsave(&l2x0_lock
, flags
);
237 writel(0, l2x0_base
+ L2X0_CTRL
);
238 spin_unlock_irqrestore(&l2x0_lock
, flags
);
241 void __init
l2x0_init(void __iomem
*base
, __u32 aux_val
, __u32 aux_mask
)
250 cache_id
= readl_relaxed(l2x0_base
+ L2X0_CACHE_ID
);
251 aux
= readl_relaxed(l2x0_base
+ L2X0_AUX_CTRL
);
256 /* Determine the number of ways */
257 switch (cache_id
& L2X0_CACHE_ID_PART_MASK
) {
258 case L2X0_CACHE_ID_PART_L310
:
265 case L2X0_CACHE_ID_PART_L210
:
266 ways
= (aux
>> 13) & 0xf;
270 /* Assume unknown chips have 8 ways */
272 type
= "L2x0 series";
276 l2x0_way_mask
= (1 << ways
) - 1;
279 * Check if l2x0 controller is already enabled.
280 * If you are booting from non-secure mode
281 * accessing the below registers will fault.
283 if (!(readl_relaxed(l2x0_base
+ L2X0_CTRL
) & 1)) {
285 /* l2x0 controller is disabled */
286 writel_relaxed(aux
, l2x0_base
+ L2X0_AUX_CTRL
);
291 writel_relaxed(1, l2x0_base
+ L2X0_CTRL
);
294 outer_cache
.inv_range
= l2x0_inv_range
;
295 outer_cache
.clean_range
= l2x0_clean_range
;
296 outer_cache
.flush_range
= l2x0_flush_range
;
297 outer_cache
.sync
= l2x0_cache_sync
;
298 outer_cache
.flush_all
= l2x0_flush_all
;
299 outer_cache
.inv_all
= l2x0_inv_all
;
300 outer_cache
.disable
= l2x0_disable
;
302 printk(KERN_INFO
"%s cache controller enabled\n", type
);
303 printk(KERN_INFO
"l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
304 ways
, cache_id
, aux
);