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1 /*
2 * linux/arch/arm/mm/cache-v3.S
3 *
4 * Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/linkage.h>
11 #include <linux/init.h>
12 #include <asm/page.h>
13 #include "proc-macros.S"
14
15 /*
16 * flush_icache_all()
17 *
18 * Unconditionally clean and invalidate the entire icache.
19 */
20 ENTRY(v3_flush_icache_all)
21 mov pc, lr
22 ENDPROC(v3_flush_icache_all)
23
24 /*
25 * flush_user_cache_all()
26 *
27 * Invalidate all cache entries in a particular address
28 * space.
29 *
30 * - mm - mm_struct describing address space
31 */
32 ENTRY(v3_flush_user_cache_all)
33 /* FALLTHROUGH */
34 /*
35 * flush_kern_cache_all()
36 *
37 * Clean and invalidate the entire cache.
38 */
39 ENTRY(v3_flush_kern_cache_all)
40 /* FALLTHROUGH */
41
42 /*
43 * flush_user_cache_range(start, end, flags)
44 *
45 * Invalidate a range of cache entries in the specified
46 * address space.
47 *
48 * - start - start address (may not be aligned)
49 * - end - end address (exclusive, may not be aligned)
50 * - flags - vma_area_struct flags describing address space
51 */
52 ENTRY(v3_flush_user_cache_range)
53 mov ip, #0
54 mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
55 mov pc, lr
56
57 /*
58 * coherent_kern_range(start, end)
59 *
60 * Ensure coherency between the Icache and the Dcache in the
61 * region described by start. If you have non-snooping
62 * Harvard caches, you need to implement this function.
63 *
64 * - start - virtual start address
65 * - end - virtual end address
66 */
67 ENTRY(v3_coherent_kern_range)
68 /* FALLTHROUGH */
69
70 /*
71 * coherent_user_range(start, end)
72 *
73 * Ensure coherency between the Icache and the Dcache in the
74 * region described by start. If you have non-snooping
75 * Harvard caches, you need to implement this function.
76 *
77 * - start - virtual start address
78 * - end - virtual end address
79 */
80 ENTRY(v3_coherent_user_range)
81 mov r0, #0
82 mov pc, lr
83
84 /*
85 * flush_kern_dcache_area(void *page, size_t size)
86 *
87 * Ensure no D cache aliasing occurs, either with itself or
88 * the I cache
89 *
90 * - addr - kernel address
91 * - size - region size
92 */
93 ENTRY(v3_flush_kern_dcache_area)
94 /* FALLTHROUGH */
95
96 /*
97 * dma_flush_range(start, end)
98 *
99 * Clean and invalidate the specified virtual address range.
100 *
101 * - start - virtual start address
102 * - end - virtual end address
103 */
104 ENTRY(v3_dma_flush_range)
105 mov r0, #0
106 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
107 mov pc, lr
108
109 /*
110 * dma_unmap_area(start, size, dir)
111 * - start - kernel virtual start address
112 * - size - size of region
113 * - dir - DMA direction
114 */
115 ENTRY(v3_dma_unmap_area)
116 teq r2, #DMA_TO_DEVICE
117 bne v3_dma_flush_range
118 /* FALLTHROUGH */
119
120 /*
121 * dma_map_area(start, size, dir)
122 * - start - kernel virtual start address
123 * - size - size of region
124 * - dir - DMA direction
125 */
126 ENTRY(v3_dma_map_area)
127 mov pc, lr
128 ENDPROC(v3_dma_unmap_area)
129 ENDPROC(v3_dma_map_area)
130
131 .globl v3_flush_kern_cache_louis
132 .equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all
133
134 __INITDATA
135
136 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
137 define_cache_functions v3