1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/mmu.c
5 * Copyright (C) 1995-2005 Russell King
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
11 #include <linux/mman.h>
12 #include <linux/nodemask.h>
13 #include <linux/memblock.h>
15 #include <linux/vmalloc.h>
16 #include <linux/sizes.h>
19 #include <asm/cputype.h>
20 #include <asm/cachetype.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/smp_plat.h>
25 #include <asm/highmem.h>
26 #include <asm/system_info.h>
27 #include <asm/traps.h>
28 #include <asm/procinfo.h>
29 #include <asm/memory.h>
30 #include <asm/pgalloc.h>
31 #include <asm/kasan_def.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/pci.h>
36 #include <asm/fixmap.h>
42 extern unsigned long __atags_pointer
;
45 * empty_zero_page is a special page that is used for
46 * zero-initialized data and COW.
48 struct page
*empty_zero_page
;
49 EXPORT_SYMBOL(empty_zero_page
);
52 * The pmd table for the upper-most set of pages.
56 pmdval_t user_pmd_table
= _PAGE_USER_TABLE
;
58 #define CPOLICY_UNCACHED 0
59 #define CPOLICY_BUFFERED 1
60 #define CPOLICY_WRITETHROUGH 2
61 #define CPOLICY_WRITEBACK 3
62 #define CPOLICY_WRITEALLOC 4
64 static unsigned int cachepolicy __initdata
= CPOLICY_WRITEBACK
;
65 static unsigned int ecc_mask __initdata
= 0;
67 pgprot_t pgprot_kernel
;
69 EXPORT_SYMBOL(pgprot_user
);
70 EXPORT_SYMBOL(pgprot_kernel
);
73 const char policy
[16];
79 static struct cachepolicy cache_policies
[] __initdata
= {
83 .pmd
= PMD_SECT_UNCACHED
,
84 .pte
= L_PTE_MT_UNCACHED
,
88 .pmd
= PMD_SECT_BUFFERED
,
89 .pte
= L_PTE_MT_BUFFERABLE
,
91 .policy
= "writethrough",
94 .pte
= L_PTE_MT_WRITETHROUGH
,
96 .policy
= "writeback",
99 .pte
= L_PTE_MT_WRITEBACK
,
101 .policy
= "writealloc",
103 .pmd
= PMD_SECT_WBWA
,
104 .pte
= L_PTE_MT_WRITEALLOC
,
108 #ifdef CONFIG_CPU_CP15
109 static unsigned long initial_pmd_value __initdata
= 0;
112 * Initialise the cache_policy variable with the initial state specified
113 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
114 * the C code sets the page tables up with the same policy as the head
115 * assembly code, which avoids an illegal state where the TLBs can get
116 * confused. See comments in early_cachepolicy() for more information.
118 void __init
init_default_cache_policy(unsigned long pmd
)
122 initial_pmd_value
= pmd
;
124 pmd
&= PMD_SECT_CACHE_MASK
;
126 for (i
= 0; i
< ARRAY_SIZE(cache_policies
); i
++)
127 if (cache_policies
[i
].pmd
== pmd
) {
132 if (i
== ARRAY_SIZE(cache_policies
))
133 pr_err("ERROR: could not find cache policy\n");
137 * These are useful for identifying cache coherency problems by allowing
138 * the cache or the cache and writebuffer to be turned off. (Note: the
139 * write buffer should not be on and the cache off).
141 static int __init
early_cachepolicy(char *p
)
143 int i
, selected
= -1;
145 for (i
= 0; i
< ARRAY_SIZE(cache_policies
); i
++) {
146 int len
= strlen(cache_policies
[i
].policy
);
148 if (memcmp(p
, cache_policies
[i
].policy
, len
) == 0) {
155 pr_err("ERROR: unknown or unsupported cache policy\n");
158 * This restriction is partly to do with the way we boot; it is
159 * unpredictable to have memory mapped using two different sets of
160 * memory attributes (shared, type, and cache attribs). We can not
161 * change these attributes once the initial assembly has setup the
164 if (cpu_architecture() >= CPU_ARCH_ARMv6
&& selected
!= cachepolicy
) {
165 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
166 cache_policies
[cachepolicy
].policy
);
170 if (selected
!= cachepolicy
) {
171 unsigned long cr
= __clear_cr(cache_policies
[selected
].cr_mask
);
172 cachepolicy
= selected
;
178 early_param("cachepolicy", early_cachepolicy
);
180 static int __init
early_nocache(char *__unused
)
182 char *p
= "buffered";
183 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p
);
184 early_cachepolicy(p
);
187 early_param("nocache", early_nocache
);
189 static int __init
early_nowrite(char *__unused
)
191 char *p
= "uncached";
192 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p
);
193 early_cachepolicy(p
);
196 early_param("nowb", early_nowrite
);
198 #ifndef CONFIG_ARM_LPAE
199 static int __init
early_ecc(char *p
)
201 if (memcmp(p
, "on", 2) == 0)
202 ecc_mask
= PMD_PROTECTION
;
203 else if (memcmp(p
, "off", 3) == 0)
207 early_param("ecc", early_ecc
);
210 #else /* ifdef CONFIG_CPU_CP15 */
212 static int __init
early_cachepolicy(char *p
)
214 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
217 early_param("cachepolicy", early_cachepolicy
);
219 static int __init
noalign_setup(char *__unused
)
221 pr_warn("noalign kernel parameter not supported without cp15\n");
224 __setup("noalign", noalign_setup
);
226 #endif /* ifdef CONFIG_CPU_CP15 / else */
228 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
229 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
230 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
232 static struct mem_type mem_types
[] __ro_after_init
= {
233 [MT_DEVICE
] = { /* Strongly ordered / ARMv6 shared device */
234 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_SHARED
|
236 .prot_l1
= PMD_TYPE_TABLE
,
237 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_S
,
240 [MT_DEVICE_NONSHARED
] = { /* ARMv6 non-shared device */
241 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_NONSHARED
,
242 .prot_l1
= PMD_TYPE_TABLE
,
243 .prot_sect
= PROT_SECT_DEVICE
,
246 [MT_DEVICE_CACHED
] = { /* ioremap_cache */
247 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_CACHED
,
248 .prot_l1
= PMD_TYPE_TABLE
,
249 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_WB
,
252 [MT_DEVICE_WC
] = { /* ioremap_wc */
253 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_WC
,
254 .prot_l1
= PMD_TYPE_TABLE
,
255 .prot_sect
= PROT_SECT_DEVICE
,
259 .prot_pte
= PROT_PTE_DEVICE
,
260 .prot_l1
= PMD_TYPE_TABLE
,
261 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
265 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
266 .domain
= DOMAIN_KERNEL
,
268 #ifndef CONFIG_ARM_LPAE
270 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
| PMD_SECT_MINICACHE
,
271 .domain
= DOMAIN_KERNEL
,
275 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
277 .prot_l1
= PMD_TYPE_TABLE
,
278 .domain
= DOMAIN_VECTORS
,
280 [MT_HIGH_VECTORS
] = {
281 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
282 L_PTE_USER
| L_PTE_RDONLY
,
283 .prot_l1
= PMD_TYPE_TABLE
,
284 .domain
= DOMAIN_VECTORS
,
287 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
,
288 .prot_l1
= PMD_TYPE_TABLE
,
289 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
290 .domain
= DOMAIN_KERNEL
,
293 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
295 .prot_l1
= PMD_TYPE_TABLE
,
296 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
297 .domain
= DOMAIN_KERNEL
,
300 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
301 L_PTE_XN
| L_PTE_RDONLY
,
302 .prot_l1
= PMD_TYPE_TABLE
,
303 .prot_sect
= PMD_TYPE_SECT
,
304 .domain
= DOMAIN_KERNEL
,
307 .prot_sect
= PMD_TYPE_SECT
,
308 .domain
= DOMAIN_KERNEL
,
310 [MT_MEMORY_RWX_NONCACHED
] = {
311 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
313 .prot_l1
= PMD_TYPE_TABLE
,
314 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
315 .domain
= DOMAIN_KERNEL
,
317 [MT_MEMORY_RW_DTCM
] = {
318 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
320 .prot_l1
= PMD_TYPE_TABLE
,
321 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
322 .domain
= DOMAIN_KERNEL
,
324 [MT_MEMORY_RWX_ITCM
] = {
325 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
,
326 .prot_l1
= PMD_TYPE_TABLE
,
327 .domain
= DOMAIN_KERNEL
,
329 [MT_MEMORY_RW_SO
] = {
330 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
331 L_PTE_MT_UNCACHED
| L_PTE_XN
,
332 .prot_l1
= PMD_TYPE_TABLE
,
333 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
| PMD_SECT_S
|
334 PMD_SECT_UNCACHED
| PMD_SECT_XN
,
335 .domain
= DOMAIN_KERNEL
,
337 [MT_MEMORY_DMA_READY
] = {
338 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
340 .prot_l1
= PMD_TYPE_TABLE
,
341 .domain
= DOMAIN_KERNEL
,
345 const struct mem_type
*get_mem_type(unsigned int type
)
347 return type
< ARRAY_SIZE(mem_types
) ? &mem_types
[type
] : NULL
;
349 EXPORT_SYMBOL(get_mem_type
);
351 static pte_t
*(*pte_offset_fixmap
)(pmd_t
*dir
, unsigned long addr
);
353 static pte_t bm_pte
[PTRS_PER_PTE
+ PTE_HWTABLE_PTRS
]
354 __aligned(PTE_HWTABLE_OFF
+ PTE_HWTABLE_SIZE
) __initdata
;
356 static pte_t
* __init
pte_offset_early_fixmap(pmd_t
*dir
, unsigned long addr
)
358 return &bm_pte
[pte_index(addr
)];
361 static pte_t
*pte_offset_late_fixmap(pmd_t
*dir
, unsigned long addr
)
363 return pte_offset_kernel(dir
, addr
);
366 static inline pmd_t
* __init
fixmap_pmd(unsigned long addr
)
368 return pmd_off_k(addr
);
371 void __init
early_fixmap_init(void)
376 * The early fixmap range spans multiple pmds, for which
377 * we are not prepared:
379 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region
) >> PMD_SHIFT
)
380 != FIXADDR_TOP
>> PMD_SHIFT
);
382 pmd
= fixmap_pmd(FIXADDR_TOP
);
383 pmd_populate_kernel(&init_mm
, pmd
, bm_pte
);
385 pte_offset_fixmap
= pte_offset_early_fixmap
;
389 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
390 * As a result, this can only be called with preemption disabled, as under
393 void __set_fixmap(enum fixed_addresses idx
, phys_addr_t phys
, pgprot_t prot
)
395 unsigned long vaddr
= __fix_to_virt(idx
);
396 pte_t
*pte
= pte_offset_fixmap(pmd_off_k(vaddr
), vaddr
);
398 /* Make sure fixmap region does not exceed available allocation. */
399 BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses
) < FIXADDR_START
);
400 BUG_ON(idx
>= __end_of_fixed_addresses
);
402 /* We support only device mappings before pgprot_kernel is set. */
403 if (WARN_ON(pgprot_val(prot
) != pgprot_val(FIXMAP_PAGE_IO
) &&
404 pgprot_val(prot
) && pgprot_val(pgprot_kernel
) == 0))
407 if (pgprot_val(prot
))
408 set_pte_at(NULL
, vaddr
, pte
,
409 pfn_pte(phys
>> PAGE_SHIFT
, prot
));
411 pte_clear(NULL
, vaddr
, pte
);
412 local_flush_tlb_kernel_range(vaddr
, vaddr
+ PAGE_SIZE
);
416 * Adjust the PMD section entries according to the CPU in use.
418 static void __init
build_mem_type_table(void)
420 struct cachepolicy
*cp
;
421 unsigned int cr
= get_cr();
422 pteval_t user_pgprot
, kern_pgprot
, vecs_pgprot
;
423 int cpu_arch
= cpu_architecture();
426 if (cpu_arch
< CPU_ARCH_ARMv6
) {
427 #if defined(CONFIG_CPU_DCACHE_DISABLE)
428 if (cachepolicy
> CPOLICY_BUFFERED
)
429 cachepolicy
= CPOLICY_BUFFERED
;
430 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
431 if (cachepolicy
> CPOLICY_WRITETHROUGH
)
432 cachepolicy
= CPOLICY_WRITETHROUGH
;
435 if (cpu_arch
< CPU_ARCH_ARMv5
) {
436 if (cachepolicy
>= CPOLICY_WRITEALLOC
)
437 cachepolicy
= CPOLICY_WRITEBACK
;
442 if (cachepolicy
!= CPOLICY_WRITEALLOC
) {
443 pr_warn("Forcing write-allocate cache policy for SMP\n");
444 cachepolicy
= CPOLICY_WRITEALLOC
;
446 if (!(initial_pmd_value
& PMD_SECT_S
)) {
447 pr_warn("Forcing shared mappings for SMP\n");
448 initial_pmd_value
|= PMD_SECT_S
;
453 * Strip out features not present on earlier architectures.
454 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
455 * without extended page tables don't have the 'Shared' bit.
457 if (cpu_arch
< CPU_ARCH_ARMv5
)
458 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
459 mem_types
[i
].prot_sect
&= ~PMD_SECT_TEX(7);
460 if ((cpu_arch
< CPU_ARCH_ARMv6
|| !(cr
& CR_XP
)) && !cpu_is_xsc3())
461 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
462 mem_types
[i
].prot_sect
&= ~PMD_SECT_S
;
465 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
466 * "update-able on write" bit on ARM610). However, Xscale and
467 * Xscale3 require this bit to be cleared.
469 if (cpu_is_xscale_family()) {
470 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
471 mem_types
[i
].prot_sect
&= ~PMD_BIT4
;
472 mem_types
[i
].prot_l1
&= ~PMD_BIT4
;
474 } else if (cpu_arch
< CPU_ARCH_ARMv6
) {
475 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
476 if (mem_types
[i
].prot_l1
)
477 mem_types
[i
].prot_l1
|= PMD_BIT4
;
478 if (mem_types
[i
].prot_sect
)
479 mem_types
[i
].prot_sect
|= PMD_BIT4
;
484 * Mark the device areas according to the CPU/architecture.
486 if (cpu_is_xsc3() || (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
))) {
487 if (!cpu_is_xsc3()) {
489 * Mark device regions on ARMv6+ as execute-never
490 * to prevent speculative instruction fetches.
492 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_XN
;
493 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_XN
;
494 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_XN
;
495 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_XN
;
497 /* Also setup NX memory mapping */
498 mem_types
[MT_MEMORY_RW
].prot_sect
|= PMD_SECT_XN
;
499 mem_types
[MT_MEMORY_RO
].prot_sect
|= PMD_SECT_XN
;
501 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
503 * For ARMv7 with TEX remapping,
504 * - shared device is SXCB=1100
505 * - nonshared device is SXCB=0100
506 * - write combine device mem is SXCB=0001
507 * (Uncached Normal memory)
509 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1);
510 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(1);
511 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
512 } else if (cpu_is_xsc3()) {
515 * - shared device is TEXCB=00101
516 * - nonshared device is TEXCB=01000
517 * - write combine device mem is TEXCB=00100
518 * (Inner/Outer Uncacheable in xsc3 parlance)
520 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED
;
521 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
522 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
525 * For ARMv6 and ARMv7 without TEX remapping,
526 * - shared device is TEXCB=00001
527 * - nonshared device is TEXCB=01000
528 * - write combine device mem is TEXCB=00100
529 * (Uncached Normal in ARMv6 parlance).
531 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_BUFFERED
;
532 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
533 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
537 * On others, write combining is "Uncached/Buffered"
539 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
543 * Now deal with the memory-type mappings
545 cp
= &cache_policies
[cachepolicy
];
546 vecs_pgprot
= kern_pgprot
= user_pgprot
= cp
->pte
;
548 #ifndef CONFIG_ARM_LPAE
550 * We don't use domains on ARMv6 (since this causes problems with
551 * v6/v7 kernels), so we must use a separate memory type for user
552 * r/o, kernel r/w to map the vectors page.
554 if (cpu_arch
== CPU_ARCH_ARMv6
)
555 vecs_pgprot
|= L_PTE_MT_VECTORS
;
558 * Check is it with support for the PXN bit
559 * in the Short-descriptor translation table format descriptors.
561 if (cpu_arch
== CPU_ARCH_ARMv7
&&
562 (read_cpuid_ext(CPUID_EXT_MMFR0
) & 0xF) >= 4) {
563 user_pmd_table
|= PMD_PXNTABLE
;
568 * ARMv6 and above have extended page tables.
570 if (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
)) {
571 #ifndef CONFIG_ARM_LPAE
573 * Mark cache clean areas and XIP ROM read only
574 * from SVC mode and no access from userspace.
576 mem_types
[MT_ROM
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
577 mem_types
[MT_MINICLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
578 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
579 mem_types
[MT_MEMORY_RO
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
583 * If the initial page tables were created with the S bit
584 * set, then we need to do the same here for the same
585 * reasons given in early_cachepolicy().
587 if (initial_pmd_value
& PMD_SECT_S
) {
588 user_pgprot
|= L_PTE_SHARED
;
589 kern_pgprot
|= L_PTE_SHARED
;
590 vecs_pgprot
|= L_PTE_SHARED
;
591 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_S
;
592 mem_types
[MT_DEVICE_WC
].prot_pte
|= L_PTE_SHARED
;
593 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_S
;
594 mem_types
[MT_DEVICE_CACHED
].prot_pte
|= L_PTE_SHARED
;
595 mem_types
[MT_MEMORY_RWX
].prot_sect
|= PMD_SECT_S
;
596 mem_types
[MT_MEMORY_RWX
].prot_pte
|= L_PTE_SHARED
;
597 mem_types
[MT_MEMORY_RW
].prot_sect
|= PMD_SECT_S
;
598 mem_types
[MT_MEMORY_RW
].prot_pte
|= L_PTE_SHARED
;
599 mem_types
[MT_MEMORY_RO
].prot_sect
|= PMD_SECT_S
;
600 mem_types
[MT_MEMORY_RO
].prot_pte
|= L_PTE_SHARED
;
601 mem_types
[MT_MEMORY_DMA_READY
].prot_pte
|= L_PTE_SHARED
;
602 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|= PMD_SECT_S
;
603 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_pte
|= L_PTE_SHARED
;
608 * Non-cacheable Normal - intended for memory areas that must
609 * not cause dirty cache line writebacks when used
611 if (cpu_arch
>= CPU_ARCH_ARMv6
) {
612 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
613 /* Non-cacheable Normal is XCB = 001 */
614 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|=
617 /* For both ARMv6 and non-TEX-remapping ARMv7 */
618 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|=
622 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|= PMD_SECT_BUFFERABLE
;
625 #ifdef CONFIG_ARM_LPAE
627 * Do not generate access flag faults for the kernel mappings.
629 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
630 mem_types
[i
].prot_pte
|= PTE_EXT_AF
;
631 if (mem_types
[i
].prot_sect
)
632 mem_types
[i
].prot_sect
|= PMD_SECT_AF
;
634 kern_pgprot
|= PTE_EXT_AF
;
635 vecs_pgprot
|= PTE_EXT_AF
;
638 * Set PXN for user mappings
640 user_pgprot
|= PTE_EXT_PXN
;
643 for (i
= 0; i
< 16; i
++) {
644 pteval_t v
= pgprot_val(protection_map
[i
]);
645 protection_map
[i
] = __pgprot(v
| user_pgprot
);
648 mem_types
[MT_LOW_VECTORS
].prot_pte
|= vecs_pgprot
;
649 mem_types
[MT_HIGH_VECTORS
].prot_pte
|= vecs_pgprot
;
651 pgprot_user
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
| user_pgprot
);
652 pgprot_kernel
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
|
653 L_PTE_DIRTY
| kern_pgprot
);
655 mem_types
[MT_LOW_VECTORS
].prot_l1
|= ecc_mask
;
656 mem_types
[MT_HIGH_VECTORS
].prot_l1
|= ecc_mask
;
657 mem_types
[MT_MEMORY_RWX
].prot_sect
|= ecc_mask
| cp
->pmd
;
658 mem_types
[MT_MEMORY_RWX
].prot_pte
|= kern_pgprot
;
659 mem_types
[MT_MEMORY_RW
].prot_sect
|= ecc_mask
| cp
->pmd
;
660 mem_types
[MT_MEMORY_RW
].prot_pte
|= kern_pgprot
;
661 mem_types
[MT_MEMORY_RO
].prot_sect
|= ecc_mask
| cp
->pmd
;
662 mem_types
[MT_MEMORY_RO
].prot_pte
|= kern_pgprot
;
663 mem_types
[MT_MEMORY_DMA_READY
].prot_pte
|= kern_pgprot
;
664 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|= ecc_mask
;
665 mem_types
[MT_ROM
].prot_sect
|= cp
->pmd
;
669 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WT
;
673 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WB
;
676 pr_info("Memory policy: %sData cache %s\n",
677 ecc_mask
? "ECC enabled, " : "", cp
->policy
);
679 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
680 struct mem_type
*t
= &mem_types
[i
];
682 t
->prot_l1
|= PMD_DOMAIN(t
->domain
);
684 t
->prot_sect
|= PMD_DOMAIN(t
->domain
);
688 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
689 pgprot_t
phys_mem_access_prot(struct file
*file
, unsigned long pfn
,
690 unsigned long size
, pgprot_t vma_prot
)
693 return pgprot_noncached(vma_prot
);
694 else if (file
->f_flags
& O_SYNC
)
695 return pgprot_writecombine(vma_prot
);
698 EXPORT_SYMBOL(phys_mem_access_prot
);
701 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
703 static void __init
*early_alloc(unsigned long sz
)
705 void *ptr
= memblock_alloc(sz
, sz
);
708 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
714 static void *__init
late_alloc(unsigned long sz
)
716 void *ptr
= (void *)__get_free_pages(GFP_PGTABLE_KERNEL
, get_order(sz
));
718 if (!ptr
|| !pgtable_pte_page_ctor(virt_to_page(ptr
)))
723 static pte_t
* __init
arm_pte_alloc(pmd_t
*pmd
, unsigned long addr
,
725 void *(*alloc
)(unsigned long sz
))
727 if (pmd_none(*pmd
)) {
728 pte_t
*pte
= alloc(PTE_HWTABLE_OFF
+ PTE_HWTABLE_SIZE
);
729 __pmd_populate(pmd
, __pa(pte
), prot
);
731 BUG_ON(pmd_bad(*pmd
));
732 return pte_offset_kernel(pmd
, addr
);
735 static pte_t
* __init
early_pte_alloc(pmd_t
*pmd
, unsigned long addr
,
738 return arm_pte_alloc(pmd
, addr
, prot
, early_alloc
);
741 static void __init
alloc_init_pte(pmd_t
*pmd
, unsigned long addr
,
742 unsigned long end
, unsigned long pfn
,
743 const struct mem_type
*type
,
744 void *(*alloc
)(unsigned long sz
),
747 pte_t
*pte
= arm_pte_alloc(pmd
, addr
, type
->prot_l1
, alloc
);
749 set_pte_ext(pte
, pfn_pte(pfn
, __pgprot(type
->prot_pte
)),
750 ng
? PTE_EXT_NG
: 0);
752 } while (pte
++, addr
+= PAGE_SIZE
, addr
!= end
);
755 static void __init
__map_init_section(pmd_t
*pmd
, unsigned long addr
,
756 unsigned long end
, phys_addr_t phys
,
757 const struct mem_type
*type
, bool ng
)
761 #ifndef CONFIG_ARM_LPAE
763 * In classic MMU format, puds and pmds are folded in to
764 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
765 * group of L1 entries making up one logical pointer to
766 * an L2 table (2MB), where as PMDs refer to the individual
767 * L1 entries (1MB). Hence increment to get the correct
768 * offset for odd 1MB sections.
769 * (See arch/arm/include/asm/pgtable-2level.h)
771 if (addr
& SECTION_SIZE
)
775 *pmd
= __pmd(phys
| type
->prot_sect
| (ng
? PMD_SECT_nG
: 0));
776 phys
+= SECTION_SIZE
;
777 } while (pmd
++, addr
+= SECTION_SIZE
, addr
!= end
);
782 static void __init
alloc_init_pmd(pud_t
*pud
, unsigned long addr
,
783 unsigned long end
, phys_addr_t phys
,
784 const struct mem_type
*type
,
785 void *(*alloc
)(unsigned long sz
), bool ng
)
787 pmd_t
*pmd
= pmd_offset(pud
, addr
);
792 * With LPAE, we must loop over to map
793 * all the pmds for the given range.
795 next
= pmd_addr_end(addr
, end
);
798 * Try a section mapping - addr, next and phys must all be
799 * aligned to a section boundary.
801 if (type
->prot_sect
&&
802 ((addr
| next
| phys
) & ~SECTION_MASK
) == 0) {
803 __map_init_section(pmd
, addr
, next
, phys
, type
, ng
);
805 alloc_init_pte(pmd
, addr
, next
,
806 __phys_to_pfn(phys
), type
, alloc
, ng
);
811 } while (pmd
++, addr
= next
, addr
!= end
);
814 static void __init
alloc_init_pud(p4d_t
*p4d
, unsigned long addr
,
815 unsigned long end
, phys_addr_t phys
,
816 const struct mem_type
*type
,
817 void *(*alloc
)(unsigned long sz
), bool ng
)
819 pud_t
*pud
= pud_offset(p4d
, addr
);
823 next
= pud_addr_end(addr
, end
);
824 alloc_init_pmd(pud
, addr
, next
, phys
, type
, alloc
, ng
);
826 } while (pud
++, addr
= next
, addr
!= end
);
829 static void __init
alloc_init_p4d(pgd_t
*pgd
, unsigned long addr
,
830 unsigned long end
, phys_addr_t phys
,
831 const struct mem_type
*type
,
832 void *(*alloc
)(unsigned long sz
), bool ng
)
834 p4d_t
*p4d
= p4d_offset(pgd
, addr
);
838 next
= p4d_addr_end(addr
, end
);
839 alloc_init_pud(p4d
, addr
, next
, phys
, type
, alloc
, ng
);
841 } while (p4d
++, addr
= next
, addr
!= end
);
844 #ifndef CONFIG_ARM_LPAE
845 static void __init
create_36bit_mapping(struct mm_struct
*mm
,
847 const struct mem_type
*type
,
850 unsigned long addr
, length
, end
;
855 phys
= __pfn_to_phys(md
->pfn
);
856 length
= PAGE_ALIGN(md
->length
);
858 if (!(cpu_architecture() >= CPU_ARCH_ARMv6
|| cpu_is_xsc3())) {
859 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
860 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
864 /* N.B. ARMv6 supersections are only defined to work with domain 0.
865 * Since domain assignments can in fact be arbitrary, the
866 * 'domain == 0' check below is required to insure that ARMv6
867 * supersections are only allocated for domain 0 regardless
868 * of the actual domain assignments in use.
871 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
872 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
876 if ((addr
| length
| __pfn_to_phys(md
->pfn
)) & ~SUPERSECTION_MASK
) {
877 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
878 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
883 * Shift bits [35:32] of address into bits [23:20] of PMD
886 phys
|= (((md
->pfn
>> (32 - PAGE_SHIFT
)) & 0xF) << 20);
888 pgd
= pgd_offset(mm
, addr
);
891 p4d_t
*p4d
= p4d_offset(pgd
, addr
);
892 pud_t
*pud
= pud_offset(p4d
, addr
);
893 pmd_t
*pmd
= pmd_offset(pud
, addr
);
896 for (i
= 0; i
< 16; i
++)
897 *pmd
++ = __pmd(phys
| type
->prot_sect
| PMD_SECT_SUPER
|
898 (ng
? PMD_SECT_nG
: 0));
900 addr
+= SUPERSECTION_SIZE
;
901 phys
+= SUPERSECTION_SIZE
;
902 pgd
+= SUPERSECTION_SIZE
>> PGDIR_SHIFT
;
903 } while (addr
!= end
);
905 #endif /* !CONFIG_ARM_LPAE */
907 static void __init
__create_mapping(struct mm_struct
*mm
, struct map_desc
*md
,
908 void *(*alloc
)(unsigned long sz
),
911 unsigned long addr
, length
, end
;
913 const struct mem_type
*type
;
916 type
= &mem_types
[md
->type
];
918 #ifndef CONFIG_ARM_LPAE
920 * Catch 36-bit addresses
922 if (md
->pfn
>= 0x100000) {
923 create_36bit_mapping(mm
, md
, type
, ng
);
928 addr
= md
->virtual & PAGE_MASK
;
929 phys
= __pfn_to_phys(md
->pfn
);
930 length
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
932 if (type
->prot_l1
== 0 && ((addr
| phys
| length
) & ~SECTION_MASK
)) {
933 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
934 (long long)__pfn_to_phys(md
->pfn
), addr
);
938 pgd
= pgd_offset(mm
, addr
);
941 unsigned long next
= pgd_addr_end(addr
, end
);
943 alloc_init_p4d(pgd
, addr
, next
, phys
, type
, alloc
, ng
);
947 } while (pgd
++, addr
!= end
);
951 * Create the page directory entries and any necessary
952 * page tables for the mapping specified by `md'. We
953 * are able to cope here with varying sizes and address
954 * offsets, and we take full advantage of sections and
957 static void __init
create_mapping(struct map_desc
*md
)
959 if (md
->virtual != vectors_base() && md
->virtual < TASK_SIZE
) {
960 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
961 (long long)__pfn_to_phys((u64
)md
->pfn
), md
->virtual);
965 if (md
->type
== MT_DEVICE
&&
966 md
->virtual >= PAGE_OFFSET
&& md
->virtual < FIXADDR_START
&&
967 (md
->virtual < VMALLOC_START
|| md
->virtual >= VMALLOC_END
)) {
968 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
969 (long long)__pfn_to_phys((u64
)md
->pfn
), md
->virtual);
972 __create_mapping(&init_mm
, md
, early_alloc
, false);
975 void __init
create_mapping_late(struct mm_struct
*mm
, struct map_desc
*md
,
978 #ifdef CONFIG_ARM_LPAE
982 p4d
= p4d_alloc(mm
, pgd_offset(mm
, md
->virtual), md
->virtual);
985 pud
= pud_alloc(mm
, p4d
, md
->virtual);
988 pmd_alloc(mm
, pud
, 0);
990 __create_mapping(mm
, md
, late_alloc
, ng
);
994 * Create the architecture specific mappings
996 void __init
iotable_init(struct map_desc
*io_desc
, int nr
)
999 struct vm_struct
*vm
;
1000 struct static_vm
*svm
;
1005 svm
= memblock_alloc(sizeof(*svm
) * nr
, __alignof__(*svm
));
1007 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1008 __func__
, sizeof(*svm
) * nr
, __alignof__(*svm
));
1010 for (md
= io_desc
; nr
; md
++, nr
--) {
1014 vm
->addr
= (void *)(md
->virtual & PAGE_MASK
);
1015 vm
->size
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
1016 vm
->phys_addr
= __pfn_to_phys(md
->pfn
);
1017 vm
->flags
= VM_IOREMAP
| VM_ARM_STATIC_MAPPING
;
1018 vm
->flags
|= VM_ARM_MTYPE(md
->type
);
1019 vm
->caller
= iotable_init
;
1020 add_static_vm_early(svm
++);
1024 void __init
vm_reserve_area_early(unsigned long addr
, unsigned long size
,
1027 struct vm_struct
*vm
;
1028 struct static_vm
*svm
;
1030 svm
= memblock_alloc(sizeof(*svm
), __alignof__(*svm
));
1032 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1033 __func__
, sizeof(*svm
), __alignof__(*svm
));
1036 vm
->addr
= (void *)addr
;
1038 vm
->flags
= VM_IOREMAP
| VM_ARM_EMPTY_MAPPING
;
1039 vm
->caller
= caller
;
1040 add_static_vm_early(svm
);
1043 #ifndef CONFIG_ARM_LPAE
1046 * The Linux PMD is made of two consecutive section entries covering 2MB
1047 * (see definition in include/asm/pgtable-2level.h). However a call to
1048 * create_mapping() may optimize static mappings by using individual
1049 * 1MB section mappings. This leaves the actual PMD potentially half
1050 * initialized if the top or bottom section entry isn't used, leaving it
1051 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1052 * the virtual space left free by that unused section entry.
1054 * Let's avoid the issue by inserting dummy vm entries covering the unused
1055 * PMD halves once the static mappings are in place.
1058 static void __init
pmd_empty_section_gap(unsigned long addr
)
1060 vm_reserve_area_early(addr
, SECTION_SIZE
, pmd_empty_section_gap
);
1063 static void __init
fill_pmd_gaps(void)
1065 struct static_vm
*svm
;
1066 struct vm_struct
*vm
;
1067 unsigned long addr
, next
= 0;
1070 list_for_each_entry(svm
, &static_vmlist
, list
) {
1072 addr
= (unsigned long)vm
->addr
;
1077 * Check if this vm starts on an odd section boundary.
1078 * If so and the first section entry for this PMD is free
1079 * then we block the corresponding virtual address.
1081 if ((addr
& ~PMD_MASK
) == SECTION_SIZE
) {
1082 pmd
= pmd_off_k(addr
);
1084 pmd_empty_section_gap(addr
& PMD_MASK
);
1088 * Then check if this vm ends on an odd section boundary.
1089 * If so and the second section entry for this PMD is empty
1090 * then we block the corresponding virtual address.
1093 if ((addr
& ~PMD_MASK
) == SECTION_SIZE
) {
1094 pmd
= pmd_off_k(addr
) + 1;
1096 pmd_empty_section_gap(addr
);
1099 /* no need to look at any vm entry until we hit the next PMD */
1100 next
= (addr
+ PMD_SIZE
- 1) & PMD_MASK
;
1105 #define fill_pmd_gaps() do { } while (0)
1108 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1109 static void __init
pci_reserve_io(void)
1111 struct static_vm
*svm
;
1113 svm
= find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE
);
1117 vm_reserve_area_early(PCI_IO_VIRT_BASE
, SZ_2M
, pci_reserve_io
);
1120 #define pci_reserve_io() do { } while (0)
1123 #ifdef CONFIG_DEBUG_LL
1124 void __init
debug_ll_io_init(void)
1126 struct map_desc map
;
1128 debug_ll_addr(&map
.pfn
, &map
.virtual);
1129 if (!map
.pfn
|| !map
.virtual)
1131 map
.pfn
= __phys_to_pfn(map
.pfn
);
1132 map
.virtual &= PAGE_MASK
;
1133 map
.length
= PAGE_SIZE
;
1134 map
.type
= MT_DEVICE
;
1135 iotable_init(&map
, 1);
1139 static unsigned long __initdata vmalloc_size
= 240 * SZ_1M
;
1142 * vmalloc=size forces the vmalloc area to be exactly 'size'
1143 * bytes. This can be used to increase (or decrease) the vmalloc
1144 * area - the default is 240MiB.
1146 static int __init
early_vmalloc(char *arg
)
1148 unsigned long vmalloc_reserve
= memparse(arg
, NULL
);
1149 unsigned long vmalloc_max
;
1151 if (vmalloc_reserve
< SZ_16M
) {
1152 vmalloc_reserve
= SZ_16M
;
1153 pr_warn("vmalloc area is too small, limiting to %luMiB\n",
1154 vmalloc_reserve
>> 20);
1157 vmalloc_max
= VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
+ VMALLOC_OFFSET
);
1158 if (vmalloc_reserve
> vmalloc_max
) {
1159 vmalloc_reserve
= vmalloc_max
;
1160 pr_warn("vmalloc area is too big, limiting to %luMiB\n",
1161 vmalloc_reserve
>> 20);
1164 vmalloc_size
= vmalloc_reserve
;
1167 early_param("vmalloc", early_vmalloc
);
1169 phys_addr_t arm_lowmem_limit __initdata
= 0;
1171 void __init
adjust_lowmem_bounds(void)
1173 phys_addr_t block_start
, block_end
, memblock_limit
= 0;
1174 u64 vmalloc_limit
, i
;
1175 phys_addr_t lowmem_limit
= 0;
1178 * Let's use our own (unoptimized) equivalent of __pa() that is
1179 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1180 * The result is used as the upper bound on physical memory address
1181 * and may itself be outside the valid range for which phys_addr_t
1182 * and therefore __pa() is defined.
1184 vmalloc_limit
= (u64
)VMALLOC_END
- vmalloc_size
- VMALLOC_OFFSET
-
1185 PAGE_OFFSET
+ PHYS_OFFSET
;
1188 * The first usable region must be PMD aligned. Mark its start
1189 * as MEMBLOCK_NOMAP if it isn't
1191 for_each_mem_range(i
, &block_start
, &block_end
) {
1192 if (!IS_ALIGNED(block_start
, PMD_SIZE
)) {
1195 len
= round_up(block_start
, PMD_SIZE
) - block_start
;
1196 memblock_mark_nomap(block_start
, len
);
1201 for_each_mem_range(i
, &block_start
, &block_end
) {
1202 if (block_start
< vmalloc_limit
) {
1203 if (block_end
> lowmem_limit
)
1205 * Compare as u64 to ensure vmalloc_limit does
1206 * not get truncated. block_end should always
1207 * fit in phys_addr_t so there should be no
1208 * issue with assignment.
1210 lowmem_limit
= min_t(u64
,
1215 * Find the first non-pmd-aligned page, and point
1216 * memblock_limit at it. This relies on rounding the
1217 * limit down to be pmd-aligned, which happens at the
1218 * end of this function.
1220 * With this algorithm, the start or end of almost any
1221 * bank can be non-pmd-aligned. The only exception is
1222 * that the start of the bank 0 must be section-
1223 * aligned, since otherwise memory would need to be
1224 * allocated when mapping the start of bank 0, which
1225 * occurs before any free memory is mapped.
1227 if (!memblock_limit
) {
1228 if (!IS_ALIGNED(block_start
, PMD_SIZE
))
1229 memblock_limit
= block_start
;
1230 else if (!IS_ALIGNED(block_end
, PMD_SIZE
))
1231 memblock_limit
= lowmem_limit
;
1237 arm_lowmem_limit
= lowmem_limit
;
1239 high_memory
= __va(arm_lowmem_limit
- 1) + 1;
1241 if (!memblock_limit
)
1242 memblock_limit
= arm_lowmem_limit
;
1245 * Round the memblock limit down to a pmd size. This
1246 * helps to ensure that we will allocate memory from the
1247 * last full pmd, which should be mapped.
1249 memblock_limit
= round_down(memblock_limit
, PMD_SIZE
);
1251 if (!IS_ENABLED(CONFIG_HIGHMEM
) || cache_is_vipt_aliasing()) {
1252 if (memblock_end_of_DRAM() > arm_lowmem_limit
) {
1253 phys_addr_t end
= memblock_end_of_DRAM();
1255 pr_notice("Ignoring RAM at %pa-%pa\n",
1256 &memblock_limit
, &end
);
1257 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1259 memblock_remove(memblock_limit
, end
- memblock_limit
);
1263 memblock_set_current_limit(memblock_limit
);
1266 static __init
void prepare_page_table(void)
1272 * Clear out all the mappings below the kernel image.
1276 * KASan's shadow memory inserts itself between the TASK_SIZE
1277 * and MODULES_VADDR. Do not clear the KASan shadow memory mappings.
1279 for (addr
= 0; addr
< KASAN_SHADOW_START
; addr
+= PMD_SIZE
)
1280 pmd_clear(pmd_off_k(addr
));
1282 * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes
1283 * equal to MODULES_VADDR and then we exit the pmd clearing. If we
1284 * are using a thumb-compiled kernel, there there will be 8MB more
1285 * to clear as KASan always offset to 16 MB below MODULES_VADDR.
1287 for (addr
= KASAN_SHADOW_END
; addr
< MODULES_VADDR
; addr
+= PMD_SIZE
)
1288 pmd_clear(pmd_off_k(addr
));
1290 for (addr
= 0; addr
< MODULES_VADDR
; addr
+= PMD_SIZE
)
1291 pmd_clear(pmd_off_k(addr
));
1294 #ifdef CONFIG_XIP_KERNEL
1295 /* The XIP kernel is mapped in the module area -- skip over it */
1296 addr
= ((unsigned long)_exiprom
+ PMD_SIZE
- 1) & PMD_MASK
;
1298 for ( ; addr
< PAGE_OFFSET
; addr
+= PMD_SIZE
)
1299 pmd_clear(pmd_off_k(addr
));
1302 * Find the end of the first block of lowmem.
1304 end
= memblock
.memory
.regions
[0].base
+ memblock
.memory
.regions
[0].size
;
1305 if (end
>= arm_lowmem_limit
)
1306 end
= arm_lowmem_limit
;
1309 * Clear out all the kernel space mappings, except for the first
1310 * memory bank, up to the vmalloc region.
1312 for (addr
= __phys_to_virt(end
);
1313 addr
< VMALLOC_START
; addr
+= PMD_SIZE
)
1314 pmd_clear(pmd_off_k(addr
));
1317 #ifdef CONFIG_ARM_LPAE
1318 /* the first page is reserved for pgd */
1319 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1320 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1322 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1326 * Reserve the special regions of memory
1328 void __init
arm_mm_memblock_reserve(void)
1331 * Reserve the page tables. These are already in use,
1332 * and can only be in node 0.
1334 memblock_reserve(__pa(swapper_pg_dir
), SWAPPER_PG_DIR_SIZE
);
1336 #ifdef CONFIG_SA1111
1338 * Because of the SA1111 DMA bug, we want to preserve our
1339 * precious DMA-able memory...
1341 memblock_reserve(PHYS_OFFSET
, __pa(swapper_pg_dir
) - PHYS_OFFSET
);
1346 * Set up the device mappings. Since we clear out the page tables for all
1347 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1348 * device mappings. This means earlycon can be used to debug this function
1349 * Any other function or debugging method which may touch any device _will_
1352 static void __init
devicemaps_init(const struct machine_desc
*mdesc
)
1354 struct map_desc map
;
1359 * Allocate the vector page early.
1361 vectors
= early_alloc(PAGE_SIZE
* 2);
1363 early_trap_init(vectors
);
1366 * Clear page table except top pmd used by early fixmaps
1368 for (addr
= VMALLOC_START
; addr
< (FIXADDR_TOP
& PMD_MASK
); addr
+= PMD_SIZE
)
1369 pmd_clear(pmd_off_k(addr
));
1371 if (__atags_pointer
) {
1372 /* create a read-only mapping of the device tree */
1373 map
.pfn
= __phys_to_pfn(__atags_pointer
& SECTION_MASK
);
1374 map
.virtual = FDT_FIXED_BASE
;
1375 map
.length
= FDT_FIXED_SIZE
;
1376 map
.type
= MT_MEMORY_RO
;
1377 create_mapping(&map
);
1381 * Map the kernel if it is XIP.
1382 * It is always first in the modulearea.
1384 #ifdef CONFIG_XIP_KERNEL
1385 map
.pfn
= __phys_to_pfn(CONFIG_XIP_PHYS_ADDR
& SECTION_MASK
);
1386 map
.virtual = MODULES_VADDR
;
1387 map
.length
= ((unsigned long)_exiprom
- map
.virtual + ~SECTION_MASK
) & SECTION_MASK
;
1389 create_mapping(&map
);
1393 * Map the cache flushing regions.
1396 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
);
1397 map
.virtual = FLUSH_BASE
;
1399 map
.type
= MT_CACHECLEAN
;
1400 create_mapping(&map
);
1402 #ifdef FLUSH_BASE_MINICACHE
1403 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
+ SZ_1M
);
1404 map
.virtual = FLUSH_BASE_MINICACHE
;
1406 map
.type
= MT_MINICLEAN
;
1407 create_mapping(&map
);
1411 * Create a mapping for the machine vectors at the high-vectors
1412 * location (0xffff0000). If we aren't using high-vectors, also
1413 * create a mapping at the low-vectors virtual address.
1415 map
.pfn
= __phys_to_pfn(virt_to_phys(vectors
));
1416 map
.virtual = 0xffff0000;
1417 map
.length
= PAGE_SIZE
;
1418 #ifdef CONFIG_KUSER_HELPERS
1419 map
.type
= MT_HIGH_VECTORS
;
1421 map
.type
= MT_LOW_VECTORS
;
1423 create_mapping(&map
);
1425 if (!vectors_high()) {
1427 map
.length
= PAGE_SIZE
* 2;
1428 map
.type
= MT_LOW_VECTORS
;
1429 create_mapping(&map
);
1432 /* Now create a kernel read-only mapping */
1434 map
.virtual = 0xffff0000 + PAGE_SIZE
;
1435 map
.length
= PAGE_SIZE
;
1436 map
.type
= MT_LOW_VECTORS
;
1437 create_mapping(&map
);
1440 * Ask the machine support to map in the statically mapped devices.
1448 /* Reserve fixed i/o space in VMALLOC region */
1452 * Finally flush the caches and tlb to ensure that we're in a
1453 * consistent state wrt the writebuffer. This also ensures that
1454 * any write-allocated cache lines in the vector page are written
1455 * back. After this point, we can start to touch devices again.
1457 local_flush_tlb_all();
1460 /* Enable asynchronous aborts */
1464 static void __init
kmap_init(void)
1466 #ifdef CONFIG_HIGHMEM
1467 pkmap_page_table
= early_pte_alloc(pmd_off_k(PKMAP_BASE
),
1468 PKMAP_BASE
, _PAGE_KERNEL_TABLE
);
1471 early_pte_alloc(pmd_off_k(FIXADDR_START
), FIXADDR_START
,
1472 _PAGE_KERNEL_TABLE
);
1475 static void __init
map_lowmem(void)
1477 phys_addr_t start
, end
;
1480 /* Map all the lowmem memory banks. */
1481 for_each_mem_range(i
, &start
, &end
) {
1482 struct map_desc map
;
1484 pr_debug("map lowmem start: 0x%08llx, end: 0x%08llx\n",
1485 (long long)start
, (long long)end
);
1486 if (end
> arm_lowmem_limit
)
1487 end
= arm_lowmem_limit
;
1492 * If our kernel image is in the VMALLOC area we need to remove
1493 * the kernel physical memory from lowmem since the kernel will
1494 * be mapped separately.
1496 * The kernel will typically be at the very start of lowmem,
1497 * but any placement relative to memory ranges is possible.
1499 * If the memblock contains the kernel, we have to chisel out
1500 * the kernel memory from it and map each part separately. We
1501 * get 6 different theoretical cases:
1503 * +--------+ +--------+
1504 * +-- start --+ +--------+ | Kernel | | Kernel |
1505 * | | | Kernel | | case 2 | | case 5 |
1506 * | | | case 1 | +--------+ | | +--------+
1507 * | Memory | +--------+ | | | Kernel |
1508 * | range | +--------+ | | | case 6 |
1509 * | | | Kernel | +--------+ | | +--------+
1510 * | | | case 3 | | Kernel | | |
1511 * +-- end ----+ +--------+ | case 4 | | |
1512 * +--------+ +--------+
1515 /* Case 5: kernel covers range, don't map anything, should be rare */
1516 if ((start
> kernel_sec_start
) && (end
< kernel_sec_end
))
1519 /* Cases where the kernel is starting inside the range */
1520 if ((kernel_sec_start
>= start
) && (kernel_sec_start
<= end
)) {
1521 /* Case 6: kernel is embedded in the range, we need two mappings */
1522 if ((start
< kernel_sec_start
) && (end
> kernel_sec_end
)) {
1523 /* Map memory below the kernel */
1524 map
.pfn
= __phys_to_pfn(start
);
1525 map
.virtual = __phys_to_virt(start
);
1526 map
.length
= kernel_sec_start
- start
;
1527 map
.type
= MT_MEMORY_RW
;
1528 create_mapping(&map
);
1529 /* Map memory above the kernel */
1530 map
.pfn
= __phys_to_pfn(kernel_sec_end
);
1531 map
.virtual = __phys_to_virt(kernel_sec_end
);
1532 map
.length
= end
- kernel_sec_end
;
1533 map
.type
= MT_MEMORY_RW
;
1534 create_mapping(&map
);
1537 /* Case 1: kernel and range start at the same address, should be common */
1538 if (kernel_sec_start
== start
)
1539 start
= kernel_sec_end
;
1540 /* Case 3: kernel and range end at the same address, should be rare */
1541 if (kernel_sec_end
== end
)
1542 end
= kernel_sec_start
;
1543 } else if ((kernel_sec_start
< start
) && (kernel_sec_end
> start
) && (kernel_sec_end
< end
)) {
1544 /* Case 2: kernel ends inside range, starts below it */
1545 start
= kernel_sec_end
;
1546 } else if ((kernel_sec_start
> start
) && (kernel_sec_start
< end
) && (kernel_sec_end
> end
)) {
1547 /* Case 4: kernel starts inside range, ends above it */
1548 end
= kernel_sec_start
;
1550 map
.pfn
= __phys_to_pfn(start
);
1551 map
.virtual = __phys_to_virt(start
);
1552 map
.length
= end
- start
;
1553 map
.type
= MT_MEMORY_RW
;
1554 create_mapping(&map
);
1558 static void __init
map_kernel(void)
1561 * We use the well known kernel section start and end and split the area in the
1565 * +----------------+ kernel_x_start
1568 * +----------------+ kernel_x_end / kernel_nx_start
1569 * | Non-executable |
1571 * +----------------+ kernel_nx_end
1575 * Notice that we are dealing with section sized mappings here so all of this
1576 * will be bumped to the closest section boundary. This means that some of the
1577 * non-executable part of the kernel memory is actually mapped as executable.
1578 * This will only persist until we turn on proper memory management later on
1579 * and we remap the whole kernel with page granularity.
1581 phys_addr_t kernel_x_start
= kernel_sec_start
;
1582 phys_addr_t kernel_x_end
= round_up(__pa(__init_end
), SECTION_SIZE
);
1583 phys_addr_t kernel_nx_start
= kernel_x_end
;
1584 phys_addr_t kernel_nx_end
= kernel_sec_end
;
1585 struct map_desc map
;
1587 map
.pfn
= __phys_to_pfn(kernel_x_start
);
1588 map
.virtual = __phys_to_virt(kernel_x_start
);
1589 map
.length
= kernel_x_end
- kernel_x_start
;
1590 map
.type
= MT_MEMORY_RWX
;
1591 create_mapping(&map
);
1593 /* If the nx part is small it may end up covered by the tail of the RWX section */
1594 if (kernel_x_end
== kernel_nx_end
)
1597 map
.pfn
= __phys_to_pfn(kernel_nx_start
);
1598 map
.virtual = __phys_to_virt(kernel_nx_start
);
1599 map
.length
= kernel_nx_end
- kernel_nx_start
;
1600 map
.type
= MT_MEMORY_RW
;
1601 create_mapping(&map
);
1604 #ifdef CONFIG_ARM_PV_FIXUP
1605 typedef void pgtables_remap(long long offset
, unsigned long pgd
);
1606 pgtables_remap lpae_pgtables_remap_asm
;
1609 * early_paging_init() recreates boot time page table setup, allowing machines
1610 * to switch over to a high (>4G) address space on LPAE systems
1612 static void __init
early_paging_init(const struct machine_desc
*mdesc
)
1614 pgtables_remap
*lpae_pgtables_remap
;
1615 unsigned long pa_pgd
;
1616 unsigned int cr
, ttbcr
;
1619 if (!mdesc
->pv_fixup
)
1622 offset
= mdesc
->pv_fixup();
1627 * Offset the kernel section physical offsets so that the kernel
1628 * mapping will work out later on.
1630 kernel_sec_start
+= offset
;
1631 kernel_sec_end
+= offset
;
1634 * Get the address of the remap function in the 1:1 identity
1635 * mapping setup by the early page table assembly code. We
1636 * must get this prior to the pv update. The following barrier
1637 * ensures that this is complete before we fixup any P:V offsets.
1639 lpae_pgtables_remap
= (pgtables_remap
*)(unsigned long)__pa(lpae_pgtables_remap_asm
);
1640 pa_pgd
= __pa(swapper_pg_dir
);
1643 pr_info("Switching physical address space to 0x%08llx\n",
1644 (u64
)PHYS_OFFSET
+ offset
);
1646 /* Re-set the phys pfn offset, and the pv offset */
1647 __pv_offset
+= offset
;
1648 __pv_phys_pfn_offset
+= PFN_DOWN(offset
);
1650 /* Run the patch stub to update the constants */
1651 fixup_pv_table(&__pv_table_begin
,
1652 (&__pv_table_end
- &__pv_table_begin
) << 2);
1655 * We changing not only the virtual to physical mapping, but also
1656 * the physical addresses used to access memory. We need to flush
1657 * all levels of cache in the system with caching disabled to
1658 * ensure that all data is written back, and nothing is prefetched
1659 * into the caches. We also need to prevent the TLB walkers
1660 * allocating into the caches too. Note that this is ARMv7 LPAE
1664 set_cr(cr
& ~(CR_I
| CR_C
));
1665 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr
));
1666 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1667 : : "r" (ttbcr
& ~(3 << 8 | 3 << 10)));
1671 * Fixup the page tables - this must be in the idmap region as
1672 * we need to disable the MMU to do this safely, and hence it
1673 * needs to be assembly. It's fairly simple, as we're using the
1674 * temporary tables setup by the initial assembly code.
1676 lpae_pgtables_remap(offset
, pa_pgd
);
1678 /* Re-enable the caches and cacheable TLB walks */
1679 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr
));
1685 static void __init
early_paging_init(const struct machine_desc
*mdesc
)
1689 if (!mdesc
->pv_fixup
)
1692 offset
= mdesc
->pv_fixup();
1696 pr_crit("Physical address space modification is only to support Keystone2.\n");
1697 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1698 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1699 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_STILL_OK
);
1704 static void __init
early_fixmap_shutdown(void)
1707 unsigned long va
= fix_to_virt(__end_of_permanent_fixed_addresses
- 1);
1709 pte_offset_fixmap
= pte_offset_late_fixmap
;
1710 pmd_clear(fixmap_pmd(va
));
1711 local_flush_tlb_kernel_page(va
);
1713 for (i
= 0; i
< __end_of_permanent_fixed_addresses
; i
++) {
1715 struct map_desc map
;
1717 map
.virtual = fix_to_virt(i
);
1718 pte
= pte_offset_early_fixmap(pmd_off_k(map
.virtual), map
.virtual);
1720 /* Only i/o device mappings are supported ATM */
1721 if (pte_none(*pte
) ||
1722 (pte_val(*pte
) & L_PTE_MT_MASK
) != L_PTE_MT_DEV_SHARED
)
1725 map
.pfn
= pte_pfn(*pte
);
1726 map
.type
= MT_DEVICE
;
1727 map
.length
= PAGE_SIZE
;
1729 create_mapping(&map
);
1734 * paging_init() sets up the page tables, initialises the zone memory
1735 * maps, and sets up the zero page, bad page and bad page tables.
1737 void __init
paging_init(const struct machine_desc
*mdesc
)
1741 pr_debug("physical kernel sections: 0x%08llx-0x%08llx\n",
1742 kernel_sec_start
, kernel_sec_end
);
1744 prepare_page_table();
1746 memblock_set_current_limit(arm_lowmem_limit
);
1747 pr_debug("lowmem limit is %08llx\n", (long long)arm_lowmem_limit
);
1749 * After this point early_alloc(), i.e. the memblock allocator, can
1753 dma_contiguous_remap();
1754 early_fixmap_shutdown();
1755 devicemaps_init(mdesc
);
1759 top_pmd
= pmd_off_k(0xffff0000);
1761 /* allocate the zero page. */
1762 zero_page
= early_alloc(PAGE_SIZE
);
1766 empty_zero_page
= virt_to_page(zero_page
);
1767 __flush_dcache_page(NULL
, empty_zero_page
);
1770 void __init
early_mm_init(const struct machine_desc
*mdesc
)
1772 build_mem_type_table();
1773 early_paging_init(mdesc
);
1776 void set_pte_at(struct mm_struct
*mm
, unsigned long addr
,
1777 pte_t
*ptep
, pte_t pteval
)
1779 unsigned long ext
= 0;
1781 if (addr
< TASK_SIZE
&& pte_valid_user(pteval
)) {
1782 if (!pte_special(pteval
))
1783 __sync_icache_dcache(pteval
);
1787 set_pte_ext(ptep
, pteval
, ext
);