2 * linux/arch/arm/mm/nommu.c
4 * ARM uCLinux supporting functions.
6 #include <linux/module.h>
8 #include <linux/pagemap.h>
10 #include <linux/memblock.h>
11 #include <linux/kernel.h>
13 #include <asm/cacheflush.h>
15 #include <asm/sections.h>
17 #include <asm/setup.h>
18 #include <asm/traps.h>
19 #include <asm/mach/arch.h>
20 #include <asm/cputype.h>
22 #include <asm/procinfo.h>
26 unsigned long vectors_base
;
29 struct mpu_rgn_info mpu_rgn_info
;
32 static void rgnr_write(u32 v
)
34 asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v
));
37 /* Data-side / unified region attributes */
39 /* Region access control register */
40 static void dracr_write(u32 v
)
42 asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v
));
45 /* Region size register */
46 static void drsr_write(u32 v
)
48 asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v
));
51 /* Region base address register */
52 static void drbar_write(u32 v
)
54 asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v
));
57 static u32
drbar_read(void)
60 asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v
));
63 /* Optional instruction-side region attributes */
65 /* I-side Region access control register */
66 static void iracr_write(u32 v
)
68 asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v
));
71 /* I-side Region size register */
72 static void irsr_write(u32 v
)
74 asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v
));
77 /* I-side Region base address register */
78 static void irbar_write(u32 v
)
80 asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v
));
83 static unsigned long irbar_read(void)
86 asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v
));
90 /* MPU initialisation functions */
91 void __init
adjust_lowmem_bounds_mpu(void)
93 phys_addr_t phys_offset
= PHYS_OFFSET
;
94 phys_addr_t aligned_region_size
, specified_mem_size
, rounded_mem_size
;
95 struct memblock_region
*reg
;
97 phys_addr_t mem_start
;
100 for_each_memblock(memory
, reg
) {
103 * Initially only use memory continuous from
105 if (reg
->base
!= phys_offset
)
106 panic("First memory bank must be contiguous from PHYS_OFFSET");
108 mem_start
= reg
->base
;
109 mem_end
= reg
->base
+ reg
->size
;
110 specified_mem_size
= reg
->size
;
114 * memblock auto merges contiguous blocks, remove
115 * all blocks afterwards in one go (we can't remove
116 * blocks separately while iterating)
118 pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
119 &mem_end
, ®
->base
);
120 memblock_remove(reg
->base
, 0 - reg
->base
);
126 * MPU has curious alignment requirements: Size must be power of 2, and
127 * region start must be aligned to the region size
129 if (phys_offset
!= 0)
130 pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
133 * Maximum aligned region might overflow phys_addr_t if phys_offset is
134 * 0. Hence we keep everything below 4G until we take the smaller of
135 * the aligned_region_size and rounded_mem_size, one of which is
136 * guaranteed to be smaller than the maximum physical address.
138 aligned_region_size
= (phys_offset
- 1) ^ (phys_offset
);
139 /* Find the max power-of-two sized region that fits inside our bank */
140 rounded_mem_size
= (1 << __fls(specified_mem_size
)) - 1;
142 /* The actual region size is the smaller of the two */
143 aligned_region_size
= aligned_region_size
< rounded_mem_size
144 ? aligned_region_size
+ 1
145 : rounded_mem_size
+ 1;
147 if (aligned_region_size
!= specified_mem_size
) {
148 pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
149 &specified_mem_size
, &aligned_region_size
);
150 memblock_remove(mem_start
+ aligned_region_size
,
151 specified_mem_size
- aligned_region_size
);
153 mem_end
= mem_start
+ aligned_region_size
;
156 pr_debug("MPU Region from %pa size %pa (end %pa))\n",
157 &phys_offset
, &aligned_region_size
, &mem_end
);
161 static int mpu_present(void)
163 return ((read_cpuid_ext(CPUID_EXT_MMFR0
) & MMFR0_PMSA
) == MMFR0_PMSAv7
);
166 static int mpu_max_regions(void)
169 * We don't support a different number of I/D side regions so if we
170 * have separate instruction and data memory maps then return
171 * whichever side has a smaller number of supported regions.
173 u32 dregions
, iregions
, mpuir
;
174 mpuir
= read_cpuid(CPUID_MPUIR
);
176 dregions
= iregions
= (mpuir
& MPUIR_DREGION_SZMASK
) >> MPUIR_DREGION
;
178 /* Check for separate d-side and i-side memory maps */
179 if (mpuir
& MPUIR_nU
)
180 iregions
= (mpuir
& MPUIR_IREGION_SZMASK
) >> MPUIR_IREGION
;
182 /* Use the smallest of the two maxima */
183 return min(dregions
, iregions
);
186 static int mpu_iside_independent(void)
188 /* MPUIR.nU specifies whether there is *not* a unified memory map */
189 return read_cpuid(CPUID_MPUIR
) & MPUIR_nU
;
192 static int mpu_min_region_order(void)
194 u32 drbar_result
, irbar_result
;
195 /* We've kept a region free for this probing */
196 rgnr_write(MPU_PROBE_REGION
);
199 * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
202 drbar_write(0xFFFFFFFC);
203 drbar_result
= irbar_result
= drbar_read();
205 /* If the MPU is non-unified, we use the larger of the two minima*/
206 if (mpu_iside_independent()) {
207 irbar_write(0xFFFFFFFC);
208 irbar_result
= irbar_read();
211 isb(); /* Ensure that MPU region operations have completed */
212 /* Return whichever result is larger */
213 return __ffs(max(drbar_result
, irbar_result
));
216 static int mpu_setup_region(unsigned int number
, phys_addr_t start
,
217 unsigned int size_order
, unsigned int properties
)
221 /* We kept a region free for probing resolution of MPU regions*/
222 if (number
> mpu_max_regions() || number
== MPU_PROBE_REGION
)
228 if (size_order
< mpu_min_region_order())
231 /* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */
232 size_data
= ((size_order
- 1) << MPU_RSR_SZ
) | 1 << MPU_RSR_EN
;
234 dsb(); /* Ensure all previous data accesses occur with old mappings */
238 dracr_write(properties
);
239 isb(); /* Propagate properties before enabling region */
240 drsr_write(size_data
);
242 /* Check for independent I-side registers */
243 if (mpu_iside_independent()) {
245 iracr_write(properties
);
247 irsr_write(size_data
);
251 /* Store region info (we treat i/d side the same, so only store d) */
252 mpu_rgn_info
.rgns
[number
].dracr
= properties
;
253 mpu_rgn_info
.rgns
[number
].drbar
= start
;
254 mpu_rgn_info
.rgns
[number
].drsr
= size_data
;
259 * Set up default MPU regions, doing nothing if there is no MPU
261 void __init
mpu_setup(void)
267 region_err
= mpu_setup_region(MPU_RAM_REGION
, PHYS_OFFSET
,
268 ilog2(memblock
.memory
.regions
[0].size
),
269 MPU_AP_PL1RW_PL0RW
| MPU_RGN_NORMAL
);
271 panic("MPU region initialization failure! %d", region_err
);
273 pr_info("Using ARMv7 PMSA Compliant MPU. "
274 "Region independence: %s, Max regions: %d\n",
275 mpu_iside_independent() ? "Yes" : "No",
280 static void adjust_lowmem_bounds_mpu(void) {}
281 static void __init
mpu_setup(void) {}
282 #endif /* CONFIG_ARM_MPU */
284 #ifdef CONFIG_CPU_CP15
285 #ifdef CONFIG_CPU_HIGH_VECTOR
286 static unsigned long __init
setup_vectors_base(void)
288 unsigned long reg
= get_cr();
293 #else /* CONFIG_CPU_HIGH_VECTOR */
294 /* Write exception base address to VBAR */
295 static inline void set_vbar(unsigned long val
)
297 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val
) : "cc");
301 * Security extensions, bits[7:4], permitted values,
302 * 0b0000 - not implemented, 0b0001/0b0010 - implemented
304 static inline bool security_extensions_enabled(void)
306 return !!cpuid_feature_extract(CPUID_EXT_PFR1
, 4);
309 static unsigned long __init
setup_vectors_base(void)
311 unsigned long base
= 0, reg
= get_cr();
314 if (security_extensions_enabled()) {
315 if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM
))
316 base
= CONFIG_DRAM_BASE
;
318 } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM
)) {
319 if (CONFIG_DRAM_BASE
!= 0)
320 pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n");
325 #endif /* CONFIG_CPU_HIGH_VECTOR */
326 #endif /* CONFIG_CPU_CP15 */
328 void __init
arm_mm_memblock_reserve(void)
330 #ifndef CONFIG_CPU_V7M
331 vectors_base
= IS_ENABLED(CONFIG_CPU_CP15
) ? setup_vectors_base() : 0;
333 * Register the exception vector page.
334 * some architectures which the DRAM is the exception vector to trap,
335 * alloc_page breaks with error, although it is not NULL, but "0."
337 memblock_reserve(vectors_base
, 2 * PAGE_SIZE
);
338 #else /* ifndef CONFIG_CPU_V7M */
340 * There is no dedicated vector page on V7-M. So nothing needs to be
346 void __init
adjust_lowmem_bounds(void)
349 adjust_lowmem_bounds_mpu();
350 end
= memblock_end_of_DRAM();
351 high_memory
= __va(end
- 1) + 1;
352 memblock_set_current_limit(end
);
356 * paging_init() sets up the page tables, initialises the zone memory
357 * maps, and sets up the zero page, bad page and bad page tables.
359 void __init
paging_init(const struct machine_desc
*mdesc
)
361 early_trap_init((void *)vectors_base
);
367 * We don't need to do anything here for nommu machines.
369 void setup_mm_for_reboot(void)
373 void flush_dcache_page(struct page
*page
)
375 __cpuc_flush_dcache_area(page_address(page
), PAGE_SIZE
);
377 EXPORT_SYMBOL(flush_dcache_page
);
379 void flush_kernel_dcache_page(struct page
*page
)
381 __cpuc_flush_dcache_area(page_address(page
), PAGE_SIZE
);
383 EXPORT_SYMBOL(flush_kernel_dcache_page
);
385 void copy_to_user_page(struct vm_area_struct
*vma
, struct page
*page
,
386 unsigned long uaddr
, void *dst
, const void *src
,
389 memcpy(dst
, src
, len
);
390 if (vma
->vm_flags
& VM_EXEC
)
391 __cpuc_coherent_user_range(uaddr
, uaddr
+ len
);
394 void __iomem
*__arm_ioremap_pfn(unsigned long pfn
, unsigned long offset
,
395 size_t size
, unsigned int mtype
)
397 if (pfn
>= (0x100000000ULL
>> PAGE_SHIFT
))
399 return (void __iomem
*) (offset
+ (pfn
<< PAGE_SHIFT
));
401 EXPORT_SYMBOL(__arm_ioremap_pfn
);
403 void __iomem
*__arm_ioremap_caller(phys_addr_t phys_addr
, size_t size
,
404 unsigned int mtype
, void *caller
)
406 return (void __iomem
*)phys_addr
;
409 void __iomem
* (*arch_ioremap_caller
)(phys_addr_t
, size_t, unsigned int, void *);
411 void __iomem
*ioremap(resource_size_t res_cookie
, size_t size
)
413 return __arm_ioremap_caller(res_cookie
, size
, MT_DEVICE
,
414 __builtin_return_address(0));
416 EXPORT_SYMBOL(ioremap
);
418 void __iomem
*ioremap_cache(resource_size_t res_cookie
, size_t size
)
419 __alias(ioremap_cached
);
421 void __iomem
*ioremap_cached(resource_size_t res_cookie
, size_t size
)
423 return __arm_ioremap_caller(res_cookie
, size
, MT_DEVICE_CACHED
,
424 __builtin_return_address(0));
426 EXPORT_SYMBOL(ioremap_cache
);
427 EXPORT_SYMBOL(ioremap_cached
);
429 void __iomem
*ioremap_wc(resource_size_t res_cookie
, size_t size
)
431 return __arm_ioremap_caller(res_cookie
, size
, MT_DEVICE_WC
,
432 __builtin_return_address(0));
434 EXPORT_SYMBOL(ioremap_wc
);
436 void *arch_memremap_wb(phys_addr_t phys_addr
, size_t size
)
438 return (void *)phys_addr
;
441 void __iounmap(volatile void __iomem
*addr
)
444 EXPORT_SYMBOL(__iounmap
);
446 void (*arch_iounmap
)(volatile void __iomem
*);
448 void iounmap(volatile void __iomem
*addr
)
451 EXPORT_SYMBOL(iounmap
);