2 * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 * These are the low level assembler for performing cache and TLB
15 * functions on the ARM1022E.
17 #include <linux/linkage.h>
18 #include <linux/init.h>
19 #include <asm/assembler.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/hwcap.h>
22 #include <asm/pgtable-hwdef.h>
23 #include <asm/pgtable.h>
24 #include <asm/ptrace.h>
26 #include "proc-macros.S"
29 * This is the maximum size of an area which will be invalidated
30 * using the single invalidate entry instructions. Anything larger
31 * than this, and we go for the whole cache.
33 * This value should be chosen such that we choose the cheapest
36 #define MAX_AREA_SIZE 32768
39 * The size of one data cache line.
41 #define CACHE_DLINESIZE 32
44 * The number of data cache segments.
46 #define CACHE_DSEGMENTS 16
49 * The number of lines in a cache segment.
51 #define CACHE_DENTRIES 64
54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual
56 * cache line maintainence instructions.
58 #define CACHE_DLIMIT 32768
62 * cpu_arm1022_proc_init()
64 ENTRY(cpu_arm1022_proc_init)
68 * cpu_arm1022_proc_fin()
70 ENTRY(cpu_arm1022_proc_fin)
71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
72 bic r0, r0, #0x1000 @ ...i............
73 bic r0, r0, #0x000e @ ............wca.
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 * cpu_arm1022_reset(loc)
80 * Perform a soft reset of the system. Put the CPU into the
81 * same state as it would be if it had been reset, and branch
82 * to what would be the reset vector.
84 * loc: location to jump to for soft reset
87 ENTRY(cpu_arm1022_reset)
89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
90 mcr p15, 0, ip, c7, c10, 4 @ drain WB
92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
95 bic ip, ip, #0x000f @ ............wcam
96 bic ip, ip, #0x1100 @ ...i...s........
97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
101 * cpu_arm1022_do_idle()
104 ENTRY(cpu_arm1022_do_idle)
105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
108 /* ================================= CACHE ================================ */
112 * flush_user_cache_all()
114 * Invalidate all cache entries in a particular address
117 ENTRY(arm1022_flush_user_cache_all)
120 * flush_kern_cache_all()
122 * Clean and invalidate the entire cache.
124 ENTRY(arm1022_flush_kern_cache_all)
128 #ifndef CONFIG_CPU_DCACHE_DISABLE
129 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
130 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
131 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
132 subs r3, r3, #1 << 26
133 bcs 2b @ entries 63 to 0
135 bcs 1b @ segments 15 to 0
138 #ifndef CONFIG_CPU_ICACHE_DISABLE
139 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
145 * flush_user_cache_range(start, end, flags)
147 * Invalidate a range of cache entries in the specified
150 * - start - start address (inclusive)
151 * - end - end address (exclusive)
152 * - flags - vm_flags for this space
154 ENTRY(arm1022_flush_user_cache_range)
156 sub r3, r1, r0 @ calculate total size
157 cmp r3, #CACHE_DLIMIT
158 bhs __flush_whole_cache
160 #ifndef CONFIG_CPU_DCACHE_DISABLE
161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
162 add r0, r0, #CACHE_DLINESIZE
167 #ifndef CONFIG_CPU_ICACHE_DISABLE
168 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
170 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
174 * coherent_kern_range(start, end)
176 * Ensure coherency between the Icache and the Dcache in the
177 * region described by start. If you have non-snooping
178 * Harvard caches, you need to implement this function.
180 * - start - virtual start address
181 * - end - virtual end address
183 ENTRY(arm1022_coherent_kern_range)
187 * coherent_user_range(start, end)
189 * Ensure coherency between the Icache and the Dcache in the
190 * region described by start. If you have non-snooping
191 * Harvard caches, you need to implement this function.
193 * - start - virtual start address
194 * - end - virtual end address
196 ENTRY(arm1022_coherent_user_range)
198 bic r0, r0, #CACHE_DLINESIZE - 1
200 #ifndef CONFIG_CPU_DCACHE_DISABLE
201 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
203 #ifndef CONFIG_CPU_ICACHE_DISABLE
204 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
206 add r0, r0, #CACHE_DLINESIZE
209 mcr p15, 0, ip, c7, c10, 4 @ drain WB
213 * flush_kern_dcache_area(void *addr, size_t size)
215 * Ensure no D cache aliasing occurs, either with itself or
218 * - addr - kernel address
219 * - size - region size
221 ENTRY(arm1022_flush_kern_dcache_area)
223 #ifndef CONFIG_CPU_DCACHE_DISABLE
225 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
226 add r0, r0, #CACHE_DLINESIZE
230 mcr p15, 0, ip, c7, c10, 4 @ drain WB
234 * dma_inv_range(start, end)
236 * Invalidate (discard) the specified virtual address range.
237 * May not write back any entries. If 'start' or 'end'
238 * are not cache line aligned, those lines must be written
241 * - start - virtual start address
242 * - end - virtual end address
246 arm1022_dma_inv_range:
248 #ifndef CONFIG_CPU_DCACHE_DISABLE
249 tst r0, #CACHE_DLINESIZE - 1
250 bic r0, r0, #CACHE_DLINESIZE - 1
251 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
252 tst r1, #CACHE_DLINESIZE - 1
253 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
254 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
255 add r0, r0, #CACHE_DLINESIZE
259 mcr p15, 0, ip, c7, c10, 4 @ drain WB
263 * dma_clean_range(start, end)
265 * Clean the specified virtual address range.
267 * - start - virtual start address
268 * - end - virtual end address
272 arm1022_dma_clean_range:
274 #ifndef CONFIG_CPU_DCACHE_DISABLE
275 bic r0, r0, #CACHE_DLINESIZE - 1
276 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
277 add r0, r0, #CACHE_DLINESIZE
281 mcr p15, 0, ip, c7, c10, 4 @ drain WB
285 * dma_flush_range(start, end)
287 * Clean and invalidate the specified virtual address range.
289 * - start - virtual start address
290 * - end - virtual end address
292 ENTRY(arm1022_dma_flush_range)
294 #ifndef CONFIG_CPU_DCACHE_DISABLE
295 bic r0, r0, #CACHE_DLINESIZE - 1
296 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
297 add r0, r0, #CACHE_DLINESIZE
301 mcr p15, 0, ip, c7, c10, 4 @ drain WB
305 * dma_map_area(start, size, dir)
306 * - start - kernel virtual start address
307 * - size - size of region
308 * - dir - DMA direction
310 ENTRY(arm1022_dma_map_area)
312 cmp r2, #DMA_TO_DEVICE
313 beq arm1022_dma_clean_range
314 bcs arm1022_dma_inv_range
315 b arm1022_dma_flush_range
316 ENDPROC(arm1022_dma_map_area)
319 * dma_unmap_area(start, size, dir)
320 * - start - kernel virtual start address
321 * - size - size of region
322 * - dir - DMA direction
324 ENTRY(arm1022_dma_unmap_area)
326 ENDPROC(arm1022_dma_unmap_area)
328 ENTRY(arm1022_cache_fns)
329 .long arm1022_flush_kern_cache_all
330 .long arm1022_flush_user_cache_all
331 .long arm1022_flush_user_cache_range
332 .long arm1022_coherent_kern_range
333 .long arm1022_coherent_user_range
334 .long arm1022_flush_kern_dcache_area
335 .long arm1022_dma_map_area
336 .long arm1022_dma_unmap_area
337 .long arm1022_dma_flush_range
340 ENTRY(cpu_arm1022_dcache_clean_area)
341 #ifndef CONFIG_CPU_DCACHE_DISABLE
343 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
344 add r0, r0, #CACHE_DLINESIZE
345 subs r1, r1, #CACHE_DLINESIZE
350 /* =============================== PageTable ============================== */
353 * cpu_arm1022_switch_mm(pgd)
355 * Set the translation base pointer to be as described by pgd.
357 * pgd: new page tables
360 ENTRY(cpu_arm1022_switch_mm)
362 #ifndef CONFIG_CPU_DCACHE_DISABLE
363 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
364 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
365 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
366 subs r3, r3, #1 << 26
367 bcs 2b @ entries 63 to 0
369 bcs 1b @ segments 15 to 0
372 #ifndef CONFIG_CPU_ICACHE_DISABLE
373 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
375 mcr p15, 0, r1, c7, c10, 4 @ drain WB
376 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
377 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
382 * cpu_arm1022_set_pte_ext(ptep, pte, ext)
384 * Set a PTE and flush it out
387 ENTRY(cpu_arm1022_set_pte_ext)
391 #ifndef CONFIG_CPU_DCACHE_DISABLE
392 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
394 #endif /* CONFIG_MMU */
399 .type __arm1022_setup, #function
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
403 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
407 adr r5, arm1022_crval
409 mrc p15, 0, r0, c1, c0 @ get control register v4
412 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
413 orr r0, r0, #0x4000 @ .R..............
416 .size __arm1022_setup, . - __arm1022_setup
420 * .RVI ZFRS BLDP WCAM
421 * .011 1001 ..11 0101
424 .type arm1022_crval, #object
426 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
431 * Purpose : Function pointers used to access above functions - all calls
434 .type arm1022_processor_functions, #object
435 arm1022_processor_functions:
436 .word v4t_early_abort
438 .word cpu_arm1022_proc_init
439 .word cpu_arm1022_proc_fin
440 .word cpu_arm1022_reset
441 .word cpu_arm1022_do_idle
442 .word cpu_arm1022_dcache_clean_area
443 .word cpu_arm1022_switch_mm
444 .word cpu_arm1022_set_pte_ext
445 .size arm1022_processor_functions, . - arm1022_processor_functions
449 .type cpu_arch_name, #object
452 .size cpu_arch_name, . - cpu_arch_name
454 .type cpu_elf_name, #object
457 .size cpu_elf_name, . - cpu_elf_name
459 .type cpu_arm1022_name, #object
462 .size cpu_arm1022_name, . - cpu_arm1022_name
466 .section ".proc.info.init", #alloc, #execinstr
468 .type __arm1022_proc_info,#object
470 .long 0x4105a220 @ ARM 1022E (v5TE)
472 .long PMD_TYPE_SECT | \
474 PMD_SECT_AP_WRITE | \
476 .long PMD_TYPE_SECT | \
478 PMD_SECT_AP_WRITE | \
483 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
484 .long cpu_arm1022_name
485 .long arm1022_processor_functions
488 .long arm1022_cache_fns
489 .size __arm1022_proc_info, . - __arm1022_proc_info