arch/arm/mm/proc-arm1026.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
   3  *
   4  *  Copyright (C) 2000 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  *
  14  * These are the low level assembler for performing cache and TLB
  15  * functions on the ARM1026EJ-S.
  16  */
  17 #include <linux/linkage.h>
  18 #include <linux/init.h>
  19 #include <asm/assembler.h>
  20 #include <asm/asm-offsets.h>
  21 #include <asm/hwcap.h>
  22 #include <asm/pgtable-hwdef.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/ptrace.h>
  25
  26 #include "proc-macros.S"
  27
  28 /*
  29  * This is the maximum size of an area which will be invalidated
  30  * using the single invalidate entry instructions.  Anything larger
  31  * than this, and we go for the whole cache.
  32  *
  33  * This value should be chosen such that we choose the cheapest
  34  * alternative.
  35  */
  36 #define MAX_AREA_SIZE   32768
  37
  38 /*
  39  * The size of one data cache line.
  40  */
  41 #define CACHE_DLINESIZE 32
  42
  43 /*
  44  * The number of data cache segments.
  45  */
  46 #define CACHE_DSEGMENTS 16
  47
  48 /*
  49  * The number of lines in a cache segment.
  50  */
  51 #define CACHE_DENTRIES  64
  52
  53 /*
  54  * This is the size at which it becomes more efficient to
  55  * clean the whole cache, rather than using the individual
  56  * cache line maintainence instructions.
  57  */
  58 #define CACHE_DLIMIT    32768
  59
  60         .text
  61 /*
  62  * cpu_arm1026_proc_init()
  63  */
  64 ENTRY(cpu_arm1026_proc_init)
  65         mov     pc, lr
  66
  67 /*
  68  * cpu_arm1026_proc_fin()
  69  */
  70 ENTRY(cpu_arm1026_proc_fin)
  71         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  72         bic     r0, r0, #0x1000                 @ ...i............
  73         bic     r0, r0, #0x000e                 @ ............wca.
  74         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  75         mov     pc, lr
  76
  77 /*
  78  * cpu_arm1026_reset(loc)
  79  *
  80  * Perform a soft reset of the system.  Put the CPU into the
  81  * same state as it would be if it had been reset, and branch
  82  * to what would be the reset vector.
  83  *
  84  * loc: location to jump to for soft reset
  85  */
  86         .align  5
  87 ENTRY(cpu_arm1026_reset)
  88         mov     ip, #0
  89         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  90         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  91 #ifdef CONFIG_MMU
  92         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  93 #endif
  94         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  95         bic     ip, ip, #0x000f                 @ ............wcam
  96         bic     ip, ip, #0x1100                 @ ...i...s........
  97         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  98         mov     pc, r0
  99
 100 /*
 101  * cpu_arm1026_do_idle()
 102  */
 103         .align  5
 104 ENTRY(cpu_arm1026_do_idle)
 105         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 106         mov     pc, lr
 107
 108 /* ================================= CACHE ================================ */
 109
 110         .align  5
 111 /*
 112  *      flush_user_cache_all()
 113  *
 114  *      Invalidate all cache entries in a particular address
 115  *      space.
 116  */
 117 ENTRY(arm1026_flush_user_cache_all)
 118         /* FALLTHROUGH */
 119 /*
 120  *      flush_kern_cache_all()
 121  *
 122  *      Clean and invalidate the entire cache.
 123  */
 124 ENTRY(arm1026_flush_kern_cache_all)
 125         mov     r2, #VM_EXEC
 126         mov     ip, #0
 127 __flush_whole_cache:
 128 #ifndef CONFIG_CPU_DCACHE_DISABLE
 129 1:      mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
 130         bne     1b
 131 #endif
 132         tst     r2, #VM_EXEC
 133 #ifndef CONFIG_CPU_ICACHE_DISABLE
 134         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 135 #endif
 136         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 137         mov     pc, lr
 138
 139 /*
 140  *      flush_user_cache_range(start, end, flags)
 141  *
 142  *      Invalidate a range of cache entries in the specified
 143  *      address space.
 144  *
 145  *      - start - start address (inclusive)
 146  *      - end   - end address (exclusive)
 147  *      - flags - vm_flags for this space
 148  */
 149 ENTRY(arm1026_flush_user_cache_range)
 150         mov     ip, #0
 151         sub     r3, r1, r0                      @ calculate total size
 152         cmp     r3, #CACHE_DLIMIT
 153         bhs     __flush_whole_cache
 154
 155 #ifndef CONFIG_CPU_DCACHE_DISABLE
 156 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 157         add     r0, r0, #CACHE_DLINESIZE
 158         cmp     r0, r1
 159         blo     1b
 160 #endif
 161         tst     r2, #VM_EXEC
 162 #ifndef CONFIG_CPU_ICACHE_DISABLE
 163         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 164 #endif
 165         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 166         mov     pc, lr
 167
 168 /*
 169  *      coherent_kern_range(start, end)
 170  *
 171  *      Ensure coherency between the Icache and the Dcache in the
 172  *      region described by start.  If you have non-snooping
 173  *      Harvard caches, you need to implement this function.
 174  *
 175  *      - start - virtual start address
 176  *      - end   - virtual end address
 177  */
 178 ENTRY(arm1026_coherent_kern_range)
 179         /* FALLTHROUGH */
 180 /*
 181  *      coherent_user_range(start, end)
 182  *
 183  *      Ensure coherency between the Icache and the Dcache in the
 184  *      region described by start.  If you have non-snooping
 185  *      Harvard caches, you need to implement this function.
 186  *
 187  *      - start - virtual start address
 188  *      - end   - virtual end address
 189  */
 190 ENTRY(arm1026_coherent_user_range)
 191         mov     ip, #0
 192         bic     r0, r0, #CACHE_DLINESIZE - 1
 193 1:
 194 #ifndef CONFIG_CPU_DCACHE_DISABLE
 195         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 196 #endif
 197 #ifndef CONFIG_CPU_ICACHE_DISABLE
 198         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 199 #endif
 200         add     r0, r0, #CACHE_DLINESIZE
 201         cmp     r0, r1
 202         blo     1b
 203         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 204         mov     pc, lr
 205
 206 /*
 207  *      flush_kern_dcache_area(void *addr, size_t size)
 208  *
 209  *      Ensure no D cache aliasing occurs, either with itself or
 210  *      the I cache
 211  *
 212  *      - addr  - kernel address
 213  *      - size  - region size
 214  */
 215 ENTRY(arm1026_flush_kern_dcache_area)
 216         mov     ip, #0
 217 #ifndef CONFIG_CPU_DCACHE_DISABLE
 218         add     r1, r0, r1
 219 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 220         add     r0, r0, #CACHE_DLINESIZE
 221         cmp     r0, r1
 222         blo     1b
 223 #endif
 224         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 225         mov     pc, lr
 226
 227 /*
 228  *      dma_inv_range(start, end)
 229  *
 230  *      Invalidate (discard) the specified virtual address range.
 231  *      May not write back any entries.  If 'start' or 'end'
 232  *      are not cache line aligned, those lines must be written
 233  *      back.
 234  *
 235  *      - start - virtual start address
 236  *      - end   - virtual end address
 237  *
 238  * (same as v4wb)
 239  */
 240 arm1026_dma_inv_range:
 241         mov     ip, #0
 242 #ifndef CONFIG_CPU_DCACHE_DISABLE
 243         tst     r0, #CACHE_DLINESIZE - 1
 244         bic     r0, r0, #CACHE_DLINESIZE - 1
 245         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 246         tst     r1, #CACHE_DLINESIZE - 1
 247         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 248 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 249         add     r0, r0, #CACHE_DLINESIZE
 250         cmp     r0, r1
 251         blo     1b
 252 #endif
 253         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 254         mov     pc, lr
 255
 256 /*
 257  *      dma_clean_range(start, end)
 258  *
 259  *      Clean the specified virtual address range.
 260  *
 261  *      - start - virtual start address
 262  *      - end   - virtual end address
 263  *
 264  * (same as v4wb)
 265  */
 266 arm1026_dma_clean_range:
 267         mov     ip, #0
 268 #ifndef CONFIG_CPU_DCACHE_DISABLE
 269         bic     r0, r0, #CACHE_DLINESIZE - 1
 270 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 271         add     r0, r0, #CACHE_DLINESIZE
 272         cmp     r0, r1
 273         blo     1b
 274 #endif
 275         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 276         mov     pc, lr
 277
 278 /*
 279  *      dma_flush_range(start, end)
 280  *
 281  *      Clean and invalidate the specified virtual address range.
 282  *
 283  *      - start - virtual start address
 284  *      - end   - virtual end address
 285  */
 286 ENTRY(arm1026_dma_flush_range)
 287         mov     ip, #0
 288 #ifndef CONFIG_CPU_DCACHE_DISABLE
 289         bic     r0, r0, #CACHE_DLINESIZE - 1
 290 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 291         add     r0, r0, #CACHE_DLINESIZE
 292         cmp     r0, r1
 293         blo     1b
 294 #endif
 295         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 296         mov     pc, lr
 297
 298 /*
 299  *      dma_map_area(start, size, dir)
 300  *      - start - kernel virtual start address
 301  *      - size  - size of region
 302  *      - dir   - DMA direction
 303  */
 304 ENTRY(arm1026_dma_map_area)
 305         add     r1, r1, r0
 306         cmp     r2, #DMA_TO_DEVICE
 307         beq     arm1026_dma_clean_range
 308         bcs     arm1026_dma_inv_range
 309         b       arm1026_dma_flush_range
 310 ENDPROC(arm1026_dma_map_area)
 311
 312 /*
 313  *      dma_unmap_area(start, size, dir)
 314  *      - start - kernel virtual start address
 315  *      - size  - size of region
 316  *      - dir   - DMA direction
 317  */
 318 ENTRY(arm1026_dma_unmap_area)
 319         mov     pc, lr
 320 ENDPROC(arm1026_dma_unmap_area)
 321
 322 ENTRY(arm1026_cache_fns)
 323         .long   arm1026_flush_kern_cache_all
 324         .long   arm1026_flush_user_cache_all
 325         .long   arm1026_flush_user_cache_range
 326         .long   arm1026_coherent_kern_range
 327         .long   arm1026_coherent_user_range
 328         .long   arm1026_flush_kern_dcache_area
 329         .long   arm1026_dma_map_area
 330         .long   arm1026_dma_unmap_area
 331         .long   arm1026_dma_flush_range
 332
 333         .align  5
 334 ENTRY(cpu_arm1026_dcache_clean_area)
 335 #ifndef CONFIG_CPU_DCACHE_DISABLE
 336         mov     ip, #0
 337 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 338         add     r0, r0, #CACHE_DLINESIZE
 339         subs    r1, r1, #CACHE_DLINESIZE
 340         bhi     1b
 341 #endif
 342         mov     pc, lr
 343
 344 /* =============================== PageTable ============================== */
 345
 346 /*
 347  * cpu_arm1026_switch_mm(pgd)
 348  *
 349  * Set the translation base pointer to be as described by pgd.
 350  *
 351  * pgd: new page tables
 352  */
 353         .align  5
 354 ENTRY(cpu_arm1026_switch_mm)
 355 #ifdef CONFIG_MMU
 356         mov     r1, #0
 357 #ifndef CONFIG_CPU_DCACHE_DISABLE
 358 1:      mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
 359         bne     1b
 360 #endif
 361 #ifndef CONFIG_CPU_ICACHE_DISABLE
 362         mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
 363 #endif
 364         mcr     p15, 0, r1, c7, c10, 4          @ drain WB
 365         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 366         mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
 367 #endif
 368         mov     pc, lr
 369
 370 /*
 371  * cpu_arm1026_set_pte_ext(ptep, pte, ext)
 372  *
 373  * Set a PTE and flush it out
 374  */
 375         .align  5
 376 ENTRY(cpu_arm1026_set_pte_ext)
 377 #ifdef CONFIG_MMU
 378         armv3_set_pte_ext
 379         mov     r0, r0
 380 #ifndef CONFIG_CPU_DCACHE_DISABLE
 381         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 382 #endif
 383 #endif /* CONFIG_MMU */
 384         mov     pc, lr
 385
 386
 387         __CPUINIT
 388
 389         .type   __arm1026_setup, #function
 390 __arm1026_setup:
 391         mov     r0, #0
 392         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 393         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 394 #ifdef CONFIG_MMU
 395         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 396         mcr     p15, 0, r4, c2, c0              @ load page table pointer
 397 #endif
 398 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 399         mov     r0, #4                          @ explicitly disable writeback
 400         mcr     p15, 7, r0, c15, c0, 0
 401 #endif
 402         adr     r5, arm1026_crval
 403         ldmia   r5, {r5, r6}
 404         mrc     p15, 0, r0, c1, c0              @ get control register v4
 405         bic     r0, r0, r5
 406         orr     r0, r0, r6
 407 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 408         orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 409 #endif
 410         mov     pc, lr
 411         .size   __arm1026_setup, . - __arm1026_setup
 412
 413         /*
 414          *  R
 415          * .RVI ZFRS BLDP WCAM
 416          * .011 1001 ..11 0101
 417          *
 418          */
 419         .type   arm1026_crval, #object
 420 arm1026_crval:
 421         crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
 422
 423         __INITDATA
 424
 425 /*
 426  * Purpose : Function pointers used to access above functions - all calls
 427  *           come through these
 428  */
 429         .type   arm1026_processor_functions, #object
 430 arm1026_processor_functions:
 431         .word   v5t_early_abort
 432         .word   legacy_pabort
 433         .word   cpu_arm1026_proc_init
 434         .word   cpu_arm1026_proc_fin
 435         .word   cpu_arm1026_reset
 436         .word   cpu_arm1026_do_idle
 437         .word   cpu_arm1026_dcache_clean_area
 438         .word   cpu_arm1026_switch_mm
 439         .word   cpu_arm1026_set_pte_ext
 440         .size   arm1026_processor_functions, . - arm1026_processor_functions
 441
 442         .section .rodata
 443
 444         .type   cpu_arch_name, #object
 445 cpu_arch_name:
 446         .asciz  "armv5tej"
 447         .size   cpu_arch_name, . - cpu_arch_name
 448
 449         .type   cpu_elf_name, #object
 450 cpu_elf_name:
 451         .asciz  "v5"
 452         .size   cpu_elf_name, . - cpu_elf_name
 453         .align
 454
 455         .type   cpu_arm1026_name, #object
 456 cpu_arm1026_name:
 457         .asciz  "ARM1026EJ-S"
 458         .size   cpu_arm1026_name, . - cpu_arm1026_name
 459
 460         .align
 461
 462         .section ".proc.info.init", #alloc, #execinstr
 463
 464         .type   __arm1026_proc_info,#object
 465 __arm1026_proc_info:
 466         .long   0x4106a260                      @ ARM 1026EJ-S (v5TEJ)
 467         .long   0xff0ffff0
 468         .long   PMD_TYPE_SECT | \
 469                 PMD_BIT4 | \
 470                 PMD_SECT_AP_WRITE | \
 471                 PMD_SECT_AP_READ
 472         .long   PMD_TYPE_SECT | \
 473                 PMD_BIT4 | \
 474                 PMD_SECT_AP_WRITE | \
 475                 PMD_SECT_AP_READ
 476         b       __arm1026_setup
 477         .long   cpu_arch_name
 478         .long   cpu_elf_name
 479         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
 480         .long   cpu_arm1026_name
 481         .long   arm1026_processor_functions
 482         .long   v4wbi_tlb_fns
 483         .long   v4wb_user_fns
 484         .long   arm1026_cache_fns
 485         .size   __arm1026_proc_info, . - __arm1026_proc_info