arch/arm/mm/proc-fa526.S

   1 /*
   2  *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
   3  *
   4  *  Written by : Luke Lee
   5  *  Copyright (C) 2005 Faraday Corp.
   6  *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  *
  14  * These are the low level assembler for performing cache and TLB
  15  * functions on the fa526.
  16  */
  17 #include <linux/linkage.h>
  18 #include <linux/init.h>
  19 #include <asm/assembler.h>
  20 #include <asm/hwcap.h>
  21 #include <asm/pgtable-hwdef.h>
  22 #include <asm/pgtable.h>
  23 #include <asm/page.h>
  24 #include <asm/ptrace.h>
  25 #include <asm/system.h>
  26
  27 #include "proc-macros.S"
  28
  29 #define CACHE_DLINESIZE 16
  30
  31         .text
  32 /*
  33  * cpu_fa526_proc_init()
  34  */
  35 ENTRY(cpu_fa526_proc_init)
  36         mov     pc, lr
  37
  38 /*
  39  * cpu_fa526_proc_fin()
  40  */
  41 ENTRY(cpu_fa526_proc_fin)
  42         stmfd   sp!, {lr}
  43         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  44         msr     cpsr_c, ip
  45         bl      fa_flush_kern_cache_all
  46         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  47         bic     r0, r0, #0x1000                 @ ...i............
  48         bic     r0, r0, #0x000e                 @ ............wca.
  49         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  50         nop
  51         nop
  52         ldmfd   sp!, {pc}
  53
  54 /*
  55  * cpu_fa526_reset(loc)
  56  *
  57  * Perform a soft reset of the system.  Put the CPU into the
  58  * same state as it would be if it had been reset, and branch
  59  * to what would be the reset vector.
  60  *
  61  * loc: location to jump to for soft reset
  62  */
  63         .align  4
  64 ENTRY(cpu_fa526_reset)
  65 /* TODO: Use CP8 if possible... */
  66         mov     ip, #0
  67         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  68         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  69 #ifdef CONFIG_MMU
  70         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  71 #endif
  72         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  73         bic     ip, ip, #0x000f                 @ ............wcam
  74         bic     ip, ip, #0x1100                 @ ...i...s........
  75         bic     ip, ip, #0x0800                 @ BTB off
  76         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  77         nop
  78         nop
  79         mov     pc, r0
  80
  81 /*
  82  * cpu_fa526_do_idle()
  83  */
  84         .align  4
  85 ENTRY(cpu_fa526_do_idle)
  86         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
  87         mov     pc, lr
  88
  89
  90 ENTRY(cpu_fa526_dcache_clean_area)
  91 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  92         add     r0, r0, #CACHE_DLINESIZE
  93         subs    r1, r1, #CACHE_DLINESIZE
  94         bhi     1b
  95         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
  96         mov     pc, lr
  97
  98 /* =============================== PageTable ============================== */
  99
 100 /*
 101  * cpu_fa526_switch_mm(pgd)
 102  *
 103  * Set the translation base pointer to be as described by pgd.
 104  *
 105  * pgd: new page tables
 106  */
 107         .align  4
 108 ENTRY(cpu_fa526_switch_mm)
 109 #ifdef CONFIG_MMU
 110         mov     ip, #0
 111 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 112         mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
 113 #else
 114         mcr     p15, 0, ip, c7, c14, 0          @ clean and invalidate whole D cache
 115 #endif
 116         mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
 117         mcr     p15, 0, ip, c7, c5, 6           @ invalidate BTB since mm changed
 118         mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
 119         mcr     p15, 0, ip, c7, c5, 4           @ prefetch flush
 120         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 121         mcr     p15, 0, ip, c8, c7, 0           @ invalidate UTLB
 122 #endif
 123         mov     pc, lr
 124
 125 /*
 126  * cpu_fa526_set_pte_ext(ptep, pte, ext)
 127  *
 128  * Set a PTE and flush it out
 129  */
 130         .align  4
 131 ENTRY(cpu_fa526_set_pte_ext)
 132 #ifdef CONFIG_MMU
 133         armv3_set_pte_ext
 134         mov     r0, r0
 135         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 136         mov     r0, #0
 137         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 138 #endif
 139         mov     pc, lr
 140
 141         __INIT
 142
 143         .type   __fa526_setup, #function
 144 __fa526_setup:
 145         /* On return of this routine, r0 must carry correct flags for CFG register */
 146         mov     r0, #0
 147         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 148         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 149 #ifdef CONFIG_MMU
 150         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 151 #endif
 152         mcr     p15, 0, r0, c7, c5, 5           @ invalidate IScratchpad RAM
 153
 154         mov     r0, #1
 155         mcr     p15, 0, r0, c1, c1, 0           @ turn-on ECR
 156
 157         mov     r0, #0
 158         mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB All
 159         mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
 160         mcr     p15, 0, r0, c7, c5, 4           @ prefetch flush
 161
 162         mov     r0, #0x1f                       @ Domains 0, 1 = manager, 2 = client
 163         mcr     p15, 0, r0, c3, c0              @ load domain access register
 164
 165         mrc     p15, 0, r0, c1, c0              @ get control register v4
 166         ldr     r5, fa526_cr1_clear
 167         bic     r0, r0, r5
 168         ldr     r5, fa526_cr1_set
 169         orr     r0, r0, r5
 170         mov     pc, lr
 171         .size   __fa526_setup, . - __fa526_setup
 172
 173         /*
 174          * .RVI ZFRS BLDP WCAM
 175          * ..11 1001 .111 1101
 176          *
 177          */
 178         .type   fa526_cr1_clear, #object
 179         .type   fa526_cr1_set, #object
 180 fa526_cr1_clear:
 181         .word   0x3f3f
 182 fa526_cr1_set:
 183         .word   0x397D
 184
 185         __INITDATA
 186
 187 /*
 188  * Purpose : Function pointers used to access above functions - all calls
 189  *           come through these
 190  */
 191         .type   fa526_processor_functions, #object
 192 fa526_processor_functions:
 193         .word   v4_early_abort
 194         .word   legacy_pabort
 195         .word   cpu_fa526_proc_init
 196         .word   cpu_fa526_proc_fin
 197         .word   cpu_fa526_reset
 198         .word   cpu_fa526_do_idle
 199         .word   cpu_fa526_dcache_clean_area
 200         .word   cpu_fa526_switch_mm
 201         .word   cpu_fa526_set_pte_ext
 202         .size   fa526_processor_functions, . - fa526_processor_functions
 203
 204         .section ".rodata"
 205
 206         .type   cpu_arch_name, #object
 207 cpu_arch_name:
 208         .asciz  "armv4"
 209         .size   cpu_arch_name, . - cpu_arch_name
 210
 211         .type   cpu_elf_name, #object
 212 cpu_elf_name:
 213         .asciz  "v4"
 214         .size   cpu_elf_name, . - cpu_elf_name
 215
 216         .type   cpu_fa526_name, #object
 217 cpu_fa526_name:
 218         .asciz  "FA526"
 219         .size   cpu_fa526_name, . - cpu_fa526_name
 220
 221         .align
 222
 223         .section ".proc.info.init", #alloc, #execinstr
 224
 225         .type   __fa526_proc_info,#object
 226 __fa526_proc_info:
 227         .long   0x66015261
 228         .long   0xff01fff1
 229         .long   PMD_TYPE_SECT | \
 230                 PMD_SECT_BUFFERABLE | \
 231                 PMD_SECT_CACHEABLE | \
 232                 PMD_BIT4 | \
 233                 PMD_SECT_AP_WRITE | \
 234                 PMD_SECT_AP_READ
 235         .long   PMD_TYPE_SECT | \
 236                 PMD_BIT4 | \
 237                 PMD_SECT_AP_WRITE | \
 238                 PMD_SECT_AP_READ
 239         b       __fa526_setup
 240         .long   cpu_arch_name
 241         .long   cpu_elf_name
 242         .long   HWCAP_SWP | HWCAP_HALF
 243         .long   cpu_fa526_name
 244         .long   fa526_processor_functions
 245         .long   fa_tlb_fns
 246         .long   fa_user_fns
 247         .long   fa_cache_fns
 248         .size   __fa526_proc_info, . - __fa526_proc_info