arch/arm/mm/proc-v6.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v6.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *  Modified by Catalin Marinas for noMMU support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  This is the "shell" of the ARMv6 processor support.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/linkage.h>
  15 #include <asm/assembler.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/hwcap.h>
  18 #include <asm/pgtable-hwdef.h>
  19 #include <asm/pgtable.h>
  20
  21 #include "proc-macros.S"
  22
  23 #define D_CACHE_LINE_SIZE       32
  24
  25 #define TTB_C           (1 << 0)
  26 #define TTB_S           (1 << 1)
  27 #define TTB_IMP         (1 << 2)
  28 #define TTB_RGN_NC      (0 << 3)
  29 #define TTB_RGN_WBWA    (1 << 3)
  30 #define TTB_RGN_WT      (2 << 3)
  31 #define TTB_RGN_WB      (3 << 3)
  32
  33 #ifndef CONFIG_SMP
  34 #define TTB_FLAGS       TTB_RGN_WBWA
  35 #define PMD_FLAGS       PMD_SECT_WB
  36 #else
  37 #define TTB_FLAGS       TTB_RGN_WBWA|TTB_S
  38 #define PMD_FLAGS       PMD_SECT_WBWA|PMD_SECT_S
  39 #endif
  40
  41 ENTRY(cpu_v6_proc_init)
  42         mov     pc, lr
  43
  44 ENTRY(cpu_v6_proc_fin)
  45         stmfd   sp!, {lr}
  46         cpsid   if                              @ disable interrupts
  47         bl      v6_flush_kern_cache_all
  48         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  49         bic     r0, r0, #0x1000                 @ ...i............
  50         bic     r0, r0, #0x0006                 @ .............ca.
  51         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  52         ldmfd   sp!, {pc}
  53
  54 /*
  55  *      cpu_v6_reset(loc)
  56  *
  57  *      Perform a soft reset of the system.  Put the CPU into the
  58  *      same state as it would be if it had been reset, and branch
  59  *      to what would be the reset vector.
  60  *
  61  *      - loc   - location to jump to for soft reset
  62  *
  63  *      It is assumed that:
  64  */
  65         .align  5
  66 ENTRY(cpu_v6_reset)
  67         mov     pc, r0
  68
  69 /*
  70  *      cpu_v6_do_idle()
  71  *
  72  *      Idle the processor (eg, wait for interrupt).
  73  *
  74  *      IRQs are already disabled.
  75  */
  76 ENTRY(cpu_v6_do_idle)
  77         mov     r1, #0
  78         mcr     p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
  79         mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
  80         mov     pc, lr
  81
  82 ENTRY(cpu_v6_dcache_clean_area)
  83 #ifndef TLB_CAN_READ_FROM_L1_CACHE
  84 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  85         add     r0, r0, #D_CACHE_LINE_SIZE
  86         subs    r1, r1, #D_CACHE_LINE_SIZE
  87         bhi     1b
  88 #endif
  89         mov     pc, lr
  90
  91 /*
  92  *      cpu_arm926_switch_mm(pgd_phys, tsk)
  93  *
  94  *      Set the translation table base pointer to be pgd_phys
  95  *
  96  *      - pgd_phys - physical address of new TTB
  97  *
  98  *      It is assumed that:
  99  *      - we are not using split page tables
 100  */
 101 ENTRY(cpu_v6_switch_mm)
 102 #ifdef CONFIG_MMU
 103         mov     r2, #0
 104         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
 105         orr     r0, r0, #TTB_FLAGS
 106         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 107         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
 108         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
 109         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
 110 #endif
 111         mov     pc, lr
 112
 113 /*
 114  *      cpu_v6_set_pte_ext(ptep, pte, ext)
 115  *
 116  *      Set a level 2 translation table entry.
 117  *
 118  *      - ptep  - pointer to level 2 translation table entry
 119  *                (hardware version is stored at -1024 bytes)
 120  *      - pte   - PTE value to store
 121  *      - ext   - value for extended PTE bits
 122  */
 123         armv6_mt_table cpu_v6
 124
 125 ENTRY(cpu_v6_set_pte_ext)
 126 #ifdef CONFIG_MMU
 127         armv6_set_pte_ext cpu_v6
 128 #endif
 129         mov     pc, lr
 130
 131
 132
 133         .type   cpu_v6_name, #object
 134 cpu_v6_name:
 135         .asciz  "ARMv6-compatible processor"
 136         .size   cpu_v6_name, . - cpu_v6_name
 137
 138         .type   cpu_pj4_name, #object
 139 cpu_pj4_name:
 140         .asciz  "Marvell PJ4 processor"
 141         .size   cpu_pj4_name, . - cpu_pj4_name
 142
 143         .align
 144
 145         __INIT
 146
 147 /*
 148  *      __v6_setup
 149  *
 150  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 151  *      on.  Return in r0 the new CP15 C1 control register setting.
 152  *
 153  *      We automatically detect if we have a Harvard cache, and use the
 154  *      Harvard cache control instructions insead of the unified cache
 155  *      control instructions.
 156  *
 157  *      This should be able to cover all ARMv6 cores.
 158  *
 159  *      It is assumed that:
 160  *      - cache type register is implemented
 161  */
 162 __v6_setup:
 163 #ifdef CONFIG_SMP
 164         mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
 165         orr     r0, r0, #0x20
 166         mcr     p15, 0, r0, c1, c0, 1
 167 #endif
 168
 169         mov     r0, #0
 170         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
 171         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 172         mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
 173         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 174 #ifdef CONFIG_MMU
 175         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
 176         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
 177         orr     r4, r4, #TTB_FLAGS
 178         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 179 #endif /* CONFIG_MMU */
 180         adr     r5, v6_crval
 181         ldmia   r5, {r5, r6}
 182 #ifdef CONFIG_CPU_ENDIAN_BE8
 183         orr     r6, r6, #1 << 25                @ big-endian page tables
 184 #endif
 185         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 186         bic     r0, r0, r5                      @ clear bits them
 187         orr     r0, r0, r6                      @ set them
 188         mov     pc, lr                          @ return to head.S:__ret
 189
 190         /*
 191          *         V X F   I D LR
 192          * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
 193          * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
 194          *         0 110       0011 1.00 .111 1101 < we want
 195          */
 196         .type   v6_crval, #object
 197 v6_crval:
 198         crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
 199
 200         .type   v6_processor_functions, #object
 201 ENTRY(v6_processor_functions)
 202         .word   v6_early_abort
 203         .word   v6_pabort
 204         .word   cpu_v6_proc_init
 205         .word   cpu_v6_proc_fin
 206         .word   cpu_v6_reset
 207         .word   cpu_v6_do_idle
 208         .word   cpu_v6_dcache_clean_area
 209         .word   cpu_v6_switch_mm
 210         .word   cpu_v6_set_pte_ext
 211         .size   v6_processor_functions, . - v6_processor_functions
 212
 213         .type   cpu_arch_name, #object
 214 cpu_arch_name:
 215         .asciz  "armv6"
 216         .size   cpu_arch_name, . - cpu_arch_name
 217
 218         .type   cpu_elf_name, #object
 219 cpu_elf_name:
 220         .asciz  "v6"
 221         .size   cpu_elf_name, . - cpu_elf_name
 222         .align
 223
 224         .section ".proc.info.init", #alloc, #execinstr
 225
 226         /*
 227          * Match any ARMv6 processor core.
 228          */
 229         .type   __v6_proc_info, #object
 230 __v6_proc_info:
 231         .long   0x0007b000
 232         .long   0x0007f000
 233         .long   PMD_TYPE_SECT | \
 234                 PMD_SECT_AP_WRITE | \
 235                 PMD_SECT_AP_READ | \
 236                 PMD_FLAGS
 237         .long   PMD_TYPE_SECT | \
 238                 PMD_SECT_XN | \
 239                 PMD_SECT_AP_WRITE | \
 240                 PMD_SECT_AP_READ
 241         b       __v6_setup
 242         .long   cpu_arch_name
 243         .long   cpu_elf_name
 244         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
 245         .long   cpu_v6_name
 246         .long   v6_processor_functions
 247         .long   v6wbi_tlb_fns
 248         .long   v6_user_fns
 249         .long   v6_cache_fns
 250         .size   __v6_proc_info, . - __v6_proc_info
 251
 252         .type   __pj4_v6_proc_info, #object
 253 __pj4_v6_proc_info:
 254         .long   0x560f5810
 255         .long   0xff0ffff0
 256         .long   PMD_TYPE_SECT | \
 257                 PMD_SECT_AP_WRITE | \
 258                 PMD_SECT_AP_READ | \
 259                 PMD_FLAGS
 260         .long   PMD_TYPE_SECT | \
 261                 PMD_SECT_XN | \
 262                 PMD_SECT_AP_WRITE | \
 263                 PMD_SECT_AP_READ
 264         b       __v6_setup
 265         .long   cpu_arch_name
 266         .long   cpu_elf_name
 267         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 268         .long   cpu_pj4_name
 269         .long   v6_processor_functions
 270         .long   v6wbi_tlb_fns
 271         .long   v6_user_fns
 272         .long   v6_cache_fns
 273         .size   __pj4_v6_proc_info, . - __pj4_v6_proc_info