arch/arm/mm/proc-v7.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv7 processor support.
  11  */
  12 #include <linux/linkage.h>
  13 #include <asm/assembler.h>
  14 #include <asm/asm-offsets.h>
  15 #include <asm/elf.h>
  16 #include <asm/pgtable-hwdef.h>
  17 #include <asm/pgtable.h>
  18
  19 #include "proc-macros.S"
  20
  21 #define TTB_C           (1 << 0)
  22 #define TTB_S           (1 << 1)
  23 #define TTB_RGN_OC_WT   (2 << 3)
  24 #define TTB_RGN_OC_WB   (3 << 3)
  25
  26 ENTRY(cpu_v7_proc_init)
  27         mov     pc, lr
  28
  29 ENTRY(cpu_v7_proc_fin)
  30         mov     pc, lr
  31
  32 /*
  33  *      cpu_v7_reset(loc)
  34  *
  35  *      Perform a soft reset of the system.  Put the CPU into the
  36  *      same state as it would be if it had been reset, and branch
  37  *      to what would be the reset vector.
  38  *
  39  *      - loc   - location to jump to for soft reset
  40  *
  41  *      It is assumed that:
  42  */
  43         .align  5
  44 ENTRY(cpu_v7_reset)
  45         mov     pc, r0
  46
  47 /*
  48  *      cpu_v7_do_idle()
  49  *
  50  *      Idle the processor (eg, wait for interrupt).
  51  *
  52  *      IRQs are already disabled.
  53  */
  54 ENTRY(cpu_v7_do_idle)
  55         .long   0xe320f003                      @ ARM V7 WFI instruction
  56         mov     pc, lr
  57
  58 ENTRY(cpu_v7_dcache_clean_area)
  59 #ifndef TLB_CAN_READ_FROM_L1_CACHE
  60         dcache_line_size r2, r3
  61 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  62         add     r0, r0, r2
  63         subs    r1, r1, r2
  64         bhi     1b
  65         dsb
  66 #endif
  67         mov     pc, lr
  68
  69 /*
  70  *      cpu_v7_switch_mm(pgd_phys, tsk)
  71  *
  72  *      Set the translation table base pointer to be pgd_phys
  73  *
  74  *      - pgd_phys - physical address of new TTB
  75  *
  76  *      It is assumed that:
  77  *      - we are not using split page tables
  78  */
  79 ENTRY(cpu_v7_switch_mm)
  80         mov     r2, #0
  81         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
  82         orr     r0, r0, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
  83         mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
  84         isb
  85 1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
  86         isb
  87         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
  88         isb
  89         mov     pc, lr
  90
  91 /*
  92  *      cpu_v7_set_pte_ext(ptep, pte)
  93  *
  94  *      Set a level 2 translation table entry.
  95  *
  96  *      - ptep  - pointer to level 2 translation table entry
  97  *                (hardware version is stored at -1024 bytes)
  98  *      - pte   - PTE value to store
  99  *      - ext   - value for extended PTE bits
 100  *
 101  *      Permissions:
 102  *        YUWD  APX AP1 AP0     SVC     User
 103  *        0xxx   0   0   0      no acc  no acc
 104  *        100x   1   0   1      r/o     no acc
 105  *        10x0   1   0   1      r/o     no acc
 106  *        1011   0   0   1      r/w     no acc
 107  *        110x   0   1   0      r/w     r/o
 108  *        11x0   0   1   0      r/w     r/o
 109  *        1111   0   1   1      r/w     r/w
 110  */
 111 ENTRY(cpu_v7_set_pte_ext)
 112         str     r1, [r0], #-2048                @ linux version
 113
 114         bic     r3, r1, #0x000003f0
 115         bic     r3, r3, #0x00000003
 116         orr     r3, r3, r2
 117         orr     r3, r3, #PTE_EXT_AP0 | 2
 118
 119         tst     r1, #L_PTE_WRITE
 120         tstne   r1, #L_PTE_DIRTY
 121         orreq   r3, r3, #PTE_EXT_APX
 122
 123         tst     r1, #L_PTE_USER
 124         orrne   r3, r3, #PTE_EXT_AP1
 125         tstne   r3, #PTE_EXT_APX
 126         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
 127
 128         tst     r1, #L_PTE_YOUNG
 129         biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
 130
 131         tst     r1, #L_PTE_EXEC
 132         orreq   r3, r3, #PTE_EXT_XN
 133
 134         tst     r1, #L_PTE_PRESENT
 135         moveq   r3, #0
 136
 137         str     r3, [r0]
 138         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
 139         mov     pc, lr
 140
 141 cpu_v7_name:
 142         .ascii  "ARMv7 Processor"
 143         .align
 144
 145         .section ".text.init", #alloc, #execinstr
 146
 147 /*
 148  *      __v7_setup
 149  *
 150  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 151  *      on.  Return in r0 the new CP15 C1 control register setting.
 152  *
 153  *      We automatically detect if we have a Harvard cache, and use the
 154  *      Harvard cache control instructions insead of the unified cache
 155  *      control instructions.
 156  *
 157  *      This should be able to cover all ARMv7 cores.
 158  *
 159  *      It is assumed that:
 160  *      - cache type register is implemented
 161  */
 162 __v7_setup:
 163         adr     r12, __v7_setup_stack           @ the local stack
 164         stmia   r12, {r0-r5, r7, r9, r11, lr}
 165         bl      v7_flush_dcache_all
 166         ldmia   r12, {r0-r5, r7, r9, r11, lr}
 167         mov     r10, #0
 168 #ifdef HARVARD_CACHE
 169         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 170 #endif
 171         dsb
 172         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 173         mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
 174         orr     r4, r4, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
 175         mcr     p15, 0, r4, c2, c0, 0           @ load TTB0
 176         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 177         mov     r10, #0x1f                      @ domains 0, 1 = manager
 178         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
 179 #ifndef CONFIG_CPU_L2CACHE_DISABLE
 180         @ L2 cache configuration in the L2 aux control register
 181         mrc     p15, 1, r10, c9, c0, 2
 182         bic     r10, r10, #(1 << 16)            @ L2 outer cache
 183         mcr     p15, 1, r10, c9, c0, 2
 184         @ L2 cache is enabled in the aux control register
 185         mrc     p15, 0, r10, c1, c0, 1
 186         orr     r10, r10, #2
 187         mcr     p15, 0, r10, c1, c0, 1
 188 #endif
 189         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 190         ldr     r10, cr1_clear                  @ get mask for bits to clear
 191         bic     r0, r0, r10                     @ clear bits them
 192         ldr     r10, cr1_set                    @ get mask for bits to set
 193         orr     r0, r0, r10                     @ set them
 194         mov     pc, lr                          @ return to head.S:__ret
 195
 196         /*
 197          *         V X F   I D LR
 198          * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
 199          * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
 200          *         0 110       0011 1.00 .111 1101 < we want
 201          */
 202         .type   cr1_clear, #object
 203         .type   cr1_set, #object
 204 cr1_clear:
 205         .word   0x0120c302
 206 cr1_set:
 207         .word   0x00c0387d
 208
 209 __v7_setup_stack:
 210         .space  4 * 11                          @ 11 registers
 211
 212         .type   v7_processor_functions, #object
 213 ENTRY(v7_processor_functions)
 214         .word   v7_early_abort
 215         .word   cpu_v7_proc_init
 216         .word   cpu_v7_proc_fin
 217         .word   cpu_v7_reset
 218         .word   cpu_v7_do_idle
 219         .word   cpu_v7_dcache_clean_area
 220         .word   cpu_v7_switch_mm
 221         .word   cpu_v7_set_pte_ext
 222         .size   v7_processor_functions, . - v7_processor_functions
 223
 224         .type   cpu_arch_name, #object
 225 cpu_arch_name:
 226         .asciz  "armv7"
 227         .size   cpu_arch_name, . - cpu_arch_name
 228
 229         .type   cpu_elf_name, #object
 230 cpu_elf_name:
 231         .asciz  "v7"
 232         .size   cpu_elf_name, . - cpu_elf_name
 233         .align
 234
 235         .section ".proc.info.init", #alloc, #execinstr
 236
 237         /*
 238          * Match any ARMv7 processor core.
 239          */
 240         .type   __v7_proc_info, #object
 241 __v7_proc_info:
 242         .long   0x000f0000              @ Required ID value
 243         .long   0x000f0000              @ Mask for ID
 244         .long   PMD_TYPE_SECT | \
 245                 PMD_SECT_BUFFERABLE | \
 246                 PMD_SECT_CACHEABLE | \
 247                 PMD_SECT_AP_WRITE | \
 248                 PMD_SECT_AP_READ
 249         .long   PMD_TYPE_SECT | \
 250                 PMD_SECT_XN | \
 251                 PMD_SECT_AP_WRITE | \
 252                 PMD_SECT_AP_READ
 253         b       __v7_setup
 254         .long   cpu_arch_name
 255         .long   cpu_elf_name
 256         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 257         .long   cpu_v7_name
 258         .long   v7_processor_functions
 259         .long   v6wbi_tlb_fns
 260         .long   v6_user_fns
 261         .long   v7_cache_fns
 262         .size   __v7_proc_info, . - __v7_proc_info