arch/arm/mm/tlb-v4wbi.S

   1 /*
   2  *  linux/arch/arm/mm/tlbv4wbi.S
   3  *
   4  *  Copyright (C) 1997-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  ARM architecture version 4 and version 5 TLB handling functions.
  11  *  These assume a split I/D TLBs, with a write buffer.
  12  *
  13  *  Processors: ARM920 ARM922 ARM925 ARM926 XScale
  14  */
  15 #include <linux/linkage.h>
  16 #include <linux/init.h>
  17 #include <asm/constants.h>
  18 #include <asm/tlbflush.h>
  19 #include "proc-macros.S"
  20
  21 /*
  22  *      v4wb_flush_user_tlb_range(start, end, mm)
  23  *
  24  *      Invalidate a range of TLB entries in the specified address space.
  25  *
  26  *      - start - range start address
  27  *      - end   - range end address
  28  *      - mm    - mm_struct describing address space
  29  */
  30         .align  5
  31 ENTRY(v4wbi_flush_user_tlb_range)
  32         vma_vm_mm ip, r2
  33         act_mm  r3                              @ get current->active_mm
  34         eors    r3, ip, r3                      @ == mm ?
  35         movne   pc, lr                          @ no, we dont do anything
  36         mov     r3, #0
  37         mcr     p15, 0, r3, c7, c10, 4          @ drain WB
  38         vma_vm_flags r2, r2
  39         bic     r0, r0, #0x0ff
  40         bic     r0, r0, #0xf00
  41 1:      tst     r2, #VM_EXEC
  42         mcrne   p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
  43         mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
  44         add     r0, r0, #PAGE_SZ
  45         cmp     r0, r1
  46         blo     1b
  47         mov     pc, lr
  48
  49 ENTRY(v4wbi_flush_kern_tlb_range)
  50         mov     r3, #0
  51         mcr     p15, 0, r3, c7, c10, 4          @ drain WB
  52         bic     r0, r0, #0x0ff
  53         bic     r0, r0, #0xf00
  54 1:      mcr     p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
  55         mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
  56         add     r0, r0, #PAGE_SZ
  57         cmp     r0, r1
  58         blo     1b
  59         mov     pc, lr
  60
  61         __INITDATA
  62
  63         .type   v4wbi_tlb_fns, #object
  64 ENTRY(v4wbi_tlb_fns)
  65         .long   v4wbi_flush_user_tlb_range
  66         .long   v4wbi_flush_kern_tlb_range
  67         .long   v4wbi_tlb_flags
  68         .size   v4wbi_tlb_fns, . - v4wbi_tlb_fns