arch/arm/plat-iop/time.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * arch/arm/plat-iop/time.c
   4  *
   5  * Timer code for IOP32x and IOP33x based systems
   6  *
   7  * Author: Deepak Saxena <dsaxena@mvista.com>
   8  *
   9  * Copyright 2002-2003 MontaVista Software Inc.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/time.h>
  15 #include <linux/init.h>
  16 #include <linux/timex.h>
  17 #include <linux/io.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/clockchips.h>
  20 #include <linux/export.h>
  21 #include <linux/sched_clock.h>
  22 #include <mach/hardware.h>
  23 #include <asm/irq.h>
  24 #include <linux/uaccess.h>
  25 #include <asm/mach/irq.h>
  26 #include <asm/mach/time.h>
  27 #include <mach/time.h>
  28
  29 /*
  30  * Minimum clocksource/clockevent timer range in seconds
  31  */
  32 #define IOP_MIN_RANGE 4
  33
  34 /*
  35  * IOP clocksource (free-running timer 1).
  36  */
  37 static u64 notrace iop_clocksource_read(struct clocksource *unused)
  38 {
  39         return 0xffffffffu - read_tcr1();
  40 }
  41
  42 static struct clocksource iop_clocksource = {
  43         .name           = "iop_timer1",
  44         .rating         = 300,
  45         .read           = iop_clocksource_read,
  46         .mask           = CLOCKSOURCE_MASK(32),
  47         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  48 };
  49
  50 /*
  51  * IOP sched_clock() implementation via its clocksource.
  52  */
  53 static u64 notrace iop_read_sched_clock(void)
  54 {
  55         return 0xffffffffu - read_tcr1();
  56 }
  57
  58 /*
  59  * IOP clockevents (interrupting timer 0).
  60  */
  61 static int iop_set_next_event(unsigned long delta,
  62                               struct clock_event_device *unused)
  63 {
  64         u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
  65
  66         BUG_ON(delta == 0);
  67         write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
  68         write_tcr0(delta);
  69         write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
  70
  71         return 0;
  72 }
  73
  74 static unsigned long ticks_per_jiffy;
  75
  76 static int iop_set_periodic(struct clock_event_device *evt)
  77 {
  78         u32 tmr = read_tmr0();
  79
  80         write_tmr0(tmr & ~IOP_TMR_EN);
  81         write_tcr0(ticks_per_jiffy - 1);
  82         write_trr0(ticks_per_jiffy - 1);
  83         tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
  84
  85         write_tmr0(tmr);
  86         return 0;
  87 }
  88
  89 static int iop_set_oneshot(struct clock_event_device *evt)
  90 {
  91         u32 tmr = read_tmr0();
  92
  93         /* ->set_next_event sets period and enables timer */
  94         tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
  95         write_tmr0(tmr);
  96         return 0;
  97 }
  98
  99 static int iop_shutdown(struct clock_event_device *evt)
 100 {
 101         u32 tmr = read_tmr0();
 102
 103         tmr &= ~IOP_TMR_EN;
 104         write_tmr0(tmr);
 105         return 0;
 106 }
 107
 108 static int iop_resume(struct clock_event_device *evt)
 109 {
 110         u32 tmr = read_tmr0();
 111
 112         tmr |= IOP_TMR_EN;
 113         write_tmr0(tmr);
 114         return 0;
 115 }
 116
 117 static struct clock_event_device iop_clockevent = {
 118         .name                   = "iop_timer0",
 119         .features               = CLOCK_EVT_FEAT_PERIODIC |
 120                                   CLOCK_EVT_FEAT_ONESHOT,
 121         .rating                 = 300,
 122         .set_next_event         = iop_set_next_event,
 123         .set_state_shutdown     = iop_shutdown,
 124         .set_state_periodic     = iop_set_periodic,
 125         .tick_resume            = iop_resume,
 126         .set_state_oneshot      = iop_set_oneshot,
 127 };
 128
 129 static irqreturn_t
 130 iop_timer_interrupt(int irq, void *dev_id)
 131 {
 132         struct clock_event_device *evt = dev_id;
 133
 134         write_tisr(1);
 135         evt->event_handler(evt);
 136         return IRQ_HANDLED;
 137 }
 138
 139 static struct irqaction iop_timer_irq = {
 140         .name           = "IOP Timer Tick",
 141         .handler        = iop_timer_interrupt,
 142         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 143         .dev_id         = &iop_clockevent,
 144 };
 145
 146 static unsigned long iop_tick_rate;
 147 unsigned long get_iop_tick_rate(void)
 148 {
 149         return iop_tick_rate;
 150 }
 151 EXPORT_SYMBOL(get_iop_tick_rate);
 152
 153 void __init iop_init_time(unsigned long tick_rate)
 154 {
 155         u32 timer_ctl;
 156
 157         sched_clock_register(iop_read_sched_clock, 32, tick_rate);
 158
 159         ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
 160         iop_tick_rate = tick_rate;
 161
 162         timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
 163                         IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
 164
 165         /*
 166          * Set up interrupting clockevent timer 0.
 167          */
 168         write_tmr0(timer_ctl & ~IOP_TMR_EN);
 169         write_tisr(1);
 170         setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
 171         iop_clockevent.cpumask = cpumask_of(0);
 172         clockevents_config_and_register(&iop_clockevent, tick_rate,
 173                                         0xf, 0xfffffffe);
 174
 175         /*
 176          * Set up free-running clocksource timer 1.
 177          */
 178         write_trr1(0xffffffff);
 179         write_tcr1(0xffffffff);
 180         write_tmr1(timer_ctl);
 181         clocksource_register_hz(&iop_clocksource, tick_rate);
 182 }