arch/arm/plat-mxc/avic.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <mach/common.h>
  24 #include <asm/mach/irq.h>
  25 #include <mach/hardware.h>
  26
  27 #include "irq-common.h"
  28
  29 #define AVIC_INTCNTL            0x00    /* int control reg */
  30 #define AVIC_NIMASK             0x04    /* int mask reg */
  31 #define AVIC_INTENNUM           0x08    /* int enable number reg */
  32 #define AVIC_INTDISNUM          0x0C    /* int disable number reg */
  33 #define AVIC_INTENABLEH         0x10    /* int enable reg high */
  34 #define AVIC_INTENABLEL         0x14    /* int enable reg low */
  35 #define AVIC_INTTYPEH           0x18    /* int type reg high */
  36 #define AVIC_INTTYPEL           0x1C    /* int type reg low */
  37 #define AVIC_NIPRIORITY(x)      (0x20 + 4 * (7 - (x))) /* int priority */
  38 #define AVIC_NIVECSR            0x40    /* norm int vector/status */
  39 #define AVIC_FIVECSR            0x44    /* fast int vector/status */
  40 #define AVIC_INTSRCH            0x48    /* int source reg high */
  41 #define AVIC_INTSRCL            0x4C    /* int source reg low */
  42 #define AVIC_INTFRCH            0x50    /* int force reg high */
  43 #define AVIC_INTFRCL            0x54    /* int force reg low */
  44 #define AVIC_NIPNDH             0x58    /* norm int pending high */
  45 #define AVIC_NIPNDL             0x5C    /* norm int pending low */
  46 #define AVIC_FIPNDH             0x60    /* fast int pending high */
  47 #define AVIC_FIPNDL             0x64    /* fast int pending low */
  48
  49 void __iomem *avic_base;
  50
  51 #ifdef CONFIG_MXC_IRQ_PRIOR
  52 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
  53 {
  54         unsigned int temp;
  55         unsigned int mask = 0x0F << irq % 8 * 4;
  56
  57         if (irq >= MXC_INTERNAL_IRQS)
  58                 return -EINVAL;;
  59
  60         temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
  61         temp &= ~mask;
  62         temp |= prio & mask;
  63
  64         __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
  65
  66         return 0;
  67 }
  68 #endif
  69
  70 #ifdef CONFIG_FIQ
  71 static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
  72 {
  73         unsigned int irqt;
  74
  75         if (irq >= MXC_INTERNAL_IRQS)
  76                 return -EINVAL;
  77
  78         if (irq < MXC_INTERNAL_IRQS / 2) {
  79                 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
  80                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
  81         } else {
  82                 irq -= MXC_INTERNAL_IRQS / 2;
  83                 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
  84                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
  85         }
  86
  87         return 0;
  88 }
  89 #endif /* CONFIG_FIQ */
  90
  91 /* Disable interrupt number "irq" in the AVIC */
  92 static void mxc_mask_irq(struct irq_data *d)
  93 {
  94         __raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
  95 }
  96
  97 /* Enable interrupt number "irq" in the AVIC */
  98 static void mxc_unmask_irq(struct irq_data *d)
  99 {
 100         __raw_writel(d->irq, avic_base + AVIC_INTENNUM);
 101 }
 102
 103 static struct mxc_irq_chip mxc_avic_chip = {
 104         .base = {
 105                 .irq_ack = mxc_mask_irq,
 106                 .irq_mask = mxc_mask_irq,
 107                 .irq_unmask = mxc_unmask_irq,
 108         },
 109 #ifdef CONFIG_MXC_IRQ_PRIOR
 110         .set_priority = avic_irq_set_priority,
 111 #endif
 112 #ifdef CONFIG_FIQ
 113         .set_irq_fiq = avic_set_irq_fiq,
 114 #endif
 115 };
 116
 117 /*
 118  * This function initializes the AVIC hardware and disables all the
 119  * interrupts. It registers the interrupt enable and disable functions
 120  * to the kernel for each interrupt source.
 121  */
 122 void __init mxc_init_irq(void __iomem *irqbase)
 123 {
 124         int i;
 125
 126         avic_base = irqbase;
 127
 128         /* put the AVIC into the reset value with
 129          * all interrupts disabled
 130          */
 131         __raw_writel(0, avic_base + AVIC_INTCNTL);
 132         __raw_writel(0x1f, avic_base + AVIC_NIMASK);
 133
 134         /* disable all interrupts */
 135         __raw_writel(0, avic_base + AVIC_INTENABLEH);
 136         __raw_writel(0, avic_base + AVIC_INTENABLEL);
 137
 138         /* all IRQ no FIQ */
 139         __raw_writel(0, avic_base + AVIC_INTTYPEH);
 140         __raw_writel(0, avic_base + AVIC_INTTYPEL);
 141         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
 142                 irq_set_chip(i, &mxc_avic_chip.base);
 143                 irq_set_handler(i, handle_level_irq);
 144                 set_irq_flags(i, IRQF_VALID);
 145         }
 146
 147         /* Set default priority value (0) for all IRQ's */
 148         for (i = 0; i < 8; i++)
 149                 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 150
 151 #ifdef CONFIG_FIQ
 152         /* Initialize FIQ */
 153         init_FIQ();
 154 #endif
 155
 156         printk(KERN_INFO "MXC IRQ initialized\n");
 157 }
 158