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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - arch/arm/plat-mxc/include/mach/mx27.h
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * This contains i.MX27-specific hardware definitions. For those
6 * hardware pieces that are common between i.MX21 and i.MX27, have a
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24 #ifndef __MACH_MX27_H__
25 #define __MACH_MX27_H__
31 #define MX27_AIPI_BASE_ADDR 0x10000000
32 #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
33 #define MX27_AIPI_SIZE SZ_1M
34 #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
35 #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
36 #define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
37 #define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
38 #define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
39 #define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
40 #define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
41 #define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
42 #define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
43 #define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
44 #define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
45 #define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
46 #define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
47 #define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
48 #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
49 #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
50 #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
51 #define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
52 #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
53 #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
54 #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
55 #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
56 #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
57 #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
58 #define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
59 #define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
60 #define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
61 #define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
62 #define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
63 #define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
64 #define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
65 #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
66 #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
67 #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
68 #define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
69 #define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR
70 #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
71 #define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
72 #define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
73 #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
74 #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
75 #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
76 #define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
77 #define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
78 #define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
79 #define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
80 #define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
81 #define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
82 #define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
84 #define MX27_AVIC_BASE_ADDR 0x10040000
87 #define MX27_ROMP_BASE_ADDR 0x10041000
89 #define MX27_SAHB1_BASE_ADDR 0x80000000
90 #define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
91 #define MX27_SAHB1_SIZE SZ_1M
92 #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
93 #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
95 /* Memory regions and CS */
96 #define MX27_SDRAM_BASE_ADDR 0xa0000000
97 #define MX27_CSD1_BASE_ADDR 0xb0000000
99 #define MX27_CS0_BASE_ADDR 0xc0000000
100 #define MX27_CS1_BASE_ADDR 0xc8000000
101 #define MX27_CS2_BASE_ADDR 0xd0000000
102 #define MX27_CS3_BASE_ADDR 0xd2000000
103 #define MX27_CS4_BASE_ADDR 0xd4000000
104 #define MX27_CS5_BASE_ADDR 0xd6000000
106 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */
107 #define MX27_X_MEMC_BASE_ADDR 0xd8000000
108 #define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
109 #define MX27_X_MEMC_SIZE SZ_1M
110 #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
111 #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
112 #define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
113 #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
114 #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
116 #define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
117 #define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
118 #define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
119 #define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
121 #define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
124 #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
126 #define MX27_IO_P2V(x) ( \
127 IMX_IO_P2V_MODULE(x, MX27_AIPI) ?: \
128 IMX_IO_P2V_MODULE(x, MX27_SAHB1) ?: \
129 IMX_IO_P2V_MODULE(x, MX27_X_MEMC))
130 #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
132 #ifndef __ASSEMBLER__
133 static inline void mx27_setup_weimcs(size_t cs
,
134 unsigned upper
, unsigned lower
, unsigned addional
)
136 __raw_writel(upper
, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs
)));
137 __raw_writel(lower
, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs
)));
138 __raw_writel(addional
, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs
)));
142 /* fixed interrupt numbers */
143 #define MX27_INT_I2C2 1
144 #define MX27_INT_GPT6 2
145 #define MX27_INT_GPT5 3
146 #define MX27_INT_GPT4 4
147 #define MX27_INT_RTIC 5
148 #define MX27_INT_CSPI3 6
149 #define MX27_INT_SDHC 7
150 #define MX27_INT_GPIO 8
151 #define MX27_INT_SDHC3 9
152 #define MX27_INT_SDHC2 10
153 #define MX27_INT_SDHC1 11
154 #define MX27_INT_I2C1 12
155 #define MX27_INT_SSI2 13
156 #define MX27_INT_SSI1 14
157 #define MX27_INT_CSPI2 15
158 #define MX27_INT_CSPI1 16
159 #define MX27_INT_UART4 17
160 #define MX27_INT_UART3 18
161 #define MX27_INT_UART2 19
162 #define MX27_INT_UART1 20
163 #define MX27_INT_KPP 21
164 #define MX27_INT_RTC 22
165 #define MX27_INT_PWM 23
166 #define MX27_INT_GPT3 24
167 #define MX27_INT_GPT2 25
168 #define MX27_INT_GPT1 26
169 #define MX27_INT_WDOG 27
170 #define MX27_INT_PCMCIA 28
171 #define MX27_INT_NFC 29
172 #define MX27_INT_ATA 30
173 #define MX27_INT_CSI 31
174 #define MX27_INT_DMACH0 32
175 #define MX27_INT_DMACH1 33
176 #define MX27_INT_DMACH2 34
177 #define MX27_INT_DMACH3 35
178 #define MX27_INT_DMACH4 36
179 #define MX27_INT_DMACH5 37
180 #define MX27_INT_DMACH6 38
181 #define MX27_INT_DMACH7 39
182 #define MX27_INT_DMACH8 40
183 #define MX27_INT_DMACH9 41
184 #define MX27_INT_DMACH10 42
185 #define MX27_INT_DMACH11 43
186 #define MX27_INT_DMACH12 44
187 #define MX27_INT_DMACH13 45
188 #define MX27_INT_DMACH14 46
189 #define MX27_INT_DMACH15 47
190 #define MX27_INT_UART6 48
191 #define MX27_INT_UART5 49
192 #define MX27_INT_FEC 50
193 #define MX27_INT_EMMAPRP 51
194 #define MX27_INT_EMMAPP 52
195 #define MX27_INT_VPU 53
196 #define MX27_INT_USB1 54
197 #define MX27_INT_USB2 55
198 #define MX27_INT_USB3 56
199 #define MX27_INT_SCC_SMN 57
200 #define MX27_INT_SCC_SCM 58
201 #define MX27_INT_SAHARA 59
202 #define MX27_INT_SLCDC 60
203 #define MX27_INT_LCDC 61
204 #define MX27_INT_IIM 62
205 #define MX27_INT_CCM 63
207 /* fixed DMA request numbers */
208 #define MX27_DMA_REQ_CSPI3_RX 1
209 #define MX27_DMA_REQ_CSPI3_TX 2
210 #define MX27_DMA_REQ_EXT 3
211 #define MX27_DMA_REQ_MSHC 4
212 #define MX27_DMA_REQ_SDHC2 6
213 #define MX27_DMA_REQ_SDHC1 7
214 #define MX27_DMA_REQ_SSI2_RX0 8
215 #define MX27_DMA_REQ_SSI2_TX0 9
216 #define MX27_DMA_REQ_SSI2_RX1 10
217 #define MX27_DMA_REQ_SSI2_TX1 11
218 #define MX27_DMA_REQ_SSI1_RX0 12
219 #define MX27_DMA_REQ_SSI1_TX0 13
220 #define MX27_DMA_REQ_SSI1_RX1 14
221 #define MX27_DMA_REQ_SSI1_TX1 15
222 #define MX27_DMA_REQ_CSPI2_RX 16
223 #define MX27_DMA_REQ_CSPI2_TX 17
224 #define MX27_DMA_REQ_CSPI1_RX 18
225 #define MX27_DMA_REQ_CSPI1_TX 19
226 #define MX27_DMA_REQ_UART4_RX 20
227 #define MX27_DMA_REQ_UART4_TX 21
228 #define MX27_DMA_REQ_UART3_RX 22
229 #define MX27_DMA_REQ_UART3_TX 23
230 #define MX27_DMA_REQ_UART2_RX 24
231 #define MX27_DMA_REQ_UART2_TX 25
232 #define MX27_DMA_REQ_UART1_RX 26
233 #define MX27_DMA_REQ_UART1_TX 27
234 #define MX27_DMA_REQ_ATA_TX 28
235 #define MX27_DMA_REQ_ATA_RCV 29
236 #define MX27_DMA_REQ_CSI_STAT 30
237 #define MX27_DMA_REQ_CSI_RX 31
238 #define MX27_DMA_REQ_UART5_TX 32
239 #define MX27_DMA_REQ_UART5_RX 33
240 #define MX27_DMA_REQ_UART6_TX 34
241 #define MX27_DMA_REQ_UART6_RX 35
242 #define MX27_DMA_REQ_SDHC3 36
243 #define MX27_DMA_REQ_NFC 37
245 /* silicon revisions specific to i.MX27 */
246 #define CHIP_REV_1_0 0x00
247 #define CHIP_REV_2_0 0x01
250 extern int mx27_revision(void);
253 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
254 /* these should go away */
255 #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
256 #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
257 #define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
258 #define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
259 #define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
260 #define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
261 #define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
262 #define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
263 #define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
264 #define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
265 #define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
266 #define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
267 #define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
268 #define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
269 #define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
270 #define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
271 #define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
272 #define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
273 #define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
274 #define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
275 #define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
276 #define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
277 #define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
278 #define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
279 #define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
280 #define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
281 #define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
282 #define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
283 #define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
284 #define X_MEMC_SIZE MX27_X_MEMC_SIZE
285 #define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
286 #define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
287 #define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
288 #define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
289 #define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
290 #define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
291 #define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
292 #define MXC_INT_I2C2 MX27_INT_I2C2
293 #define MXC_INT_GPT6 MX27_INT_GPT6
294 #define MXC_INT_GPT5 MX27_INT_GPT5
295 #define MXC_INT_GPT4 MX27_INT_GPT4
296 #define MXC_INT_RTIC MX27_INT_RTIC
297 #define MXC_INT_SDHC MX27_INT_SDHC
298 #define MXC_INT_SDHC3 MX27_INT_SDHC3
299 #define MXC_INT_ATA MX27_INT_ATA
300 #define MXC_INT_UART6 MX27_INT_UART6
301 #define MXC_INT_UART5 MX27_INT_UART5
302 #define MXC_INT_FEC MX27_INT_FEC
303 #define MXC_INT_VPU MX27_INT_VPU
304 #define MXC_INT_USB1 MX27_INT_USB1
305 #define MXC_INT_USB2 MX27_INT_USB2
306 #define MXC_INT_USB3 MX27_INT_USB3
307 #define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
308 #define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
309 #define MXC_INT_SAHARA MX27_INT_SAHARA
310 #define MXC_INT_IIM MX27_INT_IIM
311 #define MXC_INT_CCM MX27_INT_CCM
312 #define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
313 #define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
314 #define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
315 #define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
316 #define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
317 #define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
318 #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
319 #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
320 #define DMA_REQ_NFC MX27_DMA_REQ_NFC
323 #endif /* ifndef __MACH_MX27_H__ */