2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
12 #include <linux/dmaengine.h>
13 #include <linux/workqueue.h>
14 #include <linux/interrupt.h>
15 #include <linux/dmaengine.h>
17 /* dev types for memcpy */
18 #define STEDMA40_DEV_DST_MEMORY (-1)
19 #define STEDMA40_DEV_SRC_MEMORY (-1)
22 * Description of bitfields of channel_type variable is available in
27 #define STEDMA40_INFO_PRIO_TYPE_POS 2
28 #define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS)
29 #define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS)
32 #define STEDMA40_INFO_CH_MODE_TYPE_POS 6
33 #define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS)
34 #define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS)
35 #define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS)
38 #define STEDMA40_INFO_CH_MODE_OPT_POS 8
39 #define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
40 #define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
41 #define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
42 #define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
43 #define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
44 #define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
47 #define STEDMA40_INFO_TIM_POS 10
48 #define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)
49 #define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)
51 /* End of channel_type configuration */
53 #define STEDMA40_ESIZE_8_BIT 0x0
54 #define STEDMA40_ESIZE_16_BIT 0x1
55 #define STEDMA40_ESIZE_32_BIT 0x2
56 #define STEDMA40_ESIZE_64_BIT 0x3
58 /* The value 4 indicates that PEN-reg shall be set to 0 */
59 #define STEDMA40_PSIZE_PHY_1 0x4
60 #define STEDMA40_PSIZE_PHY_2 0x0
61 #define STEDMA40_PSIZE_PHY_4 0x1
62 #define STEDMA40_PSIZE_PHY_8 0x2
63 #define STEDMA40_PSIZE_PHY_16 0x3
66 * The number of elements differ in logical and
69 #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
70 #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
71 #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
72 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
74 /* Maximum number of possible physical channels */
75 #define STEDMA40_MAX_PHYS 32
77 enum stedma40_flow_ctrl
{
78 STEDMA40_NO_FLOW_CTRL
,
82 enum stedma40_endianess
{
83 STEDMA40_LITTLE_ENDIAN
,
87 enum stedma40_periph_data_width
{
88 STEDMA40_BYTE_WIDTH
= STEDMA40_ESIZE_8_BIT
,
89 STEDMA40_HALFWORD_WIDTH
= STEDMA40_ESIZE_16_BIT
,
90 STEDMA40_WORD_WIDTH
= STEDMA40_ESIZE_32_BIT
,
91 STEDMA40_DOUBLEWORD_WIDTH
= STEDMA40_ESIZE_64_BIT
94 enum stedma40_xfer_dir
{
95 STEDMA40_MEM_TO_MEM
= 1,
96 STEDMA40_MEM_TO_PERIPH
,
97 STEDMA40_PERIPH_TO_MEM
,
98 STEDMA40_PERIPH_TO_PERIPH
103 * struct stedma40_chan_cfg - dst/src channel configuration
105 * @endianess: Endianess of the src/dst hardware
106 * @data_width: Data width of the src/dst hardware
107 * @p_size: Burst size
108 * @flow_ctrl: Flow control on/off.
110 struct stedma40_half_channel_info
{
111 enum stedma40_endianess endianess
;
112 enum stedma40_periph_data_width data_width
;
114 enum stedma40_flow_ctrl flow_ctrl
;
118 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
120 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
121 * @channel_type: priority, mode, mode options and interrupt configuration.
122 * @src_dev_type: Src device type
123 * @dst_dev_type: Dst device type
124 * @src_info: Parameters for dst half channel
125 * @dst_info: Parameters for dst half channel
128 * This structure has to be filled by the client drivers.
129 * It is recommended to do all dma configurations for clients in the machine.
132 struct stedma40_chan_cfg
{
133 enum stedma40_xfer_dir dir
;
134 unsigned int channel_type
;
137 struct stedma40_half_channel_info src_info
;
138 struct stedma40_half_channel_info dst_info
;
142 * struct stedma40_platform_data - Configuration struct for the dma device.
144 * @dev_len: length of dev_tx and dev_rx
145 * @dev_tx: mapping between destination event line and io address
146 * @dev_rx: mapping between source event line and io address
147 * @memcpy: list of memcpy event lines
148 * @memcpy_len: length of memcpy
149 * @memcpy_conf_phy: default configuration of physical channel memcpy
150 * @memcpy_conf_log: default configuration of logical channel memcpy
151 * @disabled_channels: A vector, ending with -1, that marks physical channels
152 * that are for different reasons not available for the driver.
154 struct stedma40_platform_data
{
156 const dma_addr_t
*dev_tx
;
157 const dma_addr_t
*dev_rx
;
160 struct stedma40_chan_cfg
*memcpy_conf_phy
;
161 struct stedma40_chan_cfg
*memcpy_conf_log
;
162 int disabled_channels
[STEDMA40_MAX_PHYS
];
166 * stedma40_filter() - Provides stedma40_chan_cfg to the
167 * ste_dma40 dma driver via the dmaengine framework.
168 * does some checking of what's provided.
170 * Never directly called by client. It used by dmaengine.
171 * @chan: dmaengine handle.
172 * @data: Must be of type: struct stedma40_chan_cfg and is
173 * the configuration of the framework.
178 bool stedma40_filter(struct dma_chan
*chan
, void *data
);
181 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
182 * scattergatter lists.
184 * @chan: dmaengine handle
185 * @sgl_dst: Destination scatter list
186 * @sgl_src: Source scatter list
187 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
188 * and each element must match the corresponding element in the other scatter
190 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
193 struct dma_async_tx_descriptor
*stedma40_memcpy_sg(struct dma_chan
*chan
,
194 struct scatterlist
*sgl_dst
,
195 struct scatterlist
*sgl_src
,
196 unsigned int sgl_len
,
197 unsigned long flags
);
200 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
203 * @chan: dmaengine handle
204 * @addr: source or destination physicall address.
205 * @size: bytes to transfer
206 * @direction: direction of transfer
207 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
211 dma_async_tx_descriptor
*stedma40_slave_mem(struct dma_chan
*chan
,
214 enum dma_data_direction direction
,
217 struct scatterlist sg
;
218 sg_init_table(&sg
, 1);
219 sg
.dma_address
= addr
;
222 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,