2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
29 #include <asm/system.h>
30 #include <asm/hardware.h>
34 #include <asm/arch/tc.h>
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE
, DMA_CH_PARAMS_SET_DONE
, DMA_CH_STARTED
,
40 DMA_CH_QUEUED
, DMA_CH_NOTSTARTED
, DMA_CH_PAUSED
, DMA_CH_LINK_ENABLED
43 enum { DMA_CHAIN_STARTED
, DMA_CHAIN_NOTSTARTED
};
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
52 static int enable_1510_mode
= 0;
60 void (* callback
)(int lch
, u16 ch_status
, void *data
);
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
75 #ifndef CONFIG_ARCH_OMAP1
76 struct dma_link_info
{
78 int no_of_lchs_linked
;
89 static struct dma_link_info dma_linked_lch
[OMAP_LOGICAL_DMA_CH_COUNT
];
91 /* Chain handling macros */
92 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
94 dma_linked_lch[chain_id].q_head = \
95 dma_linked_lch[chain_id].q_tail = \
96 dma_linked_lch[chain_id].q_count = 0; \
98 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
99 (dma_linked_lch[chain_id].no_of_lchs_linked == \
100 dma_linked_lch[chain_id].q_count)
101 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
103 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
104 dma_linked_lch[chain_id].q_count) \
106 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
107 (0 == dma_linked_lch[chain_id].q_count)
108 #define __OMAP_DMA_CHAIN_INCQ(end) \
109 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
110 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
112 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
113 dma_linked_lch[chain_id].q_count--; \
116 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
119 dma_linked_lch[chain_id].q_count++; \
122 static int dma_chan_count
;
124 static spinlock_t dma_chan_lock
;
125 static struct omap_dma_lch dma_chan
[OMAP_LOGICAL_DMA_CH_COUNT
];
127 static const u8 omap1_dma_irq
[OMAP_LOGICAL_DMA_CH_COUNT
] = {
128 INT_DMA_CH0_6
, INT_DMA_CH1_7
, INT_DMA_CH2_8
, INT_DMA_CH3
,
129 INT_DMA_CH4
, INT_DMA_CH5
, INT_1610_DMA_CH6
, INT_1610_DMA_CH7
,
130 INT_1610_DMA_CH8
, INT_1610_DMA_CH9
, INT_1610_DMA_CH10
,
131 INT_1610_DMA_CH11
, INT_1610_DMA_CH12
, INT_1610_DMA_CH13
,
132 INT_1610_DMA_CH14
, INT_1610_DMA_CH15
, INT_DMA_LCD
135 static inline void disable_lnk(int lch
);
136 static void omap_disable_channel_irq(int lch
);
137 static inline void omap_enable_channel_irq(int lch
);
139 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
142 #ifdef CONFIG_ARCH_OMAP15XX
143 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
144 int omap_dma_in_1510_mode(void)
146 return enable_1510_mode
;
149 #define omap_dma_in_1510_mode() 0
152 #ifdef CONFIG_ARCH_OMAP1
153 static inline int get_gdma_dev(int req
)
155 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
156 int shift
= ((req
- 1) % 5) * 6;
158 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
161 static inline void set_gdma_dev(int req
, int dev
)
163 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
164 int shift
= ((req
- 1) % 5) * 6;
168 l
&= ~(0x3f << shift
);
169 l
|= (dev
- 1) << shift
;
173 #define set_gdma_dev(req, dev) do {} while (0)
176 static void clear_lch_regs(int lch
)
179 u32 lch_base
= OMAP_DMA_BASE
+ lch
* 0x40;
181 for (i
= 0; i
< 0x2c; i
+= 2)
182 omap_writew(0, lch_base
+ i
);
185 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
190 if (cpu_class_is_omap1()) {
192 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
193 reg
= OMAP_TC_OCPT1_PRIOR
;
195 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
196 reg
= OMAP_TC_OCPT2_PRIOR
;
198 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
199 reg
= OMAP_TC_EMIFF_PRIOR
;
201 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
202 reg
= OMAP_TC_EMIFS_PRIOR
;
210 l
|= (priority
& 0xf) << 8;
214 if (cpu_class_is_omap2()) {
216 OMAP_DMA_CCR_REG(lch
) |= (1 << 6);
218 OMAP_DMA_CCR_REG(lch
) &= ~(1 << 6);
222 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
223 int frame_count
, int sync_mode
,
224 int dma_trigger
, int src_or_dst_synch
)
226 OMAP_DMA_CSDP_REG(lch
) &= ~0x03;
227 OMAP_DMA_CSDP_REG(lch
) |= data_type
;
229 if (cpu_class_is_omap1()) {
230 OMAP_DMA_CCR_REG(lch
) &= ~(1 << 5);
231 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
232 OMAP_DMA_CCR_REG(lch
) |= 1 << 5;
234 OMAP1_DMA_CCR2_REG(lch
) &= ~(1 << 2);
235 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
236 OMAP1_DMA_CCR2_REG(lch
) |= 1 << 2;
239 if (cpu_class_is_omap2() && dma_trigger
) {
240 u32 val
= OMAP_DMA_CCR_REG(lch
);
243 if (dma_trigger
> 63)
245 if (dma_trigger
> 31)
249 val
|= (dma_trigger
& 0x1f);
251 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
256 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
261 if (src_or_dst_synch
)
262 val
|= 1 << 24; /* source synch */
264 val
&= ~(1 << 24); /* dest synch */
266 OMAP_DMA_CCR_REG(lch
) = val
;
269 OMAP_DMA_CEN_REG(lch
) = elem_count
;
270 OMAP_DMA_CFN_REG(lch
) = frame_count
;
273 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
277 BUG_ON(omap_dma_in_1510_mode());
279 if (cpu_class_is_omap2()) {
284 w
= OMAP1_DMA_CCR2_REG(lch
) & ~0x03;
286 case OMAP_DMA_CONSTANT_FILL
:
289 case OMAP_DMA_TRANSPARENT_COPY
:
292 case OMAP_DMA_COLOR_DIS
:
297 OMAP1_DMA_CCR2_REG(lch
) = w
;
299 w
= OMAP1_DMA_LCH_CTRL_REG(lch
) & ~0x0f;
300 /* Default is channel type 2D */
302 OMAP1_DMA_COLOR_L_REG(lch
) = (u16
)color
;
303 OMAP1_DMA_COLOR_U_REG(lch
) = (u16
)(color
>> 16);
304 w
|= 1; /* Channel type G */
306 OMAP1_DMA_LCH_CTRL_REG(lch
) = w
;
309 void omap_set_dma_write_mode(int lch
, enum omap_dma_write_mode mode
)
311 if (cpu_class_is_omap2()) {
312 OMAP_DMA_CSDP_REG(lch
) &= ~(0x3 << 16);
313 OMAP_DMA_CSDP_REG(lch
) |= (mode
<< 16);
317 /* Note that src_port is only for omap1 */
318 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
319 unsigned long src_start
,
320 int src_ei
, int src_fi
)
322 if (cpu_class_is_omap1()) {
323 OMAP_DMA_CSDP_REG(lch
) &= ~(0x1f << 2);
324 OMAP_DMA_CSDP_REG(lch
) |= src_port
<< 2;
327 OMAP_DMA_CCR_REG(lch
) &= ~(0x03 << 12);
328 OMAP_DMA_CCR_REG(lch
) |= src_amode
<< 12;
330 if (cpu_class_is_omap1()) {
331 OMAP1_DMA_CSSA_U_REG(lch
) = src_start
>> 16;
332 OMAP1_DMA_CSSA_L_REG(lch
) = src_start
;
335 if (cpu_class_is_omap2())
336 OMAP2_DMA_CSSA_REG(lch
) = src_start
;
338 OMAP_DMA_CSEI_REG(lch
) = src_ei
;
339 OMAP_DMA_CSFI_REG(lch
) = src_fi
;
342 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
* params
)
344 omap_set_dma_transfer_params(lch
, params
->data_type
,
345 params
->elem_count
, params
->frame_count
,
346 params
->sync_mode
, params
->trigger
,
347 params
->src_or_dst_synch
);
348 omap_set_dma_src_params(lch
, params
->src_port
,
349 params
->src_amode
, params
->src_start
,
350 params
->src_ei
, params
->src_fi
);
352 omap_set_dma_dest_params(lch
, params
->dst_port
,
353 params
->dst_amode
, params
->dst_start
,
354 params
->dst_ei
, params
->dst_fi
);
355 if (params
->read_prio
|| params
->write_prio
)
356 omap_dma_set_prio_lch(lch
, params
->read_prio
,
360 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
362 if (cpu_class_is_omap2()) {
366 OMAP_DMA_CSEI_REG(lch
) = eidx
;
367 OMAP_DMA_CSFI_REG(lch
) = fidx
;
370 void omap_set_dma_src_data_pack(int lch
, int enable
)
372 OMAP_DMA_CSDP_REG(lch
) &= ~(1 << 6);
374 OMAP_DMA_CSDP_REG(lch
) |= (1 << 6);
377 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
379 unsigned int burst
= 0;
380 OMAP_DMA_CSDP_REG(lch
) &= ~(0x03 << 7);
382 switch (burst_mode
) {
383 case OMAP_DMA_DATA_BURST_DIS
:
385 case OMAP_DMA_DATA_BURST_4
:
386 if (cpu_class_is_omap2())
391 case OMAP_DMA_DATA_BURST_8
:
392 if (cpu_class_is_omap2()) {
396 /* not supported by current hardware on OMAP1
400 case OMAP_DMA_DATA_BURST_16
:
401 if (cpu_class_is_omap2()) {
405 /* OMAP1 don't support burst 16
411 OMAP_DMA_CSDP_REG(lch
) |= (burst
<< 7);
414 /* Note that dest_port is only for OMAP1 */
415 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
416 unsigned long dest_start
,
417 int dst_ei
, int dst_fi
)
419 if (cpu_class_is_omap1()) {
420 OMAP_DMA_CSDP_REG(lch
) &= ~(0x1f << 9);
421 OMAP_DMA_CSDP_REG(lch
) |= dest_port
<< 9;
424 OMAP_DMA_CCR_REG(lch
) &= ~(0x03 << 14);
425 OMAP_DMA_CCR_REG(lch
) |= dest_amode
<< 14;
427 if (cpu_class_is_omap1()) {
428 OMAP1_DMA_CDSA_U_REG(lch
) = dest_start
>> 16;
429 OMAP1_DMA_CDSA_L_REG(lch
) = dest_start
;
432 if (cpu_class_is_omap2())
433 OMAP2_DMA_CDSA_REG(lch
) = dest_start
;
435 OMAP_DMA_CDEI_REG(lch
) = dst_ei
;
436 OMAP_DMA_CDFI_REG(lch
) = dst_fi
;
439 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
441 if (cpu_class_is_omap2()) {
445 OMAP_DMA_CDEI_REG(lch
) = eidx
;
446 OMAP_DMA_CDFI_REG(lch
) = fidx
;
449 void omap_set_dma_dest_data_pack(int lch
, int enable
)
451 OMAP_DMA_CSDP_REG(lch
) &= ~(1 << 13);
453 OMAP_DMA_CSDP_REG(lch
) |= 1 << 13;
456 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
458 unsigned int burst
= 0;
459 OMAP_DMA_CSDP_REG(lch
) &= ~(0x03 << 14);
461 switch (burst_mode
) {
462 case OMAP_DMA_DATA_BURST_DIS
:
464 case OMAP_DMA_DATA_BURST_4
:
465 if (cpu_class_is_omap2())
470 case OMAP_DMA_DATA_BURST_8
:
471 if (cpu_class_is_omap2())
476 case OMAP_DMA_DATA_BURST_16
:
477 if (cpu_class_is_omap2()) {
481 /* OMAP1 don't support burst 16
485 printk(KERN_ERR
"Invalid DMA burst mode\n");
489 OMAP_DMA_CSDP_REG(lch
) |= (burst
<< 14);
492 static inline void omap_enable_channel_irq(int lch
)
497 if (cpu_class_is_omap1())
498 status
= OMAP_DMA_CSR_REG(lch
);
499 else if (cpu_class_is_omap2())
500 OMAP_DMA_CSR_REG(lch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
502 /* Enable some nice interrupts. */
503 OMAP_DMA_CICR_REG(lch
) = dma_chan
[lch
].enabled_irqs
;
506 static void omap_disable_channel_irq(int lch
)
508 if (cpu_class_is_omap2())
509 OMAP_DMA_CICR_REG(lch
) = 0;
512 void omap_enable_dma_irq(int lch
, u16 bits
)
514 dma_chan
[lch
].enabled_irqs
|= bits
;
517 void omap_disable_dma_irq(int lch
, u16 bits
)
519 dma_chan
[lch
].enabled_irqs
&= ~bits
;
522 static inline void enable_lnk(int lch
)
524 if (cpu_class_is_omap1())
525 OMAP_DMA_CLNK_CTRL_REG(lch
) &= ~(1 << 14);
527 /* Set the ENABLE_LNK bits */
528 if (dma_chan
[lch
].next_lch
!= -1)
529 OMAP_DMA_CLNK_CTRL_REG(lch
) =
530 dma_chan
[lch
].next_lch
| (1 << 15);
532 #ifndef CONFIG_ARCH_OMAP1
533 if (dma_chan
[lch
].next_linked_ch
!= -1)
534 OMAP_DMA_CLNK_CTRL_REG(lch
) =
535 dma_chan
[lch
].next_linked_ch
| (1 << 15);
539 static inline void disable_lnk(int lch
)
541 /* Disable interrupts */
542 if (cpu_class_is_omap1()) {
543 OMAP_DMA_CICR_REG(lch
) = 0;
544 /* Set the STOP_LNK bit */
545 OMAP_DMA_CLNK_CTRL_REG(lch
) |= 1 << 14;
548 if (cpu_class_is_omap2()) {
549 omap_disable_channel_irq(lch
);
550 /* Clear the ENABLE_LNK bit */
551 OMAP_DMA_CLNK_CTRL_REG(lch
) &= ~(1 << 15);
554 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
557 static inline void omap2_enable_irq_lch(int lch
)
561 if (!cpu_class_is_omap2())
564 val
= omap_readl(OMAP_DMA4_IRQENABLE_L0
);
566 omap_writel(val
, OMAP_DMA4_IRQENABLE_L0
);
569 int omap_request_dma(int dev_id
, const char *dev_name
,
570 void (* callback
)(int lch
, u16 ch_status
, void *data
),
571 void *data
, int *dma_ch_out
)
573 int ch
, free_ch
= -1;
575 struct omap_dma_lch
*chan
;
577 spin_lock_irqsave(&dma_chan_lock
, flags
);
578 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
579 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
586 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
589 chan
= dma_chan
+ free_ch
;
590 chan
->dev_id
= dev_id
;
592 if (cpu_class_is_omap1())
593 clear_lch_regs(free_ch
);
595 if (cpu_class_is_omap2())
596 omap_clear_dma(free_ch
);
598 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
600 chan
->dev_name
= dev_name
;
601 chan
->callback
= callback
;
603 #ifndef CONFIG_ARCH_OMAP1
605 chan
->next_linked_ch
= -1;
607 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
609 if (cpu_class_is_omap1())
610 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
611 else if (cpu_class_is_omap2())
612 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
613 OMAP2_DMA_TRANS_ERR_IRQ
;
615 if (cpu_is_omap16xx()) {
616 /* If the sync device is set, configure it dynamically. */
618 set_gdma_dev(free_ch
+ 1, dev_id
);
619 dev_id
= free_ch
+ 1;
621 /* Disable the 1510 compatibility mode and set the sync device
623 OMAP_DMA_CCR_REG(free_ch
) = dev_id
| (1 << 10);
624 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
625 OMAP_DMA_CCR_REG(free_ch
) = dev_id
;
628 if (cpu_class_is_omap2()) {
629 omap2_enable_irq_lch(free_ch
);
631 omap_enable_channel_irq(free_ch
);
632 /* Clear the CSR register and IRQ status register */
633 OMAP_DMA_CSR_REG(free_ch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
634 omap_writel(1 << free_ch
, OMAP_DMA4_IRQSTATUS_L0
);
637 *dma_ch_out
= free_ch
;
642 void omap_free_dma(int lch
)
646 spin_lock_irqsave(&dma_chan_lock
, flags
);
647 if (dma_chan
[lch
].dev_id
== -1) {
648 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
650 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
653 dma_chan
[lch
].dev_id
= -1;
654 dma_chan
[lch
].next_lch
= -1;
655 dma_chan
[lch
].callback
= NULL
;
656 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
658 if (cpu_class_is_omap1()) {
659 /* Disable all DMA interrupts for the channel. */
660 OMAP_DMA_CICR_REG(lch
) = 0;
661 /* Make sure the DMA transfer is stopped. */
662 OMAP_DMA_CCR_REG(lch
) = 0;
665 if (cpu_class_is_omap2()) {
667 /* Disable interrupts */
668 val
= omap_readl(OMAP_DMA4_IRQENABLE_L0
);
670 omap_writel(val
, OMAP_DMA4_IRQENABLE_L0
);
672 /* Clear the CSR register and IRQ status register */
673 OMAP_DMA_CSR_REG(lch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
674 omap_writel(1 << lch
, OMAP_DMA4_IRQSTATUS_L0
);
676 /* Disable all DMA interrupts for the channel. */
677 OMAP_DMA_CICR_REG(lch
) = 0;
679 /* Make sure the DMA transfer is stopped. */
680 OMAP_DMA_CCR_REG(lch
) = 0;
686 * @brief omap_dma_set_global_params : Set global priority settings for dma
689 * @param max_fifo_depth
690 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
691 * DMA_THREAD_RESERVE_ONET
692 * DMA_THREAD_RESERVE_TWOT
693 * DMA_THREAD_RESERVE_THREET
696 omap_dma_set_global_params(int arb_rate
, int max_fifo_depth
, int tparams
)
700 if (!cpu_class_is_omap2()) {
701 printk(KERN_ERR
"FIXME: no %s on 15xx/16xx\n", __func__
);
708 reg
= (arb_rate
& 0xff) << 16;
709 reg
|= (0xff & max_fifo_depth
);
711 omap_writel(reg
, OMAP_DMA4_GCR_REG
);
713 EXPORT_SYMBOL(omap_dma_set_global_params
);
716 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
719 * @param read_prio - Read priority
720 * @param write_prio - Write priority
721 * Both of the above can be set with one of the following values :
722 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
725 omap_dma_set_prio_lch(int lch
, unsigned char read_prio
,
726 unsigned char write_prio
)
730 if (unlikely((lch
< 0 || lch
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
731 printk(KERN_ERR
"Invalid channel id\n");
734 w
= OMAP_DMA_CCR_REG(lch
);
735 w
&= ~((1 << 6) | (1 << 26));
736 if (cpu_is_omap2430() || cpu_is_omap34xx())
737 w
|= ((read_prio
& 0x1) << 6) | ((write_prio
& 0x1) << 26);
739 w
|= ((read_prio
& 0x1) << 6);
741 OMAP_DMA_CCR_REG(lch
) = w
;
744 EXPORT_SYMBOL(omap_dma_set_prio_lch
);
747 * Clears any DMA state so the DMA engine is ready to restart with new buffers
748 * through omap_start_dma(). Any buffers in flight are discarded.
750 void omap_clear_dma(int lch
)
754 local_irq_save(flags
);
756 if (cpu_class_is_omap1()) {
758 OMAP_DMA_CCR_REG(lch
) &= ~OMAP_DMA_CCR_EN
;
760 /* Clear pending interrupts */
761 status
= OMAP_DMA_CSR_REG(lch
);
764 if (cpu_class_is_omap2()) {
766 u32 lch_base
= OMAP_DMA4_BASE
+ lch
* 0x60 + 0x80;
767 for (i
= 0; i
< 0x44; i
+= 4)
768 omap_writel(0, lch_base
+ i
);
771 local_irq_restore(flags
);
774 void omap_start_dma(int lch
)
776 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
777 int next_lch
, cur_lch
;
778 char dma_chan_link_map
[OMAP_LOGICAL_DMA_CH_COUNT
];
780 dma_chan_link_map
[lch
] = 1;
781 /* Set the link register of the first channel */
784 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
785 cur_lch
= dma_chan
[lch
].next_lch
;
787 next_lch
= dma_chan
[cur_lch
].next_lch
;
789 /* The loop case: we've been here already */
790 if (dma_chan_link_map
[cur_lch
])
792 /* Mark the current channel */
793 dma_chan_link_map
[cur_lch
] = 1;
796 omap_enable_channel_irq(cur_lch
);
799 } while (next_lch
!= -1);
800 } else if (cpu_class_is_omap2()) {
801 /* Errata: Need to write lch even if not using chaining */
802 OMAP_DMA_CLNK_CTRL_REG(lch
) = lch
;
805 omap_enable_channel_irq(lch
);
807 /* Errata: On ES2.0 BUFFERING disable must be set.
808 * This will always fail on ES1.0 */
809 if (cpu_is_omap24xx()) {
810 OMAP_DMA_CCR_REG(lch
) |= OMAP_DMA_CCR_EN
;
813 OMAP_DMA_CCR_REG(lch
) |= OMAP_DMA_CCR_EN
;
815 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
818 void omap_stop_dma(int lch
)
820 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
821 int next_lch
, cur_lch
= lch
;
822 char dma_chan_link_map
[OMAP_LOGICAL_DMA_CH_COUNT
];
824 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
826 /* The loop case: we've been here already */
827 if (dma_chan_link_map
[cur_lch
])
829 /* Mark the current channel */
830 dma_chan_link_map
[cur_lch
] = 1;
832 disable_lnk(cur_lch
);
834 next_lch
= dma_chan
[cur_lch
].next_lch
;
836 } while (next_lch
!= -1);
841 /* Disable all interrupts on the channel */
842 if (cpu_class_is_omap1())
843 OMAP_DMA_CICR_REG(lch
) = 0;
845 OMAP_DMA_CCR_REG(lch
) &= ~OMAP_DMA_CCR_EN
;
846 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
850 * Allows changing the DMA callback function or data. This may be needed if
851 * the driver shares a single DMA channel for multiple dma triggers.
853 int omap_set_dma_callback(int lch
,
854 void (* callback
)(int lch
, u16 ch_status
, void *data
),
862 spin_lock_irqsave(&dma_chan_lock
, flags
);
863 if (dma_chan
[lch
].dev_id
== -1) {
864 printk(KERN_ERR
"DMA callback for not set for free channel\n");
865 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
868 dma_chan
[lch
].callback
= callback
;
869 dma_chan
[lch
].data
= data
;
870 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
876 * Returns current physical source address for the given DMA channel.
877 * If the channel is running the caller must disable interrupts prior calling
878 * this function and process the returned value before re-enabling interrupt to
879 * prevent races with the interrupt handler. Note that in continuous mode there
880 * is a chance for CSSA_L register overflow inbetween the two reads resulting
881 * in incorrect return value.
883 dma_addr_t
omap_get_dma_src_pos(int lch
)
885 dma_addr_t offset
= 0;
887 if (cpu_class_is_omap1())
888 offset
= (dma_addr_t
) (OMAP1_DMA_CSSA_L_REG(lch
) |
889 (OMAP1_DMA_CSSA_U_REG(lch
) << 16));
891 if (cpu_class_is_omap2())
892 offset
= OMAP_DMA_CSAC_REG(lch
);
898 * Returns current physical destination address for the given DMA channel.
899 * If the channel is running the caller must disable interrupts prior calling
900 * this function and process the returned value before re-enabling interrupt to
901 * prevent races with the interrupt handler. Note that in continuous mode there
902 * is a chance for CDSA_L register overflow inbetween the two reads resulting
903 * in incorrect return value.
905 dma_addr_t
omap_get_dma_dst_pos(int lch
)
907 dma_addr_t offset
= 0;
909 if (cpu_class_is_omap1())
910 offset
= (dma_addr_t
) (OMAP1_DMA_CDSA_L_REG(lch
) |
911 (OMAP1_DMA_CDSA_U_REG(lch
) << 16));
913 if (cpu_class_is_omap2())
914 offset
= OMAP_DMA_CDAC_REG(lch
);
920 * Returns current source transfer counting for the given DMA channel.
921 * Can be used to monitor the progress of a transfer inside a block.
922 * It must be called with disabled interrupts.
924 int omap_get_dma_src_addr_counter(int lch
)
926 return (dma_addr_t
) OMAP_DMA_CSAC_REG(lch
);
929 int omap_dma_running(void)
933 /* Check if LCD DMA is running */
934 if (cpu_is_omap16xx())
935 if (omap_readw(OMAP1610_DMA_LCD_CCR
) & OMAP_DMA_CCR_EN
)
938 for (lch
= 0; lch
< dma_chan_count
; lch
++)
939 if (OMAP_DMA_CCR_REG(lch
) & OMAP_DMA_CCR_EN
)
946 * lch_queue DMA will start right after lch_head one is finished.
947 * For this DMA link to start, you still need to start (see omap_start_dma)
948 * the first one. That will fire up the entire queue.
950 void omap_dma_link_lch (int lch_head
, int lch_queue
)
952 if (omap_dma_in_1510_mode()) {
953 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
958 if ((dma_chan
[lch_head
].dev_id
== -1) ||
959 (dma_chan
[lch_queue
].dev_id
== -1)) {
960 printk(KERN_ERR
"omap_dma: trying to link "
961 "non requested channels\n");
965 dma_chan
[lch_head
].next_lch
= lch_queue
;
969 * Once the DMA queue is stopped, we can destroy it.
971 void omap_dma_unlink_lch (int lch_head
, int lch_queue
)
973 if (omap_dma_in_1510_mode()) {
974 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
979 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
980 dma_chan
[lch_head
].next_lch
== -1) {
981 printk(KERN_ERR
"omap_dma: trying to unlink "
982 "non linked channels\n");
987 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
988 (dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
)) {
989 printk(KERN_ERR
"omap_dma: You need to stop the DMA channels "
990 "before unlinking\n");
994 dma_chan
[lch_head
].next_lch
= -1;
997 #ifndef CONFIG_ARCH_OMAP1
998 /* Create chain of DMA channesls */
999 static void create_dma_lch_chain(int lch_head
, int lch_queue
)
1003 /* Check if this is the first link in chain */
1004 if (dma_chan
[lch_head
].next_linked_ch
== -1) {
1005 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1006 dma_chan
[lch_head
].prev_linked_ch
= lch_queue
;
1007 dma_chan
[lch_queue
].next_linked_ch
= lch_head
;
1008 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1011 /* a link exists, link the new channel in circular chain */
1013 dma_chan
[lch_queue
].next_linked_ch
=
1014 dma_chan
[lch_head
].next_linked_ch
;
1015 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1016 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1017 dma_chan
[dma_chan
[lch_queue
].next_linked_ch
].prev_linked_ch
=
1021 w
= OMAP_DMA_CLNK_CTRL_REG(lch_head
);
1024 OMAP_DMA_CLNK_CTRL_REG(lch_head
) = w
;
1026 w
= OMAP_DMA_CLNK_CTRL_REG(lch_queue
);
1028 w
|= (dma_chan
[lch_queue
].next_linked_ch
);
1029 OMAP_DMA_CLNK_CTRL_REG(lch_queue
) = w
;
1033 * @brief omap_request_dma_chain : Request a chain of DMA channels
1035 * @param dev_id - Device id using the dma channel
1036 * @param dev_name - Device name
1037 * @param callback - Call back function
1039 * @no_of_chans - Number of channels requested
1040 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1041 * OMAP_DMA_DYNAMIC_CHAIN
1042 * @params - Channel parameters
1044 * @return - Succes : 0
1045 * Failure: -EINVAL/-ENOMEM
1047 int omap_request_dma_chain(int dev_id
, const char *dev_name
,
1048 void (*callback
) (int chain_id
, u16 ch_status
,
1050 int *chain_id
, int no_of_chans
, int chain_mode
,
1051 struct omap_dma_channel_params params
)
1056 /* Is the chain mode valid ? */
1057 if (chain_mode
!= OMAP_DMA_STATIC_CHAIN
1058 && chain_mode
!= OMAP_DMA_DYNAMIC_CHAIN
) {
1059 printk(KERN_ERR
"Invalid chain mode requested\n");
1063 if (unlikely((no_of_chans
< 1
1064 || no_of_chans
> OMAP_LOGICAL_DMA_CH_COUNT
))) {
1065 printk(KERN_ERR
"Invalid Number of channels requested\n");
1069 /* Allocate a queue to maintain the status of the channels
1071 channels
= kmalloc(sizeof(*channels
) * no_of_chans
, GFP_KERNEL
);
1072 if (channels
== NULL
) {
1073 printk(KERN_ERR
"omap_dma: No memory for channel queue\n");
1077 /* request and reserve DMA channels for the chain */
1078 for (i
= 0; i
< no_of_chans
; i
++) {
1079 err
= omap_request_dma(dev_id
, dev_name
,
1080 callback
, 0, &channels
[i
]);
1083 for (j
= 0; j
< i
; j
++)
1084 omap_free_dma(channels
[j
]);
1086 printk(KERN_ERR
"omap_dma: Request failed %d\n", err
);
1089 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1090 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1093 * Allowing client drivers to set common parameters now,
1094 * so that later only relevant (src_start, dest_start
1095 * and element count) can be set
1097 omap_set_dma_params(channels
[i
], ¶ms
);
1100 *chain_id
= channels
[0];
1101 dma_linked_lch
[*chain_id
].linked_dmach_q
= channels
;
1102 dma_linked_lch
[*chain_id
].chain_mode
= chain_mode
;
1103 dma_linked_lch
[*chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1104 dma_linked_lch
[*chain_id
].no_of_lchs_linked
= no_of_chans
;
1106 for (i
= 0; i
< no_of_chans
; i
++)
1107 dma_chan
[channels
[i
]].chain_id
= *chain_id
;
1109 /* Reset the Queue pointers */
1110 OMAP_DMA_CHAIN_QINIT(*chain_id
);
1112 /* Set up the chain */
1113 if (no_of_chans
== 1)
1114 create_dma_lch_chain(channels
[0], channels
[0]);
1116 for (i
= 0; i
< (no_of_chans
- 1); i
++)
1117 create_dma_lch_chain(channels
[i
], channels
[i
+ 1]);
1121 EXPORT_SYMBOL(omap_request_dma_chain
);
1124 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1125 * params after setting it. Dont do this while dma is running!!
1127 * @param chain_id - Chained logical channel id.
1130 * @return - Success : 0
1133 int omap_modify_dma_chain_params(int chain_id
,
1134 struct omap_dma_channel_params params
)
1139 /* Check for input params */
1140 if (unlikely((chain_id
< 0
1141 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1142 printk(KERN_ERR
"Invalid chain id\n");
1146 /* Check if the chain exists */
1147 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1148 printk(KERN_ERR
"Chain doesn't exists\n");
1151 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1153 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1155 * Allowing client drivers to set common parameters now,
1156 * so that later only relevant (src_start, dest_start
1157 * and element count) can be set
1159 omap_set_dma_params(channels
[i
], ¶ms
);
1163 EXPORT_SYMBOL(omap_modify_dma_chain_params
);
1166 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1170 * @return - Success : 0
1173 int omap_free_dma_chain(int chain_id
)
1178 /* Check for input params */
1179 if (unlikely((chain_id
< 0 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1180 printk(KERN_ERR
"Invalid chain id\n");
1184 /* Check if the chain exists */
1185 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1186 printk(KERN_ERR
"Chain doesn't exists\n");
1190 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1191 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1192 dma_chan
[channels
[i
]].next_linked_ch
= -1;
1193 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1194 dma_chan
[channels
[i
]].chain_id
= -1;
1195 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1196 omap_free_dma(channels
[i
]);
1201 dma_linked_lch
[chain_id
].linked_dmach_q
= NULL
;
1202 dma_linked_lch
[chain_id
].chain_mode
= -1;
1203 dma_linked_lch
[chain_id
].chain_state
= -1;
1206 EXPORT_SYMBOL(omap_free_dma_chain
);
1209 * @brief omap_dma_chain_status - Check if the chain is in
1210 * active / inactive state.
1213 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1216 int omap_dma_chain_status(int chain_id
)
1218 /* Check for input params */
1219 if (unlikely((chain_id
< 0 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1220 printk(KERN_ERR
"Invalid chain id\n");
1224 /* Check if the chain exists */
1225 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1226 printk(KERN_ERR
"Chain doesn't exists\n");
1229 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id
,
1230 dma_linked_lch
[chain_id
].q_count
);
1232 if (OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1233 return OMAP_DMA_CHAIN_INACTIVE
;
1234 return OMAP_DMA_CHAIN_ACTIVE
;
1236 EXPORT_SYMBOL(omap_dma_chain_status
);
1239 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1240 * set the params and start the transfer.
1243 * @param src_start - buffer start address
1244 * @param dest_start - Dest address
1246 * @param frame_count
1247 * @param callbk_data - channel callback parameter data.
1249 * @return - Success : 0
1250 * Failure: -EINVAL/-EBUSY
1252 int omap_dma_chain_a_transfer(int chain_id
, int src_start
, int dest_start
,
1253 int elem_count
, int frame_count
, void *callbk_data
)
1259 /* if buffer size is less than 1 then there is
1260 * no use of starting the chain */
1261 if (elem_count
< 1) {
1262 printk(KERN_ERR
"Invalid buffer size\n");
1266 /* Check for input params */
1267 if (unlikely((chain_id
< 0
1268 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1269 printk(KERN_ERR
"Invalid chain id\n");
1273 /* Check if the chain exists */
1274 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1275 printk(KERN_ERR
"Chain doesn't exist\n");
1279 /* Check if all the channels in chain are in use */
1280 if (OMAP_DMA_CHAIN_QFULL(chain_id
))
1283 /* Frame count may be negative in case of indexed transfers */
1284 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1286 /* Get a free channel */
1287 lch
= channels
[dma_linked_lch
[chain_id
].q_tail
];
1289 /* Store the callback data */
1290 dma_chan
[lch
].data
= callbk_data
;
1292 /* Increment the q_tail */
1293 OMAP_DMA_CHAIN_INCQTAIL(chain_id
);
1295 /* Set the params to the free channel */
1297 OMAP2_DMA_CSSA_REG(lch
) = src_start
;
1298 if (dest_start
!= 0)
1299 OMAP2_DMA_CDSA_REG(lch
) = dest_start
;
1301 /* Write the buffer size */
1302 OMAP_DMA_CEN_REG(lch
) = elem_count
;
1303 OMAP_DMA_CFN_REG(lch
) = frame_count
;
1305 /* If the chain is dynamically linked,
1306 * then we may have to start the chain if its not active */
1307 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_DYNAMIC_CHAIN
) {
1309 /* In Dynamic chain, if the chain is not started,
1310 * queue the channel */
1311 if (dma_linked_lch
[chain_id
].chain_state
==
1312 DMA_CHAIN_NOTSTARTED
) {
1313 /* Enable the link in previous channel */
1314 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1316 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1317 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1320 /* Chain is already started, make sure its active,
1321 * if not then start the chain */
1325 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1327 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1328 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1330 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
1331 (dma_chan
[lch
].prev_linked_ch
)))) {
1332 disable_lnk(dma_chan
[lch
].
1334 pr_debug("\n prev ch is stopped\n");
1339 else if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
1341 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1342 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1345 omap_enable_channel_irq(lch
);
1347 w
= OMAP_DMA_CCR_REG(lch
);
1349 if ((0 == (w
& (1 << 24))))
1353 if (start_dma
== 1) {
1354 if (0 == (w
& (1 << 7))) {
1356 dma_chan
[lch
].state
= DMA_CH_STARTED
;
1357 pr_debug("starting %d\n", lch
);
1358 OMAP_DMA_CCR_REG(lch
) = w
;
1362 if (0 == (w
& (1 << 7)))
1363 OMAP_DMA_CCR_REG(lch
) = w
;
1365 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
1370 EXPORT_SYMBOL(omap_dma_chain_a_transfer
);
1373 * @brief omap_start_dma_chain_transfers - Start the chain
1377 * @return - Success : 0
1378 * Failure : -EINVAL/-EBUSY
1380 int omap_start_dma_chain_transfers(int chain_id
)
1385 if (unlikely((chain_id
< 0 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1386 printk(KERN_ERR
"Invalid chain id\n");
1390 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1392 if (dma_linked_lch
[channels
[0]].chain_state
== DMA_CHAIN_STARTED
) {
1393 printk(KERN_ERR
"Chain is already started\n");
1397 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_STATIC_CHAIN
) {
1398 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
;
1400 enable_lnk(channels
[i
]);
1401 omap_enable_channel_irq(channels
[i
]);
1404 omap_enable_channel_irq(channels
[0]);
1407 w
= OMAP_DMA_CCR_REG(channels
[0]);
1409 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_STARTED
;
1410 dma_chan
[channels
[0]].state
= DMA_CH_STARTED
;
1412 if ((0 == (w
& (1 << 24))))
1416 OMAP_DMA_CCR_REG(channels
[0]) = w
;
1418 dma_chan
[channels
[0]].flags
|= OMAP_DMA_ACTIVE
;
1421 EXPORT_SYMBOL(omap_start_dma_chain_transfers
);
1424 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1428 * @return - Success : 0
1431 int omap_stop_dma_chain_transfers(int chain_id
)
1437 /* Check for input params */
1438 if (unlikely((chain_id
< 0 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1439 printk(KERN_ERR
"Invalid chain id\n");
1443 /* Check if the chain exists */
1444 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1445 printk(KERN_ERR
"Chain doesn't exists\n");
1448 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1451 * Special programming model needed to disable DMA before end of block
1453 sys_cf
= omap_readl(OMAP_DMA4_OCP_SYSCONFIG
);
1455 /* Middle mode reg set no Standby */
1456 w
&= ~((1 << 12)|(1 << 13));
1457 omap_writel(w
, OMAP_DMA4_OCP_SYSCONFIG
);
1459 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1461 /* Stop the Channel transmission */
1462 w
= OMAP_DMA_CCR_REG(channels
[i
]);
1464 OMAP_DMA_CCR_REG(channels
[i
]) = w
;
1466 /* Disable the link in all the channels */
1467 disable_lnk(channels
[i
]);
1468 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1471 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1473 /* Reset the Queue pointers */
1474 OMAP_DMA_CHAIN_QINIT(chain_id
);
1476 /* Errata - put in the old value */
1477 omap_writel(sys_cf
, OMAP_DMA4_OCP_SYSCONFIG
);
1480 EXPORT_SYMBOL(omap_stop_dma_chain_transfers
);
1482 /* Get the index of the ongoing DMA in chain */
1484 * @brief omap_get_dma_chain_index - Get the element and frame index
1485 * of the ongoing DMA in chain
1488 * @param ei - Element index
1489 * @param fi - Frame index
1491 * @return - Success : 0
1494 int omap_get_dma_chain_index(int chain_id
, int *ei
, int *fi
)
1499 /* Check for input params */
1500 if (unlikely((chain_id
< 0 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1501 printk(KERN_ERR
"Invalid chain id\n");
1505 /* Check if the chain exists */
1506 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1507 printk(KERN_ERR
"Chain doesn't exists\n");
1513 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1515 /* Get the current channel */
1516 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1518 *ei
= OMAP2_DMA_CCEN_REG(lch
);
1519 *fi
= OMAP2_DMA_CCFN_REG(lch
);
1523 EXPORT_SYMBOL(omap_get_dma_chain_index
);
1526 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1527 * ongoing DMA in chain
1531 * @return - Success : Destination position
1534 int omap_get_dma_chain_dst_pos(int chain_id
)
1539 /* Check for input params */
1540 if (unlikely((chain_id
< 0 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1541 printk(KERN_ERR
"Invalid chain id\n");
1545 /* Check if the chain exists */
1546 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1547 printk(KERN_ERR
"Chain doesn't exists\n");
1551 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1553 /* Get the current channel */
1554 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1556 return (OMAP_DMA_CDAC_REG(lch
));
1558 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos
);
1561 * @brief omap_get_dma_chain_src_pos - Get the source position
1562 * of the ongoing DMA in chain
1565 * @return - Success : Destination position
1568 int omap_get_dma_chain_src_pos(int chain_id
)
1573 /* Check for input params */
1574 if (unlikely((chain_id
< 0 || chain_id
>= OMAP_LOGICAL_DMA_CH_COUNT
))) {
1575 printk(KERN_ERR
"Invalid chain id\n");
1579 /* Check if the chain exists */
1580 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1581 printk(KERN_ERR
"Chain doesn't exists\n");
1585 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1587 /* Get the current channel */
1588 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1590 return (OMAP_DMA_CSAC_REG(lch
));
1592 EXPORT_SYMBOL(omap_get_dma_chain_src_pos
);
1595 /*----------------------------------------------------------------------------*/
1597 #ifdef CONFIG_ARCH_OMAP1
1599 static int omap1_dma_handle_ch(int ch
)
1603 if (enable_1510_mode
&& ch
>= 6) {
1604 csr
= dma_chan
[ch
].saved_csr
;
1605 dma_chan
[ch
].saved_csr
= 0;
1607 csr
= OMAP_DMA_CSR_REG(ch
);
1608 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
1609 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
1612 if ((csr
& 0x3f) == 0)
1614 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1615 printk(KERN_WARNING
"Spurious interrupt from DMA channel "
1616 "%d (CSR %04x)\n", ch
, csr
);
1619 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
1620 printk(KERN_WARNING
"DMA timeout with device %d\n",
1621 dma_chan
[ch
].dev_id
);
1622 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
1623 printk(KERN_WARNING
"DMA synchronization event drop occurred "
1624 "with device %d\n", dma_chan
[ch
].dev_id
);
1625 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
1626 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1627 if (likely(dma_chan
[ch
].callback
!= NULL
))
1628 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
1632 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
)
1634 int ch
= ((int) dev_id
) - 1;
1638 int handled_now
= 0;
1640 handled_now
+= omap1_dma_handle_ch(ch
);
1641 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
1642 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
1645 handled
+= handled_now
;
1648 return handled
? IRQ_HANDLED
: IRQ_NONE
;
1652 #define omap1_dma_irq_handler NULL
1655 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1657 static int omap2_dma_handle_ch(int ch
)
1659 u32 status
= OMAP_DMA_CSR_REG(ch
);
1662 if (printk_ratelimit())
1663 printk(KERN_WARNING
"Spurious DMA IRQ for lch %d\n", ch
);
1664 omap_writel(1 << ch
, OMAP_DMA4_IRQSTATUS_L0
);
1667 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1668 if (printk_ratelimit())
1669 printk(KERN_WARNING
"IRQ %04x for non-allocated DMA"
1670 "channel %d\n", status
, ch
);
1673 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
1675 "DMA synchronization event drop occurred with device "
1676 "%d\n", dma_chan
[ch
].dev_id
);
1677 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
))
1678 printk(KERN_INFO
"DMA transaction error with device %d\n",
1679 dma_chan
[ch
].dev_id
);
1680 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
1681 printk(KERN_INFO
"DMA secure error with device %d\n",
1682 dma_chan
[ch
].dev_id
);
1683 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
1684 printk(KERN_INFO
"DMA misaligned error with device %d\n",
1685 dma_chan
[ch
].dev_id
);
1687 OMAP_DMA_CSR_REG(ch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
1688 omap_writel(1 << ch
, OMAP_DMA4_IRQSTATUS_L0
);
1690 /* If the ch is not chained then chain_id will be -1 */
1691 if (dma_chan
[ch
].chain_id
!= -1) {
1692 int chain_id
= dma_chan
[ch
].chain_id
;
1693 dma_chan
[ch
].state
= DMA_CH_NOTSTARTED
;
1694 if (OMAP_DMA_CLNK_CTRL_REG(ch
) & (1 << 15))
1695 dma_chan
[dma_chan
[ch
].next_linked_ch
].state
=
1697 if (dma_linked_lch
[chain_id
].chain_mode
==
1698 OMAP_DMA_DYNAMIC_CHAIN
)
1701 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1702 OMAP_DMA_CHAIN_INCQHEAD(chain_id
);
1704 status
= OMAP_DMA_CSR_REG(ch
);
1707 if (likely(dma_chan
[ch
].callback
!= NULL
))
1708 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
1710 OMAP_DMA_CSR_REG(ch
) = status
;
1715 /* STATUS register count is from 1-32 while our is 0-31 */
1716 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
)
1721 val
= omap_readl(OMAP_DMA4_IRQSTATUS_L0
);
1723 if (printk_ratelimit())
1724 printk(KERN_WARNING
"Spurious DMA IRQ\n");
1727 for (i
= 0; i
< OMAP_LOGICAL_DMA_CH_COUNT
&& val
!= 0; i
++) {
1729 omap2_dma_handle_ch(i
);
1736 static struct irqaction omap24xx_dma_irq
= {
1738 .handler
= omap2_dma_irq_handler
,
1739 .flags
= IRQF_DISABLED
1743 static struct irqaction omap24xx_dma_irq
;
1746 /*----------------------------------------------------------------------------*/
1748 static struct lcd_dma_info
{
1751 void (* callback
)(u16 status
, void *data
);
1755 unsigned long addr
, size
;
1756 int rotate
, data_type
, xres
, yres
;
1762 int single_transfer
;
1765 void omap_set_lcd_dma_b1(unsigned long addr
, u16 fb_xres
, u16 fb_yres
,
1768 lcd_dma
.addr
= addr
;
1769 lcd_dma
.data_type
= data_type
;
1770 lcd_dma
.xres
= fb_xres
;
1771 lcd_dma
.yres
= fb_yres
;
1774 void omap_set_lcd_dma_src_port(int port
)
1776 lcd_dma
.src_port
= port
;
1779 void omap_set_lcd_dma_ext_controller(int external
)
1781 lcd_dma
.ext_ctrl
= external
;
1784 void omap_set_lcd_dma_single_transfer(int single
)
1786 lcd_dma
.single_transfer
= single
;
1790 void omap_set_lcd_dma_b1_rotation(int rotate
)
1792 if (omap_dma_in_1510_mode()) {
1793 printk(KERN_ERR
"DMA rotation is not supported in 1510 mode\n");
1797 lcd_dma
.rotate
= rotate
;
1800 void omap_set_lcd_dma_b1_mirror(int mirror
)
1802 if (omap_dma_in_1510_mode()) {
1803 printk(KERN_ERR
"DMA mirror is not supported in 1510 mode\n");
1806 lcd_dma
.mirror
= mirror
;
1809 void omap_set_lcd_dma_b1_vxres(unsigned long vxres
)
1811 if (omap_dma_in_1510_mode()) {
1812 printk(KERN_ERR
"DMA virtual resulotion is not supported "
1816 lcd_dma
.vxres
= vxres
;
1819 void omap_set_lcd_dma_b1_scale(unsigned int xscale
, unsigned int yscale
)
1821 if (omap_dma_in_1510_mode()) {
1822 printk(KERN_ERR
"DMA scale is not supported in 1510 mode\n");
1825 lcd_dma
.xscale
= xscale
;
1826 lcd_dma
.yscale
= yscale
;
1829 static void set_b1_regs(void)
1831 unsigned long top
, bottom
;
1834 unsigned long en
, fn
;
1836 unsigned long vxres
;
1837 unsigned int xscale
, yscale
;
1839 switch (lcd_dma
.data_type
) {
1840 case OMAP_DMA_DATA_TYPE_S8
:
1843 case OMAP_DMA_DATA_TYPE_S16
:
1846 case OMAP_DMA_DATA_TYPE_S32
:
1854 vxres
= lcd_dma
.vxres
? lcd_dma
.vxres
: lcd_dma
.xres
;
1855 xscale
= lcd_dma
.xscale
? lcd_dma
.xscale
: 1;
1856 yscale
= lcd_dma
.yscale
? lcd_dma
.yscale
: 1;
1857 BUG_ON(vxres
< lcd_dma
.xres
);
1858 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1859 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1860 switch (lcd_dma
.rotate
) {
1862 if (!lcd_dma
.mirror
) {
1863 top
= PIXADDR(0, 0);
1864 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1865 /* 1510 DMA requires the bottom address to be 2 more
1866 * than the actual last memory access location. */
1867 if (omap_dma_in_1510_mode() &&
1868 lcd_dma
.data_type
== OMAP_DMA_DATA_TYPE_S32
)
1870 ei
= PIXSTEP(0, 0, 1, 0);
1871 fi
= PIXSTEP(lcd_dma
.xres
- 1, 0, 0, 1);
1873 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
1874 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
1875 ei
= PIXSTEP(1, 0, 0, 0);
1876 fi
= PIXSTEP(0, 0, lcd_dma
.xres
- 1, 1);
1882 if (!lcd_dma
.mirror
) {
1883 top
= PIXADDR(0, lcd_dma
.yres
- 1);
1884 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
1885 ei
= PIXSTEP(0, 1, 0, 0);
1886 fi
= PIXSTEP(0, 0, 1, lcd_dma
.yres
- 1);
1888 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1889 bottom
= PIXADDR(0, 0);
1890 ei
= PIXSTEP(0, 1, 0, 0);
1891 fi
= PIXSTEP(1, 0, 0, lcd_dma
.yres
- 1);
1897 if (!lcd_dma
.mirror
) {
1898 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1899 bottom
= PIXADDR(0, 0);
1900 ei
= PIXSTEP(1, 0, 0, 0);
1901 fi
= PIXSTEP(0, 1, lcd_dma
.xres
- 1, 0);
1903 top
= PIXADDR(0, lcd_dma
.yres
- 1);
1904 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
1905 ei
= PIXSTEP(0, 0, 1, 0);
1906 fi
= PIXSTEP(lcd_dma
.xres
- 1, 1, 0, 0);
1912 if (!lcd_dma
.mirror
) {
1913 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
1914 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
1915 ei
= PIXSTEP(0, 0, 0, 1);
1916 fi
= PIXSTEP(1, lcd_dma
.yres
- 1, 0, 0);
1918 top
= PIXADDR(0, 0);
1919 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1920 ei
= PIXSTEP(0, 0, 0, 1);
1921 fi
= PIXSTEP(0, lcd_dma
.yres
- 1, 1, 0);
1928 return; /* Suppress warning about uninitialized vars */
1931 if (omap_dma_in_1510_mode()) {
1932 omap_writew(top
>> 16, OMAP1510_DMA_LCD_TOP_F1_U
);
1933 omap_writew(top
, OMAP1510_DMA_LCD_TOP_F1_L
);
1934 omap_writew(bottom
>> 16, OMAP1510_DMA_LCD_BOT_F1_U
);
1935 omap_writew(bottom
, OMAP1510_DMA_LCD_BOT_F1_L
);
1941 omap_writew(top
>> 16, OMAP1610_DMA_LCD_TOP_B1_U
);
1942 omap_writew(top
, OMAP1610_DMA_LCD_TOP_B1_L
);
1943 omap_writew(bottom
>> 16, OMAP1610_DMA_LCD_BOT_B1_U
);
1944 omap_writew(bottom
, OMAP1610_DMA_LCD_BOT_B1_L
);
1946 omap_writew(en
, OMAP1610_DMA_LCD_SRC_EN_B1
);
1947 omap_writew(fn
, OMAP1610_DMA_LCD_SRC_FN_B1
);
1949 w
= omap_readw(OMAP1610_DMA_LCD_CSDP
);
1951 w
|= lcd_dma
.data_type
;
1952 omap_writew(w
, OMAP1610_DMA_LCD_CSDP
);
1954 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1955 /* Always set the source port as SDRAM for now*/
1957 if (lcd_dma
.callback
!= NULL
)
1958 w
|= 1 << 1; /* Block interrupt enable */
1961 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1963 if (!(lcd_dma
.rotate
|| lcd_dma
.mirror
||
1964 lcd_dma
.vxres
|| lcd_dma
.xscale
|| lcd_dma
.yscale
))
1967 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1968 /* Set the double-indexed addressing mode */
1970 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1972 omap_writew(ei
, OMAP1610_DMA_LCD_SRC_EI_B1
);
1973 omap_writew(fi
>> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U
);
1974 omap_writew(fi
, OMAP1610_DMA_LCD_SRC_FI_B1_L
);
1977 static irqreturn_t
lcd_dma_irq_handler(int irq
, void *dev_id
)
1981 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1982 if (unlikely(!(w
& (1 << 3)))) {
1983 printk(KERN_WARNING
"Spurious LCD DMA IRQ\n");
1988 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1990 if (lcd_dma
.callback
!= NULL
)
1991 lcd_dma
.callback(w
, lcd_dma
.cb_data
);
1996 int omap_request_lcd_dma(void (* callback
)(u16 status
, void *data
),
1999 spin_lock_irq(&lcd_dma
.lock
);
2000 if (lcd_dma
.reserved
) {
2001 spin_unlock_irq(&lcd_dma
.lock
);
2002 printk(KERN_ERR
"LCD DMA channel already reserved\n");
2006 lcd_dma
.reserved
= 1;
2007 spin_unlock_irq(&lcd_dma
.lock
);
2008 lcd_dma
.callback
= callback
;
2009 lcd_dma
.cb_data
= data
;
2011 lcd_dma
.single_transfer
= 0;
2017 lcd_dma
.ext_ctrl
= 0;
2018 lcd_dma
.src_port
= 0;
2023 void omap_free_lcd_dma(void)
2025 spin_lock(&lcd_dma
.lock
);
2026 if (!lcd_dma
.reserved
) {
2027 spin_unlock(&lcd_dma
.lock
);
2028 printk(KERN_ERR
"LCD DMA is not reserved\n");
2032 if (!enable_1510_mode
)
2033 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR
) & ~1,
2034 OMAP1610_DMA_LCD_CCR
);
2035 lcd_dma
.reserved
= 0;
2036 spin_unlock(&lcd_dma
.lock
);
2039 void omap_enable_lcd_dma(void)
2043 /* Set the Enable bit only if an external controller is
2044 * connected. Otherwise the OMAP internal controller will
2045 * start the transfer when it gets enabled.
2047 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
2050 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2052 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2056 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2058 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2061 void omap_setup_lcd_dma(void)
2063 BUG_ON(lcd_dma
.active
);
2064 if (!enable_1510_mode
) {
2065 /* Set some reasonable defaults */
2066 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR
);
2067 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP
);
2068 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL
);
2071 if (!enable_1510_mode
) {
2074 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2075 /* If DMA was already active set the end_prog bit to have
2076 * the programmed register set loaded into the active
2079 w
|= 1 << 11; /* End_prog */
2080 if (!lcd_dma
.single_transfer
)
2081 w
|= (3 << 8); /* Auto_init, repeat */
2082 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2086 void omap_stop_lcd_dma(void)
2091 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
2094 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2096 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2098 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2100 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2103 /*----------------------------------------------------------------------------*/
2105 static int __init
omap_init_dma(void)
2109 if (cpu_is_omap15xx()) {
2110 printk(KERN_INFO
"DMA support for OMAP15xx initialized\n");
2112 enable_1510_mode
= 1;
2113 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2114 printk(KERN_INFO
"OMAP DMA hardware version %d\n",
2115 omap_readw(OMAP_DMA_HW_ID
));
2116 printk(KERN_INFO
"DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2117 (omap_readw(OMAP_DMA_CAPS_0_U
) << 16) |
2118 omap_readw(OMAP_DMA_CAPS_0_L
),
2119 (omap_readw(OMAP_DMA_CAPS_1_U
) << 16) |
2120 omap_readw(OMAP_DMA_CAPS_1_L
),
2121 omap_readw(OMAP_DMA_CAPS_2
), omap_readw(OMAP_DMA_CAPS_3
),
2122 omap_readw(OMAP_DMA_CAPS_4
));
2123 if (!enable_1510_mode
) {
2126 /* Disable OMAP 3.0/3.1 compatibility mode. */
2127 w
= omap_readw(OMAP_DMA_GSCR
);
2129 omap_writew(w
, OMAP_DMA_GSCR
);
2130 dma_chan_count
= 16;
2133 if (cpu_is_omap16xx()) {
2136 /* this would prevent OMAP sleep */
2137 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2139 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2141 } else if (cpu_class_is_omap2()) {
2142 u8 revision
= omap_readb(OMAP_DMA4_REVISION
);
2143 printk(KERN_INFO
"OMAP DMA hardware revision %d.%d\n",
2144 revision
>> 4, revision
& 0xf);
2145 dma_chan_count
= OMAP_LOGICAL_DMA_CH_COUNT
;
2151 memset(&lcd_dma
, 0, sizeof(lcd_dma
));
2152 spin_lock_init(&lcd_dma
.lock
);
2153 spin_lock_init(&dma_chan_lock
);
2154 memset(&dma_chan
, 0, sizeof(dma_chan
));
2156 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
2158 dma_chan
[ch
].dev_id
= -1;
2159 dma_chan
[ch
].next_lch
= -1;
2161 if (ch
>= 6 && enable_1510_mode
)
2164 if (cpu_class_is_omap1()) {
2165 /* request_irq() doesn't like dev_id (ie. ch) being
2166 * zero, so we have to kludge around this. */
2167 r
= request_irq(omap1_dma_irq
[ch
],
2168 omap1_dma_irq_handler
, 0, "DMA",
2173 printk(KERN_ERR
"unable to request IRQ %d "
2174 "for DMA (error %d)\n",
2175 omap1_dma_irq
[ch
], r
);
2176 for (i
= 0; i
< ch
; i
++)
2177 free_irq(omap1_dma_irq
[i
],
2184 if (cpu_is_omap2430() || cpu_is_omap34xx())
2185 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE
,
2186 DMA_DEFAULT_FIFO_DEPTH
, 0);
2188 if (cpu_class_is_omap2())
2189 setup_irq(INT_24XX_SDMA_IRQ0
, &omap24xx_dma_irq
);
2191 /* FIXME: Update LCD DMA to work on 24xx */
2192 if (cpu_class_is_omap1()) {
2193 r
= request_irq(INT_DMA_LCD
, lcd_dma_irq_handler
, 0,
2198 printk(KERN_ERR
"unable to request IRQ for LCD DMA "
2200 for (i
= 0; i
< dma_chan_count
; i
++)
2201 free_irq(omap1_dma_irq
[i
], (void *) (i
+ 1));
2209 arch_initcall(omap_init_dma
);
2211 EXPORT_SYMBOL(omap_get_dma_src_pos
);
2212 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
2213 EXPORT_SYMBOL(omap_get_dma_src_addr_counter
);
2214 EXPORT_SYMBOL(omap_clear_dma
);
2215 EXPORT_SYMBOL(omap_set_dma_priority
);
2216 EXPORT_SYMBOL(omap_request_dma
);
2217 EXPORT_SYMBOL(omap_free_dma
);
2218 EXPORT_SYMBOL(omap_start_dma
);
2219 EXPORT_SYMBOL(omap_stop_dma
);
2220 EXPORT_SYMBOL(omap_set_dma_callback
);
2221 EXPORT_SYMBOL(omap_enable_dma_irq
);
2222 EXPORT_SYMBOL(omap_disable_dma_irq
);
2224 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
2225 EXPORT_SYMBOL(omap_set_dma_color_mode
);
2226 EXPORT_SYMBOL(omap_set_dma_write_mode
);
2228 EXPORT_SYMBOL(omap_set_dma_src_params
);
2229 EXPORT_SYMBOL(omap_set_dma_src_index
);
2230 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
2231 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
2233 EXPORT_SYMBOL(omap_set_dma_dest_params
);
2234 EXPORT_SYMBOL(omap_set_dma_dest_index
);
2235 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
2236 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
2238 EXPORT_SYMBOL(omap_set_dma_params
);
2240 EXPORT_SYMBOL(omap_dma_link_lch
);
2241 EXPORT_SYMBOL(omap_dma_unlink_lch
);
2243 EXPORT_SYMBOL(omap_request_lcd_dma
);
2244 EXPORT_SYMBOL(omap_free_lcd_dma
);
2245 EXPORT_SYMBOL(omap_enable_lcd_dma
);
2246 EXPORT_SYMBOL(omap_setup_lcd_dma
);
2247 EXPORT_SYMBOL(omap_stop_lcd_dma
);
2248 EXPORT_SYMBOL(omap_set_lcd_dma_b1
);
2249 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer
);
2250 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller
);
2251 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation
);
2252 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres
);
2253 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale
);
2254 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror
);