2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
30 #include <asm/system.h>
31 #include <asm/hardware.h>
34 #include <asm/arch/tc.h>
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE
, DMA_CH_PARAMS_SET_DONE
, DMA_CH_STARTED
,
40 DMA_CH_QUEUED
, DMA_CH_NOTSTARTED
, DMA_CH_PAUSED
, DMA_CH_LINK_ENABLED
43 enum { DMA_CHAIN_STARTED
, DMA_CHAIN_NOTSTARTED
};
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
52 static int enable_1510_mode
;
60 void (*callback
)(int lch
, u16 ch_status
, void *data
);
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
75 struct dma_link_info
{
77 int no_of_lchs_linked
;
88 static struct dma_link_info
*dma_linked_lch
;
90 #ifndef CONFIG_ARCH_OMAP1
92 /* Chain handling macros */
93 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
99 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109 #define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
124 static int dma_lch_count
;
125 static int dma_chan_count
;
127 static spinlock_t dma_chan_lock
;
128 static struct omap_dma_lch
*dma_chan
;
129 static void __iomem
*omap_dma_base
;
131 static const u8 omap1_dma_irq
[OMAP1_LOGICAL_DMA_CH_COUNT
] = {
132 INT_DMA_CH0_6
, INT_DMA_CH1_7
, INT_DMA_CH2_8
, INT_DMA_CH3
,
133 INT_DMA_CH4
, INT_DMA_CH5
, INT_1610_DMA_CH6
, INT_1610_DMA_CH7
,
134 INT_1610_DMA_CH8
, INT_1610_DMA_CH9
, INT_1610_DMA_CH10
,
135 INT_1610_DMA_CH11
, INT_1610_DMA_CH12
, INT_1610_DMA_CH13
,
136 INT_1610_DMA_CH14
, INT_1610_DMA_CH15
, INT_DMA_LCD
139 static inline void disable_lnk(int lch
);
140 static void omap_disable_channel_irq(int lch
);
141 static inline void omap_enable_channel_irq(int lch
);
143 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
146 #define dma_read(reg) \
149 if (cpu_class_is_omap1()) \
150 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
152 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
156 #define dma_write(val, reg) \
158 if (cpu_class_is_omap1()) \
159 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
161 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
164 #ifdef CONFIG_ARCH_OMAP15XX
165 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
166 int omap_dma_in_1510_mode(void)
168 return enable_1510_mode
;
171 #define omap_dma_in_1510_mode() 0
174 #ifdef CONFIG_ARCH_OMAP1
175 static inline int get_gdma_dev(int req
)
177 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
178 int shift
= ((req
- 1) % 5) * 6;
180 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
183 static inline void set_gdma_dev(int req
, int dev
)
185 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
186 int shift
= ((req
- 1) % 5) * 6;
190 l
&= ~(0x3f << shift
);
191 l
|= (dev
- 1) << shift
;
195 #define set_gdma_dev(req, dev) do {} while (0)
199 static void clear_lch_regs(int lch
)
202 void __iomem
*lch_base
= omap_dma_base
+ OMAP1_DMA_CH_BASE(lch
);
204 for (i
= 0; i
< 0x2c; i
+= 2)
205 __raw_writew(0, lch_base
+ i
);
208 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
213 if (cpu_class_is_omap1()) {
215 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
216 reg
= OMAP_TC_OCPT1_PRIOR
;
218 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
219 reg
= OMAP_TC_OCPT2_PRIOR
;
221 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
222 reg
= OMAP_TC_EMIFF_PRIOR
;
224 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
225 reg
= OMAP_TC_EMIFS_PRIOR
;
233 l
|= (priority
& 0xf) << 8;
237 if (cpu_class_is_omap2()) {
240 ccr
= dma_read(CCR(lch
));
245 dma_write(ccr
, CCR(lch
));
248 EXPORT_SYMBOL(omap_set_dma_priority
);
250 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
251 int frame_count
, int sync_mode
,
252 int dma_trigger
, int src_or_dst_synch
)
256 l
= dma_read(CSDP(lch
));
259 dma_write(l
, CSDP(lch
));
261 if (cpu_class_is_omap1()) {
264 ccr
= dma_read(CCR(lch
));
266 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
268 dma_write(ccr
, CCR(lch
));
270 ccr
= dma_read(CCR2(lch
));
272 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
274 dma_write(ccr
, CCR2(lch
));
277 if (cpu_class_is_omap2() && dma_trigger
) {
280 val
= dma_read(CCR(lch
));
282 if (dma_trigger
> 63)
284 if (dma_trigger
> 31)
288 val
|= (dma_trigger
& 0x1f);
290 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
295 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
300 if (src_or_dst_synch
)
301 val
|= 1 << 24; /* source synch */
303 val
&= ~(1 << 24); /* dest synch */
305 dma_write(val
, CCR(lch
));
308 dma_write(elem_count
, CEN(lch
));
309 dma_write(frame_count
, CFN(lch
));
311 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
313 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
317 BUG_ON(omap_dma_in_1510_mode());
319 if (cpu_class_is_omap2()) {
324 w
= dma_read(CCR2(lch
));
328 case OMAP_DMA_CONSTANT_FILL
:
331 case OMAP_DMA_TRANSPARENT_COPY
:
334 case OMAP_DMA_COLOR_DIS
:
339 dma_write(w
, CCR2(lch
));
341 w
= dma_read(LCH_CTRL(lch
));
343 /* Default is channel type 2D */
345 dma_write((u16
)color
, COLOR_L(lch
));
346 dma_write((u16
)(color
>> 16), COLOR_U(lch
));
347 w
|= 1; /* Channel type G */
349 dma_write(w
, LCH_CTRL(lch
));
351 EXPORT_SYMBOL(omap_set_dma_color_mode
);
353 void omap_set_dma_write_mode(int lch
, enum omap_dma_write_mode mode
)
355 if (cpu_class_is_omap2()) {
358 csdp
= dma_read(CSDP(lch
));
359 csdp
&= ~(0x3 << 16);
360 csdp
|= (mode
<< 16);
361 dma_write(csdp
, CSDP(lch
));
364 EXPORT_SYMBOL(omap_set_dma_write_mode
);
366 void omap_set_dma_channel_mode(int lch
, enum omap_dma_channel_mode mode
)
368 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
371 l
= dma_read(LCH_CTRL(lch
));
374 dma_write(l
, LCH_CTRL(lch
));
377 EXPORT_SYMBOL(omap_set_dma_channel_mode
);
379 /* Note that src_port is only for omap1 */
380 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
381 unsigned long src_start
,
382 int src_ei
, int src_fi
)
386 if (cpu_class_is_omap1()) {
389 w
= dma_read(CSDP(lch
));
392 dma_write(w
, CSDP(lch
));
395 l
= dma_read(CCR(lch
));
397 l
|= src_amode
<< 12;
398 dma_write(l
, CCR(lch
));
400 if (cpu_class_is_omap1()) {
401 dma_write(src_start
>> 16, CSSA_U(lch
));
402 dma_write((u16
)src_start
, CSSA_L(lch
));
405 if (cpu_class_is_omap2())
406 dma_write(src_start
, CSSA(lch
));
408 dma_write(src_ei
, CSEI(lch
));
409 dma_write(src_fi
, CSFI(lch
));
411 EXPORT_SYMBOL(omap_set_dma_src_params
);
413 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
*params
)
415 omap_set_dma_transfer_params(lch
, params
->data_type
,
416 params
->elem_count
, params
->frame_count
,
417 params
->sync_mode
, params
->trigger
,
418 params
->src_or_dst_synch
);
419 omap_set_dma_src_params(lch
, params
->src_port
,
420 params
->src_amode
, params
->src_start
,
421 params
->src_ei
, params
->src_fi
);
423 omap_set_dma_dest_params(lch
, params
->dst_port
,
424 params
->dst_amode
, params
->dst_start
,
425 params
->dst_ei
, params
->dst_fi
);
426 if (params
->read_prio
|| params
->write_prio
)
427 omap_dma_set_prio_lch(lch
, params
->read_prio
,
430 EXPORT_SYMBOL(omap_set_dma_params
);
432 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
434 if (cpu_class_is_omap2())
437 dma_write(eidx
, CSEI(lch
));
438 dma_write(fidx
, CSFI(lch
));
440 EXPORT_SYMBOL(omap_set_dma_src_index
);
442 void omap_set_dma_src_data_pack(int lch
, int enable
)
446 l
= dma_read(CSDP(lch
));
450 dma_write(l
, CSDP(lch
));
452 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
454 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
456 unsigned int burst
= 0;
459 l
= dma_read(CSDP(lch
));
462 switch (burst_mode
) {
463 case OMAP_DMA_DATA_BURST_DIS
:
465 case OMAP_DMA_DATA_BURST_4
:
466 if (cpu_class_is_omap2())
471 case OMAP_DMA_DATA_BURST_8
:
472 if (cpu_class_is_omap2()) {
476 /* not supported by current hardware on OMAP1
480 case OMAP_DMA_DATA_BURST_16
:
481 if (cpu_class_is_omap2()) {
485 /* OMAP1 don't support burst 16
493 dma_write(l
, CSDP(lch
));
495 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
497 /* Note that dest_port is only for OMAP1 */
498 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
499 unsigned long dest_start
,
500 int dst_ei
, int dst_fi
)
504 if (cpu_class_is_omap1()) {
505 l
= dma_read(CSDP(lch
));
508 dma_write(l
, CSDP(lch
));
511 l
= dma_read(CCR(lch
));
513 l
|= dest_amode
<< 14;
514 dma_write(l
, CCR(lch
));
516 if (cpu_class_is_omap1()) {
517 dma_write(dest_start
>> 16, CDSA_U(lch
));
518 dma_write(dest_start
, CDSA_L(lch
));
521 if (cpu_class_is_omap2())
522 dma_write(dest_start
, CDSA(lch
));
524 dma_write(dst_ei
, CDEI(lch
));
525 dma_write(dst_fi
, CDFI(lch
));
527 EXPORT_SYMBOL(omap_set_dma_dest_params
);
529 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
531 if (cpu_class_is_omap2())
534 dma_write(eidx
, CDEI(lch
));
535 dma_write(fidx
, CDFI(lch
));
537 EXPORT_SYMBOL(omap_set_dma_dest_index
);
539 void omap_set_dma_dest_data_pack(int lch
, int enable
)
543 l
= dma_read(CSDP(lch
));
547 dma_write(l
, CSDP(lch
));
549 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
551 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
553 unsigned int burst
= 0;
556 l
= dma_read(CSDP(lch
));
559 switch (burst_mode
) {
560 case OMAP_DMA_DATA_BURST_DIS
:
562 case OMAP_DMA_DATA_BURST_4
:
563 if (cpu_class_is_omap2())
568 case OMAP_DMA_DATA_BURST_8
:
569 if (cpu_class_is_omap2())
574 case OMAP_DMA_DATA_BURST_16
:
575 if (cpu_class_is_omap2()) {
579 /* OMAP1 don't support burst 16
583 printk(KERN_ERR
"Invalid DMA burst mode\n");
588 dma_write(l
, CSDP(lch
));
590 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
592 static inline void omap_enable_channel_irq(int lch
)
597 if (cpu_class_is_omap1())
598 status
= dma_read(CSR(lch
));
599 else if (cpu_class_is_omap2())
600 dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR(lch
));
602 /* Enable some nice interrupts. */
603 dma_write(dma_chan
[lch
].enabled_irqs
, CICR(lch
));
606 static void omap_disable_channel_irq(int lch
)
608 if (cpu_class_is_omap2())
609 dma_write(0, CICR(lch
));
612 void omap_enable_dma_irq(int lch
, u16 bits
)
614 dma_chan
[lch
].enabled_irqs
|= bits
;
616 EXPORT_SYMBOL(omap_enable_dma_irq
);
618 void omap_disable_dma_irq(int lch
, u16 bits
)
620 dma_chan
[lch
].enabled_irqs
&= ~bits
;
622 EXPORT_SYMBOL(omap_disable_dma_irq
);
624 static inline void enable_lnk(int lch
)
628 l
= dma_read(CLNK_CTRL(lch
));
630 if (cpu_class_is_omap1())
633 /* Set the ENABLE_LNK bits */
634 if (dma_chan
[lch
].next_lch
!= -1)
635 l
= dma_chan
[lch
].next_lch
| (1 << 15);
637 #ifndef CONFIG_ARCH_OMAP1
638 if (cpu_class_is_omap2())
639 if (dma_chan
[lch
].next_linked_ch
!= -1)
640 l
= dma_chan
[lch
].next_linked_ch
| (1 << 15);
643 dma_write(l
, CLNK_CTRL(lch
));
646 static inline void disable_lnk(int lch
)
650 l
= dma_read(CLNK_CTRL(lch
));
652 /* Disable interrupts */
653 if (cpu_class_is_omap1()) {
654 dma_write(0, CICR(lch
));
655 /* Set the STOP_LNK bit */
659 if (cpu_class_is_omap2()) {
660 omap_disable_channel_irq(lch
);
661 /* Clear the ENABLE_LNK bit */
665 dma_write(l
, CLNK_CTRL(lch
));
666 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
669 static inline void omap2_enable_irq_lch(int lch
)
673 if (!cpu_class_is_omap2())
676 val
= dma_read(IRQENABLE_L0
);
678 dma_write(val
, IRQENABLE_L0
);
681 int omap_request_dma(int dev_id
, const char *dev_name
,
682 void (*callback
)(int lch
, u16 ch_status
, void *data
),
683 void *data
, int *dma_ch_out
)
685 int ch
, free_ch
= -1;
687 struct omap_dma_lch
*chan
;
689 spin_lock_irqsave(&dma_chan_lock
, flags
);
690 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
691 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
698 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
701 chan
= dma_chan
+ free_ch
;
702 chan
->dev_id
= dev_id
;
704 if (cpu_class_is_omap1())
705 clear_lch_regs(free_ch
);
707 if (cpu_class_is_omap2())
708 omap_clear_dma(free_ch
);
710 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
712 chan
->dev_name
= dev_name
;
713 chan
->callback
= callback
;
716 #ifndef CONFIG_ARCH_OMAP1
717 if (cpu_class_is_omap2()) {
719 chan
->next_linked_ch
= -1;
723 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
725 if (cpu_class_is_omap1())
726 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
727 else if (cpu_class_is_omap2())
728 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
729 OMAP2_DMA_TRANS_ERR_IRQ
;
731 if (cpu_is_omap16xx()) {
732 /* If the sync device is set, configure it dynamically. */
734 set_gdma_dev(free_ch
+ 1, dev_id
);
735 dev_id
= free_ch
+ 1;
738 * Disable the 1510 compatibility mode and set the sync device
741 dma_write(dev_id
| (1 << 10), CCR(free_ch
));
742 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
743 dma_write(dev_id
, CCR(free_ch
));
746 if (cpu_class_is_omap2()) {
747 omap2_enable_irq_lch(free_ch
);
748 omap_enable_channel_irq(free_ch
);
749 /* Clear the CSR register and IRQ status register */
750 dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR(free_ch
));
751 dma_write(1 << free_ch
, IRQSTATUS_L0
);
754 *dma_ch_out
= free_ch
;
758 EXPORT_SYMBOL(omap_request_dma
);
760 void omap_free_dma(int lch
)
764 spin_lock_irqsave(&dma_chan_lock
, flags
);
765 if (dma_chan
[lch
].dev_id
== -1) {
766 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
768 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
772 dma_chan
[lch
].dev_id
= -1;
773 dma_chan
[lch
].next_lch
= -1;
774 dma_chan
[lch
].callback
= NULL
;
775 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
777 if (cpu_class_is_omap1()) {
778 /* Disable all DMA interrupts for the channel. */
779 dma_write(0, CICR(lch
));
780 /* Make sure the DMA transfer is stopped. */
781 dma_write(0, CCR(lch
));
784 if (cpu_class_is_omap2()) {
786 /* Disable interrupts */
787 val
= dma_read(IRQENABLE_L0
);
789 dma_write(val
, IRQENABLE_L0
);
791 /* Clear the CSR register and IRQ status register */
792 dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR(lch
));
793 dma_write(1 << lch
, IRQSTATUS_L0
);
795 /* Disable all DMA interrupts for the channel. */
796 dma_write(0, CICR(lch
));
798 /* Make sure the DMA transfer is stopped. */
799 dma_write(0, CCR(lch
));
803 EXPORT_SYMBOL(omap_free_dma
);
806 * @brief omap_dma_set_global_params : Set global priority settings for dma
809 * @param max_fifo_depth
810 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
811 * DMA_THREAD_RESERVE_ONET
812 * DMA_THREAD_RESERVE_TWOT
813 * DMA_THREAD_RESERVE_THREET
816 omap_dma_set_global_params(int arb_rate
, int max_fifo_depth
, int tparams
)
820 if (!cpu_class_is_omap2()) {
821 printk(KERN_ERR
"FIXME: no %s on 15xx/16xx\n", __func__
);
828 reg
= (arb_rate
& 0xff) << 16;
829 reg
|= (0xff & max_fifo_depth
);
833 EXPORT_SYMBOL(omap_dma_set_global_params
);
836 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
839 * @param read_prio - Read priority
840 * @param write_prio - Write priority
841 * Both of the above can be set with one of the following values :
842 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
845 omap_dma_set_prio_lch(int lch
, unsigned char read_prio
,
846 unsigned char write_prio
)
850 if (unlikely((lch
< 0 || lch
>= dma_lch_count
))) {
851 printk(KERN_ERR
"Invalid channel id\n");
854 l
= dma_read(CCR(lch
));
855 l
&= ~((1 << 6) | (1 << 26));
856 if (cpu_is_omap2430() || cpu_is_omap34xx())
857 l
|= ((read_prio
& 0x1) << 6) | ((write_prio
& 0x1) << 26);
859 l
|= ((read_prio
& 0x1) << 6);
861 dma_write(l
, CCR(lch
));
865 EXPORT_SYMBOL(omap_dma_set_prio_lch
);
868 * Clears any DMA state so the DMA engine is ready to restart with new buffers
869 * through omap_start_dma(). Any buffers in flight are discarded.
871 void omap_clear_dma(int lch
)
875 local_irq_save(flags
);
877 if (cpu_class_is_omap1()) {
880 l
= dma_read(CCR(lch
));
881 l
&= ~OMAP_DMA_CCR_EN
;
882 dma_write(l
, CCR(lch
));
884 /* Clear pending interrupts */
885 l
= dma_read(CSR(lch
));
888 if (cpu_class_is_omap2()) {
890 void __iomem
*lch_base
= omap_dma_base
+ OMAP_DMA4_CH_BASE(lch
);
891 for (i
= 0; i
< 0x44; i
+= 4)
892 __raw_writel(0, lch_base
+ i
);
895 local_irq_restore(flags
);
897 EXPORT_SYMBOL(omap_clear_dma
);
899 void omap_start_dma(int lch
)
903 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
904 int next_lch
, cur_lch
;
905 char dma_chan_link_map
[OMAP_DMA4_LOGICAL_DMA_CH_COUNT
];
907 dma_chan_link_map
[lch
] = 1;
908 /* Set the link register of the first channel */
911 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
912 cur_lch
= dma_chan
[lch
].next_lch
;
914 next_lch
= dma_chan
[cur_lch
].next_lch
;
916 /* The loop case: we've been here already */
917 if (dma_chan_link_map
[cur_lch
])
919 /* Mark the current channel */
920 dma_chan_link_map
[cur_lch
] = 1;
923 omap_enable_channel_irq(cur_lch
);
926 } while (next_lch
!= -1);
927 } else if (cpu_class_is_omap2()) {
928 /* Errata: Need to write lch even if not using chaining */
929 dma_write(lch
, CLNK_CTRL(lch
));
932 omap_enable_channel_irq(lch
);
934 l
= dma_read(CCR(lch
));
937 * Errata: On ES2.0 BUFFERING disable must be set.
938 * This will always fail on ES1.0
940 if (cpu_is_omap24xx())
941 l
|= OMAP_DMA_CCR_EN
;
943 l
|= OMAP_DMA_CCR_EN
;
944 dma_write(l
, CCR(lch
));
946 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
948 EXPORT_SYMBOL(omap_start_dma
);
950 void omap_stop_dma(int lch
)
954 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
955 int next_lch
, cur_lch
= lch
;
956 char dma_chan_link_map
[OMAP_DMA4_LOGICAL_DMA_CH_COUNT
];
958 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
960 /* The loop case: we've been here already */
961 if (dma_chan_link_map
[cur_lch
])
963 /* Mark the current channel */
964 dma_chan_link_map
[cur_lch
] = 1;
966 disable_lnk(cur_lch
);
968 next_lch
= dma_chan
[cur_lch
].next_lch
;
970 } while (next_lch
!= -1);
975 /* Disable all interrupts on the channel */
976 if (cpu_class_is_omap1())
977 dma_write(0, CICR(lch
));
979 l
= dma_read(CCR(lch
));
980 l
&= ~OMAP_DMA_CCR_EN
;
981 dma_write(l
, CCR(lch
));
983 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
985 EXPORT_SYMBOL(omap_stop_dma
);
988 * Allows changing the DMA callback function or data. This may be needed if
989 * the driver shares a single DMA channel for multiple dma triggers.
991 int omap_set_dma_callback(int lch
,
992 void (*callback
)(int lch
, u16 ch_status
, void *data
),
1000 spin_lock_irqsave(&dma_chan_lock
, flags
);
1001 if (dma_chan
[lch
].dev_id
== -1) {
1002 printk(KERN_ERR
"DMA callback for not set for free channel\n");
1003 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1006 dma_chan
[lch
].callback
= callback
;
1007 dma_chan
[lch
].data
= data
;
1008 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1012 EXPORT_SYMBOL(omap_set_dma_callback
);
1015 * Returns current physical source address for the given DMA channel.
1016 * If the channel is running the caller must disable interrupts prior calling
1017 * this function and process the returned value before re-enabling interrupt to
1018 * prevent races with the interrupt handler. Note that in continuous mode there
1019 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1020 * in incorrect return value.
1022 dma_addr_t
omap_get_dma_src_pos(int lch
)
1024 dma_addr_t offset
= 0;
1026 if (cpu_is_omap15xx())
1027 offset
= dma_read(CPC(lch
));
1029 offset
= dma_read(CSAC(lch
));
1032 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1033 * read before the DMA controller finished disabling the channel.
1035 if (!cpu_is_omap15xx() && offset
== 0)
1036 offset
= dma_read(CSAC(lch
));
1038 if (cpu_class_is_omap1())
1039 offset
|= (dma_read(CSSA_U(lch
)) << 16);
1043 EXPORT_SYMBOL(omap_get_dma_src_pos
);
1046 * Returns current physical destination address for the given DMA channel.
1047 * If the channel is running the caller must disable interrupts prior calling
1048 * this function and process the returned value before re-enabling interrupt to
1049 * prevent races with the interrupt handler. Note that in continuous mode there
1050 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1051 * in incorrect return value.
1053 dma_addr_t
omap_get_dma_dst_pos(int lch
)
1055 dma_addr_t offset
= 0;
1057 if (cpu_is_omap15xx())
1058 offset
= dma_read(CPC(lch
));
1060 offset
= dma_read(CDAC(lch
));
1063 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1064 * read before the DMA controller finished disabling the channel.
1066 if (!cpu_is_omap15xx() && offset
== 0)
1067 offset
= dma_read(CDAC(lch
));
1069 if (cpu_class_is_omap1())
1070 offset
|= (dma_read(CDSA_U(lch
)) << 16);
1074 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
1076 int omap_get_dma_active_status(int lch
)
1078 return (dma_read(CCR(lch
)) & OMAP_DMA_CCR_EN
) != 0;
1080 EXPORT_SYMBOL(omap_get_dma_active_status
);
1082 int omap_dma_running(void)
1086 /* Check if LCD DMA is running */
1087 if (cpu_is_omap16xx())
1088 if (omap_readw(OMAP1610_DMA_LCD_CCR
) & OMAP_DMA_CCR_EN
)
1091 for (lch
= 0; lch
< dma_chan_count
; lch
++)
1092 if (dma_read(CCR(lch
)) & OMAP_DMA_CCR_EN
)
1099 * lch_queue DMA will start right after lch_head one is finished.
1100 * For this DMA link to start, you still need to start (see omap_start_dma)
1101 * the first one. That will fire up the entire queue.
1103 void omap_dma_link_lch(int lch_head
, int lch_queue
)
1105 if (omap_dma_in_1510_mode()) {
1106 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1111 if ((dma_chan
[lch_head
].dev_id
== -1) ||
1112 (dma_chan
[lch_queue
].dev_id
== -1)) {
1113 printk(KERN_ERR
"omap_dma: trying to link "
1114 "non requested channels\n");
1118 dma_chan
[lch_head
].next_lch
= lch_queue
;
1120 EXPORT_SYMBOL(omap_dma_link_lch
);
1123 * Once the DMA queue is stopped, we can destroy it.
1125 void omap_dma_unlink_lch(int lch_head
, int lch_queue
)
1127 if (omap_dma_in_1510_mode()) {
1128 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1133 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
1134 dma_chan
[lch_head
].next_lch
== -1) {
1135 printk(KERN_ERR
"omap_dma: trying to unlink "
1136 "non linked channels\n");
1140 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
1141 (dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
)) {
1142 printk(KERN_ERR
"omap_dma: You need to stop the DMA channels "
1143 "before unlinking\n");
1147 dma_chan
[lch_head
].next_lch
= -1;
1149 EXPORT_SYMBOL(omap_dma_unlink_lch
);
1151 /*----------------------------------------------------------------------------*/
1153 #ifndef CONFIG_ARCH_OMAP1
1154 /* Create chain of DMA channesls */
1155 static void create_dma_lch_chain(int lch_head
, int lch_queue
)
1159 /* Check if this is the first link in chain */
1160 if (dma_chan
[lch_head
].next_linked_ch
== -1) {
1161 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1162 dma_chan
[lch_head
].prev_linked_ch
= lch_queue
;
1163 dma_chan
[lch_queue
].next_linked_ch
= lch_head
;
1164 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1167 /* a link exists, link the new channel in circular chain */
1169 dma_chan
[lch_queue
].next_linked_ch
=
1170 dma_chan
[lch_head
].next_linked_ch
;
1171 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1172 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1173 dma_chan
[dma_chan
[lch_queue
].next_linked_ch
].prev_linked_ch
=
1177 l
= dma_read(CLNK_CTRL(lch_head
));
1180 dma_write(l
, CLNK_CTRL(lch_head
));
1182 l
= dma_read(CLNK_CTRL(lch_queue
));
1184 l
|= (dma_chan
[lch_queue
].next_linked_ch
);
1185 dma_write(l
, CLNK_CTRL(lch_queue
));
1189 * @brief omap_request_dma_chain : Request a chain of DMA channels
1191 * @param dev_id - Device id using the dma channel
1192 * @param dev_name - Device name
1193 * @param callback - Call back function
1195 * @no_of_chans - Number of channels requested
1196 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1197 * OMAP_DMA_DYNAMIC_CHAIN
1198 * @params - Channel parameters
1200 * @return - Succes : 0
1201 * Failure: -EINVAL/-ENOMEM
1203 int omap_request_dma_chain(int dev_id
, const char *dev_name
,
1204 void (*callback
) (int chain_id
, u16 ch_status
,
1206 int *chain_id
, int no_of_chans
, int chain_mode
,
1207 struct omap_dma_channel_params params
)
1212 /* Is the chain mode valid ? */
1213 if (chain_mode
!= OMAP_DMA_STATIC_CHAIN
1214 && chain_mode
!= OMAP_DMA_DYNAMIC_CHAIN
) {
1215 printk(KERN_ERR
"Invalid chain mode requested\n");
1219 if (unlikely((no_of_chans
< 1
1220 || no_of_chans
> dma_lch_count
))) {
1221 printk(KERN_ERR
"Invalid Number of channels requested\n");
1225 /* Allocate a queue to maintain the status of the channels
1227 channels
= kmalloc(sizeof(*channels
) * no_of_chans
, GFP_KERNEL
);
1228 if (channels
== NULL
) {
1229 printk(KERN_ERR
"omap_dma: No memory for channel queue\n");
1233 /* request and reserve DMA channels for the chain */
1234 for (i
= 0; i
< no_of_chans
; i
++) {
1235 err
= omap_request_dma(dev_id
, dev_name
,
1236 callback
, 0, &channels
[i
]);
1239 for (j
= 0; j
< i
; j
++)
1240 omap_free_dma(channels
[j
]);
1242 printk(KERN_ERR
"omap_dma: Request failed %d\n", err
);
1245 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1246 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1249 * Allowing client drivers to set common parameters now,
1250 * so that later only relevant (src_start, dest_start
1251 * and element count) can be set
1253 omap_set_dma_params(channels
[i
], ¶ms
);
1256 *chain_id
= channels
[0];
1257 dma_linked_lch
[*chain_id
].linked_dmach_q
= channels
;
1258 dma_linked_lch
[*chain_id
].chain_mode
= chain_mode
;
1259 dma_linked_lch
[*chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1260 dma_linked_lch
[*chain_id
].no_of_lchs_linked
= no_of_chans
;
1262 for (i
= 0; i
< no_of_chans
; i
++)
1263 dma_chan
[channels
[i
]].chain_id
= *chain_id
;
1265 /* Reset the Queue pointers */
1266 OMAP_DMA_CHAIN_QINIT(*chain_id
);
1268 /* Set up the chain */
1269 if (no_of_chans
== 1)
1270 create_dma_lch_chain(channels
[0], channels
[0]);
1272 for (i
= 0; i
< (no_of_chans
- 1); i
++)
1273 create_dma_lch_chain(channels
[i
], channels
[i
+ 1]);
1278 EXPORT_SYMBOL(omap_request_dma_chain
);
1281 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1282 * params after setting it. Dont do this while dma is running!!
1284 * @param chain_id - Chained logical channel id.
1287 * @return - Success : 0
1290 int omap_modify_dma_chain_params(int chain_id
,
1291 struct omap_dma_channel_params params
)
1296 /* Check for input params */
1297 if (unlikely((chain_id
< 0
1298 || chain_id
>= dma_lch_count
))) {
1299 printk(KERN_ERR
"Invalid chain id\n");
1303 /* Check if the chain exists */
1304 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1305 printk(KERN_ERR
"Chain doesn't exists\n");
1308 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1310 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1312 * Allowing client drivers to set common parameters now,
1313 * so that later only relevant (src_start, dest_start
1314 * and element count) can be set
1316 omap_set_dma_params(channels
[i
], ¶ms
);
1321 EXPORT_SYMBOL(omap_modify_dma_chain_params
);
1324 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1328 * @return - Success : 0
1331 int omap_free_dma_chain(int chain_id
)
1336 /* Check for input params */
1337 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1338 printk(KERN_ERR
"Invalid chain id\n");
1342 /* Check if the chain exists */
1343 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1344 printk(KERN_ERR
"Chain doesn't exists\n");
1348 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1349 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1350 dma_chan
[channels
[i
]].next_linked_ch
= -1;
1351 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1352 dma_chan
[channels
[i
]].chain_id
= -1;
1353 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1354 omap_free_dma(channels
[i
]);
1359 dma_linked_lch
[chain_id
].linked_dmach_q
= NULL
;
1360 dma_linked_lch
[chain_id
].chain_mode
= -1;
1361 dma_linked_lch
[chain_id
].chain_state
= -1;
1365 EXPORT_SYMBOL(omap_free_dma_chain
);
1368 * @brief omap_dma_chain_status - Check if the chain is in
1369 * active / inactive state.
1372 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1375 int omap_dma_chain_status(int chain_id
)
1377 /* Check for input params */
1378 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1379 printk(KERN_ERR
"Invalid chain id\n");
1383 /* Check if the chain exists */
1384 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1385 printk(KERN_ERR
"Chain doesn't exists\n");
1388 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id
,
1389 dma_linked_lch
[chain_id
].q_count
);
1391 if (OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1392 return OMAP_DMA_CHAIN_INACTIVE
;
1394 return OMAP_DMA_CHAIN_ACTIVE
;
1396 EXPORT_SYMBOL(omap_dma_chain_status
);
1399 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1400 * set the params and start the transfer.
1403 * @param src_start - buffer start address
1404 * @param dest_start - Dest address
1406 * @param frame_count
1407 * @param callbk_data - channel callback parameter data.
1409 * @return - Success : 0
1410 * Failure: -EINVAL/-EBUSY
1412 int omap_dma_chain_a_transfer(int chain_id
, int src_start
, int dest_start
,
1413 int elem_count
, int frame_count
, void *callbk_data
)
1420 * if buffer size is less than 1 then there is
1421 * no use of starting the chain
1423 if (elem_count
< 1) {
1424 printk(KERN_ERR
"Invalid buffer size\n");
1428 /* Check for input params */
1429 if (unlikely((chain_id
< 0
1430 || chain_id
>= dma_lch_count
))) {
1431 printk(KERN_ERR
"Invalid chain id\n");
1435 /* Check if the chain exists */
1436 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1437 printk(KERN_ERR
"Chain doesn't exist\n");
1441 /* Check if all the channels in chain are in use */
1442 if (OMAP_DMA_CHAIN_QFULL(chain_id
))
1445 /* Frame count may be negative in case of indexed transfers */
1446 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1448 /* Get a free channel */
1449 lch
= channels
[dma_linked_lch
[chain_id
].q_tail
];
1451 /* Store the callback data */
1452 dma_chan
[lch
].data
= callbk_data
;
1454 /* Increment the q_tail */
1455 OMAP_DMA_CHAIN_INCQTAIL(chain_id
);
1457 /* Set the params to the free channel */
1459 dma_write(src_start
, CSSA(lch
));
1460 if (dest_start
!= 0)
1461 dma_write(dest_start
, CDSA(lch
));
1463 /* Write the buffer size */
1464 dma_write(elem_count
, CEN(lch
));
1465 dma_write(frame_count
, CFN(lch
));
1468 * If the chain is dynamically linked,
1469 * then we may have to start the chain if its not active
1471 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_DYNAMIC_CHAIN
) {
1474 * In Dynamic chain, if the chain is not started,
1477 if (dma_linked_lch
[chain_id
].chain_state
==
1478 DMA_CHAIN_NOTSTARTED
) {
1479 /* Enable the link in previous channel */
1480 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1482 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1483 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1487 * Chain is already started, make sure its active,
1488 * if not then start the chain
1493 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1495 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1496 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1498 if (0 == ((1 << 7) & dma_read(
1499 CCR(dma_chan
[lch
].prev_linked_ch
)))) {
1500 disable_lnk(dma_chan
[lch
].
1502 pr_debug("\n prev ch is stopped\n");
1507 else if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
1509 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1510 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1513 omap_enable_channel_irq(lch
);
1515 l
= dma_read(CCR(lch
));
1517 if ((0 == (l
& (1 << 24))))
1521 if (start_dma
== 1) {
1522 if (0 == (l
& (1 << 7))) {
1524 dma_chan
[lch
].state
= DMA_CH_STARTED
;
1525 pr_debug("starting %d\n", lch
);
1526 dma_write(l
, CCR(lch
));
1530 if (0 == (l
& (1 << 7)))
1531 dma_write(l
, CCR(lch
));
1533 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
1539 EXPORT_SYMBOL(omap_dma_chain_a_transfer
);
1542 * @brief omap_start_dma_chain_transfers - Start the chain
1546 * @return - Success : 0
1547 * Failure : -EINVAL/-EBUSY
1549 int omap_start_dma_chain_transfers(int chain_id
)
1554 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1555 printk(KERN_ERR
"Invalid chain id\n");
1559 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1561 if (dma_linked_lch
[channels
[0]].chain_state
== DMA_CHAIN_STARTED
) {
1562 printk(KERN_ERR
"Chain is already started\n");
1566 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_STATIC_CHAIN
) {
1567 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
;
1569 enable_lnk(channels
[i
]);
1570 omap_enable_channel_irq(channels
[i
]);
1573 omap_enable_channel_irq(channels
[0]);
1576 l
= dma_read(CCR(channels
[0]));
1578 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_STARTED
;
1579 dma_chan
[channels
[0]].state
= DMA_CH_STARTED
;
1581 if ((0 == (l
& (1 << 24))))
1585 dma_write(l
, CCR(channels
[0]));
1587 dma_chan
[channels
[0]].flags
|= OMAP_DMA_ACTIVE
;
1591 EXPORT_SYMBOL(omap_start_dma_chain_transfers
);
1594 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1598 * @return - Success : 0
1601 int omap_stop_dma_chain_transfers(int chain_id
)
1607 /* Check for input params */
1608 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1609 printk(KERN_ERR
"Invalid chain id\n");
1613 /* Check if the chain exists */
1614 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1615 printk(KERN_ERR
"Chain doesn't exists\n");
1618 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1622 * Special programming model needed to disable DMA before end of block
1624 sys_cf
= dma_read(OCP_SYSCONFIG
);
1626 /* Middle mode reg set no Standby */
1627 l
&= ~((1 << 12)|(1 << 13));
1628 dma_write(l
, OCP_SYSCONFIG
);
1630 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1632 /* Stop the Channel transmission */
1633 l
= dma_read(CCR(channels
[i
]));
1635 dma_write(l
, CCR(channels
[i
]));
1637 /* Disable the link in all the channels */
1638 disable_lnk(channels
[i
]);
1639 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1642 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1644 /* Reset the Queue pointers */
1645 OMAP_DMA_CHAIN_QINIT(chain_id
);
1647 /* Errata - put in the old value */
1648 dma_write(sys_cf
, OCP_SYSCONFIG
);
1652 EXPORT_SYMBOL(omap_stop_dma_chain_transfers
);
1654 /* Get the index of the ongoing DMA in chain */
1656 * @brief omap_get_dma_chain_index - Get the element and frame index
1657 * of the ongoing DMA in chain
1660 * @param ei - Element index
1661 * @param fi - Frame index
1663 * @return - Success : 0
1666 int omap_get_dma_chain_index(int chain_id
, int *ei
, int *fi
)
1671 /* Check for input params */
1672 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1673 printk(KERN_ERR
"Invalid chain id\n");
1677 /* Check if the chain exists */
1678 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1679 printk(KERN_ERR
"Chain doesn't exists\n");
1685 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1687 /* Get the current channel */
1688 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1690 *ei
= dma_read(CCEN(lch
));
1691 *fi
= dma_read(CCFN(lch
));
1695 EXPORT_SYMBOL(omap_get_dma_chain_index
);
1698 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1699 * ongoing DMA in chain
1703 * @return - Success : Destination position
1706 int omap_get_dma_chain_dst_pos(int chain_id
)
1711 /* Check for input params */
1712 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1713 printk(KERN_ERR
"Invalid chain id\n");
1717 /* Check if the chain exists */
1718 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1719 printk(KERN_ERR
"Chain doesn't exists\n");
1723 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1725 /* Get the current channel */
1726 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1728 return dma_read(CDAC(lch
));
1730 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos
);
1733 * @brief omap_get_dma_chain_src_pos - Get the source position
1734 * of the ongoing DMA in chain
1737 * @return - Success : Destination position
1740 int omap_get_dma_chain_src_pos(int chain_id
)
1745 /* Check for input params */
1746 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1747 printk(KERN_ERR
"Invalid chain id\n");
1751 /* Check if the chain exists */
1752 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1753 printk(KERN_ERR
"Chain doesn't exists\n");
1757 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1759 /* Get the current channel */
1760 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1762 return dma_read(CSAC(lch
));
1764 EXPORT_SYMBOL(omap_get_dma_chain_src_pos
);
1765 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1767 /*----------------------------------------------------------------------------*/
1769 #ifdef CONFIG_ARCH_OMAP1
1771 static int omap1_dma_handle_ch(int ch
)
1775 if (enable_1510_mode
&& ch
>= 6) {
1776 csr
= dma_chan
[ch
].saved_csr
;
1777 dma_chan
[ch
].saved_csr
= 0;
1779 csr
= dma_read(CSR(ch
));
1780 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
1781 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
1784 if ((csr
& 0x3f) == 0)
1786 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1787 printk(KERN_WARNING
"Spurious interrupt from DMA channel "
1788 "%d (CSR %04x)\n", ch
, csr
);
1791 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
1792 printk(KERN_WARNING
"DMA timeout with device %d\n",
1793 dma_chan
[ch
].dev_id
);
1794 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
1795 printk(KERN_WARNING
"DMA synchronization event drop occurred "
1796 "with device %d\n", dma_chan
[ch
].dev_id
);
1797 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
1798 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1799 if (likely(dma_chan
[ch
].callback
!= NULL
))
1800 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
1805 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
)
1807 int ch
= ((int) dev_id
) - 1;
1811 int handled_now
= 0;
1813 handled_now
+= omap1_dma_handle_ch(ch
);
1814 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
1815 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
1818 handled
+= handled_now
;
1821 return handled
? IRQ_HANDLED
: IRQ_NONE
;
1825 #define omap1_dma_irq_handler NULL
1828 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1830 static int omap2_dma_handle_ch(int ch
)
1832 u32 status
= dma_read(CSR(ch
));
1835 if (printk_ratelimit())
1836 printk(KERN_WARNING
"Spurious DMA IRQ for lch %d\n",
1838 dma_write(1 << ch
, IRQSTATUS_L0
);
1841 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1842 if (printk_ratelimit())
1843 printk(KERN_WARNING
"IRQ %04x for non-allocated DMA"
1844 "channel %d\n", status
, ch
);
1847 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
1849 "DMA synchronization event drop occurred with device "
1850 "%d\n", dma_chan
[ch
].dev_id
);
1851 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
))
1852 printk(KERN_INFO
"DMA transaction error with device %d\n",
1853 dma_chan
[ch
].dev_id
);
1854 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
1855 printk(KERN_INFO
"DMA secure error with device %d\n",
1856 dma_chan
[ch
].dev_id
);
1857 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
1858 printk(KERN_INFO
"DMA misaligned error with device %d\n",
1859 dma_chan
[ch
].dev_id
);
1861 dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR(ch
));
1862 dma_write(1 << ch
, IRQSTATUS_L0
);
1864 /* If the ch is not chained then chain_id will be -1 */
1865 if (dma_chan
[ch
].chain_id
!= -1) {
1866 int chain_id
= dma_chan
[ch
].chain_id
;
1867 dma_chan
[ch
].state
= DMA_CH_NOTSTARTED
;
1868 if (dma_read(CLNK_CTRL(ch
)) & (1 << 15))
1869 dma_chan
[dma_chan
[ch
].next_linked_ch
].state
=
1871 if (dma_linked_lch
[chain_id
].chain_mode
==
1872 OMAP_DMA_DYNAMIC_CHAIN
)
1875 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1876 OMAP_DMA_CHAIN_INCQHEAD(chain_id
);
1878 status
= dma_read(CSR(ch
));
1881 if (likely(dma_chan
[ch
].callback
!= NULL
))
1882 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
1884 dma_write(status
, CSR(ch
));
1889 /* STATUS register count is from 1-32 while our is 0-31 */
1890 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
)
1895 val
= dma_read(IRQSTATUS_L0
);
1897 if (printk_ratelimit())
1898 printk(KERN_WARNING
"Spurious DMA IRQ\n");
1901 for (i
= 0; i
< dma_lch_count
&& val
!= 0; i
++) {
1903 omap2_dma_handle_ch(i
);
1910 static struct irqaction omap24xx_dma_irq
= {
1912 .handler
= omap2_dma_irq_handler
,
1913 .flags
= IRQF_DISABLED
1917 static struct irqaction omap24xx_dma_irq
;
1920 /*----------------------------------------------------------------------------*/
1922 static struct lcd_dma_info
{
1925 void (*callback
)(u16 status
, void *data
);
1929 unsigned long addr
, size
;
1930 int rotate
, data_type
, xres
, yres
;
1936 int single_transfer
;
1939 void omap_set_lcd_dma_b1(unsigned long addr
, u16 fb_xres
, u16 fb_yres
,
1942 lcd_dma
.addr
= addr
;
1943 lcd_dma
.data_type
= data_type
;
1944 lcd_dma
.xres
= fb_xres
;
1945 lcd_dma
.yres
= fb_yres
;
1947 EXPORT_SYMBOL(omap_set_lcd_dma_b1
);
1949 void omap_set_lcd_dma_src_port(int port
)
1951 lcd_dma
.src_port
= port
;
1954 void omap_set_lcd_dma_ext_controller(int external
)
1956 lcd_dma
.ext_ctrl
= external
;
1958 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller
);
1960 void omap_set_lcd_dma_single_transfer(int single
)
1962 lcd_dma
.single_transfer
= single
;
1964 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer
);
1966 void omap_set_lcd_dma_b1_rotation(int rotate
)
1968 if (omap_dma_in_1510_mode()) {
1969 printk(KERN_ERR
"DMA rotation is not supported in 1510 mode\n");
1973 lcd_dma
.rotate
= rotate
;
1975 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation
);
1977 void omap_set_lcd_dma_b1_mirror(int mirror
)
1979 if (omap_dma_in_1510_mode()) {
1980 printk(KERN_ERR
"DMA mirror is not supported in 1510 mode\n");
1983 lcd_dma
.mirror
= mirror
;
1985 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror
);
1987 void omap_set_lcd_dma_b1_vxres(unsigned long vxres
)
1989 if (omap_dma_in_1510_mode()) {
1990 printk(KERN_ERR
"DMA virtual resulotion is not supported "
1994 lcd_dma
.vxres
= vxres
;
1996 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres
);
1998 void omap_set_lcd_dma_b1_scale(unsigned int xscale
, unsigned int yscale
)
2000 if (omap_dma_in_1510_mode()) {
2001 printk(KERN_ERR
"DMA scale is not supported in 1510 mode\n");
2004 lcd_dma
.xscale
= xscale
;
2005 lcd_dma
.yscale
= yscale
;
2007 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale
);
2009 static void set_b1_regs(void)
2011 unsigned long top
, bottom
;
2014 unsigned long en
, fn
;
2016 unsigned long vxres
;
2017 unsigned int xscale
, yscale
;
2019 switch (lcd_dma
.data_type
) {
2020 case OMAP_DMA_DATA_TYPE_S8
:
2023 case OMAP_DMA_DATA_TYPE_S16
:
2026 case OMAP_DMA_DATA_TYPE_S32
:
2034 vxres
= lcd_dma
.vxres
? lcd_dma
.vxres
: lcd_dma
.xres
;
2035 xscale
= lcd_dma
.xscale
? lcd_dma
.xscale
: 1;
2036 yscale
= lcd_dma
.yscale
? lcd_dma
.yscale
: 1;
2037 BUG_ON(vxres
< lcd_dma
.xres
);
2039 #define PIXADDR(x, y) (lcd_dma.addr + \
2040 ((y) * vxres * yscale + (x) * xscale) * es)
2041 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2043 switch (lcd_dma
.rotate
) {
2045 if (!lcd_dma
.mirror
) {
2046 top
= PIXADDR(0, 0);
2047 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
2048 /* 1510 DMA requires the bottom address to be 2 more
2049 * than the actual last memory access location. */
2050 if (omap_dma_in_1510_mode() &&
2051 lcd_dma
.data_type
== OMAP_DMA_DATA_TYPE_S32
)
2053 ei
= PIXSTEP(0, 0, 1, 0);
2054 fi
= PIXSTEP(lcd_dma
.xres
- 1, 0, 0, 1);
2056 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
2057 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
2058 ei
= PIXSTEP(1, 0, 0, 0);
2059 fi
= PIXSTEP(0, 0, lcd_dma
.xres
- 1, 1);
2065 if (!lcd_dma
.mirror
) {
2066 top
= PIXADDR(0, lcd_dma
.yres
- 1);
2067 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
2068 ei
= PIXSTEP(0, 1, 0, 0);
2069 fi
= PIXSTEP(0, 0, 1, lcd_dma
.yres
- 1);
2071 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
2072 bottom
= PIXADDR(0, 0);
2073 ei
= PIXSTEP(0, 1, 0, 0);
2074 fi
= PIXSTEP(1, 0, 0, lcd_dma
.yres
- 1);
2080 if (!lcd_dma
.mirror
) {
2081 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
2082 bottom
= PIXADDR(0, 0);
2083 ei
= PIXSTEP(1, 0, 0, 0);
2084 fi
= PIXSTEP(0, 1, lcd_dma
.xres
- 1, 0);
2086 top
= PIXADDR(0, lcd_dma
.yres
- 1);
2087 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
2088 ei
= PIXSTEP(0, 0, 1, 0);
2089 fi
= PIXSTEP(lcd_dma
.xres
- 1, 1, 0, 0);
2095 if (!lcd_dma
.mirror
) {
2096 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
2097 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
2098 ei
= PIXSTEP(0, 0, 0, 1);
2099 fi
= PIXSTEP(1, lcd_dma
.yres
- 1, 0, 0);
2101 top
= PIXADDR(0, 0);
2102 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
2103 ei
= PIXSTEP(0, 0, 0, 1);
2104 fi
= PIXSTEP(0, lcd_dma
.yres
- 1, 1, 0);
2111 return; /* Suppress warning about uninitialized vars */
2114 if (omap_dma_in_1510_mode()) {
2115 omap_writew(top
>> 16, OMAP1510_DMA_LCD_TOP_F1_U
);
2116 omap_writew(top
, OMAP1510_DMA_LCD_TOP_F1_L
);
2117 omap_writew(bottom
>> 16, OMAP1510_DMA_LCD_BOT_F1_U
);
2118 omap_writew(bottom
, OMAP1510_DMA_LCD_BOT_F1_L
);
2124 omap_writew(top
>> 16, OMAP1610_DMA_LCD_TOP_B1_U
);
2125 omap_writew(top
, OMAP1610_DMA_LCD_TOP_B1_L
);
2126 omap_writew(bottom
>> 16, OMAP1610_DMA_LCD_BOT_B1_U
);
2127 omap_writew(bottom
, OMAP1610_DMA_LCD_BOT_B1_L
);
2129 omap_writew(en
, OMAP1610_DMA_LCD_SRC_EN_B1
);
2130 omap_writew(fn
, OMAP1610_DMA_LCD_SRC_FN_B1
);
2132 w
= omap_readw(OMAP1610_DMA_LCD_CSDP
);
2134 w
|= lcd_dma
.data_type
;
2135 omap_writew(w
, OMAP1610_DMA_LCD_CSDP
);
2137 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2138 /* Always set the source port as SDRAM for now*/
2140 if (lcd_dma
.callback
!= NULL
)
2141 w
|= 1 << 1; /* Block interrupt enable */
2144 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2146 if (!(lcd_dma
.rotate
|| lcd_dma
.mirror
||
2147 lcd_dma
.vxres
|| lcd_dma
.xscale
|| lcd_dma
.yscale
))
2150 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2151 /* Set the double-indexed addressing mode */
2153 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2155 omap_writew(ei
, OMAP1610_DMA_LCD_SRC_EI_B1
);
2156 omap_writew(fi
>> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U
);
2157 omap_writew(fi
, OMAP1610_DMA_LCD_SRC_FI_B1_L
);
2160 static irqreturn_t
lcd_dma_irq_handler(int irq
, void *dev_id
)
2164 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2165 if (unlikely(!(w
& (1 << 3)))) {
2166 printk(KERN_WARNING
"Spurious LCD DMA IRQ\n");
2171 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2173 if (lcd_dma
.callback
!= NULL
)
2174 lcd_dma
.callback(w
, lcd_dma
.cb_data
);
2179 int omap_request_lcd_dma(void (*callback
)(u16 status
, void *data
),
2182 spin_lock_irq(&lcd_dma
.lock
);
2183 if (lcd_dma
.reserved
) {
2184 spin_unlock_irq(&lcd_dma
.lock
);
2185 printk(KERN_ERR
"LCD DMA channel already reserved\n");
2189 lcd_dma
.reserved
= 1;
2190 spin_unlock_irq(&lcd_dma
.lock
);
2191 lcd_dma
.callback
= callback
;
2192 lcd_dma
.cb_data
= data
;
2194 lcd_dma
.single_transfer
= 0;
2200 lcd_dma
.ext_ctrl
= 0;
2201 lcd_dma
.src_port
= 0;
2205 EXPORT_SYMBOL(omap_request_lcd_dma
);
2207 void omap_free_lcd_dma(void)
2209 spin_lock(&lcd_dma
.lock
);
2210 if (!lcd_dma
.reserved
) {
2211 spin_unlock(&lcd_dma
.lock
);
2212 printk(KERN_ERR
"LCD DMA is not reserved\n");
2216 if (!enable_1510_mode
)
2217 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR
) & ~1,
2218 OMAP1610_DMA_LCD_CCR
);
2219 lcd_dma
.reserved
= 0;
2220 spin_unlock(&lcd_dma
.lock
);
2222 EXPORT_SYMBOL(omap_free_lcd_dma
);
2224 void omap_enable_lcd_dma(void)
2229 * Set the Enable bit only if an external controller is
2230 * connected. Otherwise the OMAP internal controller will
2231 * start the transfer when it gets enabled.
2233 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
2236 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2238 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2242 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2244 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2246 EXPORT_SYMBOL(omap_enable_lcd_dma
);
2248 void omap_setup_lcd_dma(void)
2250 BUG_ON(lcd_dma
.active
);
2251 if (!enable_1510_mode
) {
2252 /* Set some reasonable defaults */
2253 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR
);
2254 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP
);
2255 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL
);
2258 if (!enable_1510_mode
) {
2261 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2263 * If DMA was already active set the end_prog bit to have
2264 * the programmed register set loaded into the active
2267 w
|= 1 << 11; /* End_prog */
2268 if (!lcd_dma
.single_transfer
)
2269 w
|= (3 << 8); /* Auto_init, repeat */
2270 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2273 EXPORT_SYMBOL(omap_setup_lcd_dma
);
2275 void omap_stop_lcd_dma(void)
2280 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
2283 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
2285 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
2287 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2289 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2291 EXPORT_SYMBOL(omap_stop_lcd_dma
);
2293 /*----------------------------------------------------------------------------*/
2295 static int __init
omap_init_dma(void)
2299 if (cpu_class_is_omap1()) {
2300 omap_dma_base
= (void __iomem
*)IO_ADDRESS(OMAP1_DMA_BASE
);
2301 dma_lch_count
= OMAP1_LOGICAL_DMA_CH_COUNT
;
2302 } else if (cpu_is_omap24xx()) {
2303 omap_dma_base
= (void __iomem
*)IO_ADDRESS(OMAP24XX_DMA4_BASE
);
2304 dma_lch_count
= OMAP_DMA4_LOGICAL_DMA_CH_COUNT
;
2305 } else if (cpu_is_omap34xx()) {
2306 omap_dma_base
= (void __iomem
*)IO_ADDRESS(OMAP34XX_DMA4_BASE
);
2307 dma_lch_count
= OMAP_DMA4_LOGICAL_DMA_CH_COUNT
;
2309 pr_err("DMA init failed for unsupported omap\n");
2313 dma_chan
= kzalloc(sizeof(struct omap_dma_lch
) * dma_lch_count
,
2318 if (cpu_class_is_omap2()) {
2319 dma_linked_lch
= kzalloc(sizeof(struct dma_link_info
) *
2320 dma_lch_count
, GFP_KERNEL
);
2321 if (!dma_linked_lch
) {
2327 if (cpu_is_omap15xx()) {
2328 printk(KERN_INFO
"DMA support for OMAP15xx initialized\n");
2330 enable_1510_mode
= 1;
2331 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2332 printk(KERN_INFO
"OMAP DMA hardware version %d\n",
2334 printk(KERN_INFO
"DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2335 (dma_read(CAPS_0_U
) << 16) |
2337 (dma_read(CAPS_1_U
) << 16) |
2339 dma_read(CAPS_2
), dma_read(CAPS_3
),
2341 if (!enable_1510_mode
) {
2344 /* Disable OMAP 3.0/3.1 compatibility mode. */
2348 dma_chan_count
= 16;
2351 if (cpu_is_omap16xx()) {
2354 /* this would prevent OMAP sleep */
2355 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
2357 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
2359 } else if (cpu_class_is_omap2()) {
2360 u8 revision
= dma_read(REVISION
) & 0xff;
2361 printk(KERN_INFO
"OMAP DMA hardware revision %d.%d\n",
2362 revision
>> 4, revision
& 0xf);
2363 dma_chan_count
= OMAP_DMA4_LOGICAL_DMA_CH_COUNT
;
2369 spin_lock_init(&lcd_dma
.lock
);
2370 spin_lock_init(&dma_chan_lock
);
2372 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
2374 dma_chan
[ch
].dev_id
= -1;
2375 dma_chan
[ch
].next_lch
= -1;
2377 if (ch
>= 6 && enable_1510_mode
)
2380 if (cpu_class_is_omap1()) {
2382 * request_irq() doesn't like dev_id (ie. ch) being
2383 * zero, so we have to kludge around this.
2385 r
= request_irq(omap1_dma_irq
[ch
],
2386 omap1_dma_irq_handler
, 0, "DMA",
2391 printk(KERN_ERR
"unable to request IRQ %d "
2392 "for DMA (error %d)\n",
2393 omap1_dma_irq
[ch
], r
);
2394 for (i
= 0; i
< ch
; i
++)
2395 free_irq(omap1_dma_irq
[i
],
2402 if (cpu_is_omap2430() || cpu_is_omap34xx())
2403 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE
,
2404 DMA_DEFAULT_FIFO_DEPTH
, 0);
2406 if (cpu_class_is_omap2())
2407 setup_irq(INT_24XX_SDMA_IRQ0
, &omap24xx_dma_irq
);
2409 /* FIXME: Update LCD DMA to work on 24xx */
2410 if (cpu_class_is_omap1()) {
2411 r
= request_irq(INT_DMA_LCD
, lcd_dma_irq_handler
, 0,
2416 printk(KERN_ERR
"unable to request IRQ for LCD DMA "
2418 for (i
= 0; i
< dma_chan_count
; i
++)
2419 free_irq(omap1_dma_irq
[i
], (void *) (i
+ 1));
2427 arch_initcall(omap_init_dma
);