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Merge branch 'pm-runtime' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman...
[mirror_ubuntu-zesty-kernel.git] / arch / arm / plat-omap / gpio.c
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30 #include <plat/powerdomain.h>
31
32 /*
33 * OMAP1510 GPIO registers
34 */
35 #define OMAP1510_GPIO_BASE 0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44 #define OMAP1510_IH_GPIO_BASE 64
45
46 /*
47 * OMAP1610 specific GPIO registers
48 */
49 #define OMAP1610_GPIO1_BASE 0xfffbe400
50 #define OMAP1610_GPIO2_BASE 0xfffbec00
51 #define OMAP1610_GPIO3_BASE 0xfffbb400
52 #define OMAP1610_GPIO4_BASE 0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70
71 /*
72 * OMAP7XX specific GPIO registers
73 */
74 #define OMAP7XX_GPIO1_BASE 0xfffbc000
75 #define OMAP7XX_GPIO2_BASE 0xfffbc800
76 #define OMAP7XX_GPIO3_BASE 0xfffbd000
77 #define OMAP7XX_GPIO4_BASE 0xfffbd800
78 #define OMAP7XX_GPIO5_BASE 0xfffbe000
79 #define OMAP7XX_GPIO6_BASE 0xfffbe800
80 #define OMAP7XX_GPIO_DATA_INPUT 0x00
81 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
83 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
84 #define OMAP7XX_GPIO_INT_MASK 0x10
85 #define OMAP7XX_GPIO_INT_STATUS 0x14
86
87 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
88
89 /*
90 * omap24xx specific GPIO registers
91 */
92 #define OMAP242X_GPIO1_BASE 0x48018000
93 #define OMAP242X_GPIO2_BASE 0x4801a000
94 #define OMAP242X_GPIO3_BASE 0x4801c000
95 #define OMAP242X_GPIO4_BASE 0x4801e000
96
97 #define OMAP243X_GPIO1_BASE 0x4900C000
98 #define OMAP243X_GPIO2_BASE 0x4900E000
99 #define OMAP243X_GPIO3_BASE 0x49010000
100 #define OMAP243X_GPIO4_BASE 0x49012000
101 #define OMAP243X_GPIO5_BASE 0x480B6000
102
103 #define OMAP24XX_GPIO_REVISION 0x0000
104 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
105 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
106 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
107 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
109 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
110 #define OMAP24XX_GPIO_WAKE_EN 0x0020
111 #define OMAP24XX_GPIO_CTRL 0x0030
112 #define OMAP24XX_GPIO_OE 0x0034
113 #define OMAP24XX_GPIO_DATAIN 0x0038
114 #define OMAP24XX_GPIO_DATAOUT 0x003c
115 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
116 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
117 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
118 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
119 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
120 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
121 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
122 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
123 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
124 #define OMAP24XX_GPIO_SETWKUENA 0x0084
125 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
126 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
127
128 #define OMAP4_GPIO_REVISION 0x0000
129 #define OMAP4_GPIO_SYSCONFIG 0x0010
130 #define OMAP4_GPIO_EOI 0x0020
131 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
133 #define OMAP4_GPIO_IRQSTATUS0 0x002c
134 #define OMAP4_GPIO_IRQSTATUS1 0x0030
135 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
136 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
137 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
138 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139 #define OMAP4_GPIO_IRQWAKEN0 0x0044
140 #define OMAP4_GPIO_IRQWAKEN1 0x0048
141 #define OMAP4_GPIO_SYSSTATUS 0x0114
142 #define OMAP4_GPIO_IRQENABLE1 0x011c
143 #define OMAP4_GPIO_WAKE_EN 0x0120
144 #define OMAP4_GPIO_IRQSTATUS2 0x0128
145 #define OMAP4_GPIO_IRQENABLE2 0x012c
146 #define OMAP4_GPIO_CTRL 0x0130
147 #define OMAP4_GPIO_OE 0x0134
148 #define OMAP4_GPIO_DATAIN 0x0138
149 #define OMAP4_GPIO_DATAOUT 0x013c
150 #define OMAP4_GPIO_LEVELDETECT0 0x0140
151 #define OMAP4_GPIO_LEVELDETECT1 0x0144
152 #define OMAP4_GPIO_RISINGDETECT 0x0148
153 #define OMAP4_GPIO_FALLINGDETECT 0x014c
154 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
155 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
156 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
157 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
158 #define OMAP4_GPIO_CLEARWKUENA 0x0180
159 #define OMAP4_GPIO_SETWKUENA 0x0184
160 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
161 #define OMAP4_GPIO_SETDATAOUT 0x0194
162 /*
163 * omap34xx specific GPIO registers
164 */
165
166 #define OMAP34XX_GPIO1_BASE 0x48310000
167 #define OMAP34XX_GPIO2_BASE 0x49050000
168 #define OMAP34XX_GPIO3_BASE 0x49052000
169 #define OMAP34XX_GPIO4_BASE 0x49054000
170 #define OMAP34XX_GPIO5_BASE 0x49056000
171 #define OMAP34XX_GPIO6_BASE 0x49058000
172
173 /*
174 * OMAP44XX specific GPIO registers
175 */
176 #define OMAP44XX_GPIO1_BASE 0x4a310000
177 #define OMAP44XX_GPIO2_BASE 0x48055000
178 #define OMAP44XX_GPIO3_BASE 0x48057000
179 #define OMAP44XX_GPIO4_BASE 0x48059000
180 #define OMAP44XX_GPIO5_BASE 0x4805B000
181 #define OMAP44XX_GPIO6_BASE 0x4805D000
182
183 struct gpio_bank {
184 unsigned long pbase;
185 void __iomem *base;
186 u16 irq;
187 u16 virtual_irq_start;
188 int method;
189 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
190 u32 suspend_wakeup;
191 u32 saved_wakeup;
192 #endif
193 #ifdef CONFIG_ARCH_OMAP2PLUS
194 u32 non_wakeup_gpios;
195 u32 enabled_non_wakeup_gpios;
196
197 u32 saved_datain;
198 u32 saved_fallingdetect;
199 u32 saved_risingdetect;
200 #endif
201 u32 level_mask;
202 u32 toggle_mask;
203 spinlock_t lock;
204 struct gpio_chip chip;
205 struct clk *dbck;
206 u32 mod_usage;
207 u32 dbck_enable_mask;
208 };
209
210 #define METHOD_MPUIO 0
211 #define METHOD_GPIO_1510 1
212 #define METHOD_GPIO_1610 2
213 #define METHOD_GPIO_7XX 3
214 #define METHOD_GPIO_24XX 5
215 #define METHOD_GPIO_44XX 6
216
217 #ifdef CONFIG_ARCH_OMAP16XX
218 static struct gpio_bank gpio_bank_1610[5] = {
219 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
220 METHOD_MPUIO },
221 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
222 METHOD_GPIO_1610 },
223 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
224 METHOD_GPIO_1610 },
225 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
226 METHOD_GPIO_1610 },
227 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
228 METHOD_GPIO_1610 },
229 };
230 #endif
231
232 #ifdef CONFIG_ARCH_OMAP15XX
233 static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
235 METHOD_MPUIO },
236 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
237 METHOD_GPIO_1510 }
238 };
239 #endif
240
241 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
242 static struct gpio_bank gpio_bank_7xx[7] = {
243 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
244 METHOD_MPUIO },
245 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
246 METHOD_GPIO_7XX },
247 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
248 METHOD_GPIO_7XX },
249 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
250 METHOD_GPIO_7XX },
251 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
252 METHOD_GPIO_7XX },
253 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
254 METHOD_GPIO_7XX },
255 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
256 METHOD_GPIO_7XX },
257 };
258 #endif
259
260 #ifdef CONFIG_ARCH_OMAP2
261
262 static struct gpio_bank gpio_bank_242x[4] = {
263 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
264 METHOD_GPIO_24XX },
265 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
266 METHOD_GPIO_24XX },
267 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
268 METHOD_GPIO_24XX },
269 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
270 METHOD_GPIO_24XX },
271 };
272
273 static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
275 METHOD_GPIO_24XX },
276 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
277 METHOD_GPIO_24XX },
278 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
279 METHOD_GPIO_24XX },
280 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
281 METHOD_GPIO_24XX },
282 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
283 METHOD_GPIO_24XX },
284 };
285
286 #endif
287
288 #ifdef CONFIG_ARCH_OMAP3
289 static struct gpio_bank gpio_bank_34xx[6] = {
290 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
291 METHOD_GPIO_24XX },
292 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
293 METHOD_GPIO_24XX },
294 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
295 METHOD_GPIO_24XX },
296 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
297 METHOD_GPIO_24XX },
298 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
299 METHOD_GPIO_24XX },
300 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
301 METHOD_GPIO_24XX },
302 };
303
304 struct omap3_gpio_regs {
305 u32 sysconfig;
306 u32 irqenable1;
307 u32 irqenable2;
308 u32 wake_en;
309 u32 ctrl;
310 u32 oe;
311 u32 leveldetect0;
312 u32 leveldetect1;
313 u32 risingdetect;
314 u32 fallingdetect;
315 u32 dataout;
316 };
317
318 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
319 #endif
320
321 #ifdef CONFIG_ARCH_OMAP4
322 static struct gpio_bank gpio_bank_44xx[6] = {
323 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
324 METHOD_GPIO_44XX },
325 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
326 METHOD_GPIO_44XX },
327 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
328 METHOD_GPIO_44XX },
329 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
330 METHOD_GPIO_44XX },
331 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
332 METHOD_GPIO_44XX },
333 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
334 METHOD_GPIO_44XX },
335 };
336
337 #endif
338
339 static struct gpio_bank *gpio_bank;
340 static int gpio_bank_count;
341
342 static inline struct gpio_bank *get_gpio_bank(int gpio)
343 {
344 if (cpu_is_omap15xx()) {
345 if (OMAP_GPIO_IS_MPUIO(gpio))
346 return &gpio_bank[0];
347 return &gpio_bank[1];
348 }
349 if (cpu_is_omap16xx()) {
350 if (OMAP_GPIO_IS_MPUIO(gpio))
351 return &gpio_bank[0];
352 return &gpio_bank[1 + (gpio >> 4)];
353 }
354 if (cpu_is_omap7xx()) {
355 if (OMAP_GPIO_IS_MPUIO(gpio))
356 return &gpio_bank[0];
357 return &gpio_bank[1 + (gpio >> 5)];
358 }
359 if (cpu_is_omap24xx())
360 return &gpio_bank[gpio >> 5];
361 if (cpu_is_omap34xx() || cpu_is_omap44xx())
362 return &gpio_bank[gpio >> 5];
363 BUG();
364 return NULL;
365 }
366
367 static inline int get_gpio_index(int gpio)
368 {
369 if (cpu_is_omap7xx())
370 return gpio & 0x1f;
371 if (cpu_is_omap24xx())
372 return gpio & 0x1f;
373 if (cpu_is_omap34xx() || cpu_is_omap44xx())
374 return gpio & 0x1f;
375 return gpio & 0x0f;
376 }
377
378 static inline int gpio_valid(int gpio)
379 {
380 if (gpio < 0)
381 return -1;
382 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
383 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
384 return -1;
385 return 0;
386 }
387 if (cpu_is_omap15xx() && gpio < 16)
388 return 0;
389 if ((cpu_is_omap16xx()) && gpio < 64)
390 return 0;
391 if (cpu_is_omap7xx() && gpio < 192)
392 return 0;
393 if (cpu_is_omap2420() && gpio < 128)
394 return 0;
395 if (cpu_is_omap2430() && gpio < 160)
396 return 0;
397 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
398 return 0;
399 return -1;
400 }
401
402 static int check_gpio(int gpio)
403 {
404 if (unlikely(gpio_valid(gpio) < 0)) {
405 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
406 dump_stack();
407 return -1;
408 }
409 return 0;
410 }
411
412 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
413 {
414 void __iomem *reg = bank->base;
415 u32 l;
416
417 switch (bank->method) {
418 #ifdef CONFIG_ARCH_OMAP1
419 case METHOD_MPUIO:
420 reg += OMAP_MPUIO_IO_CNTL;
421 break;
422 #endif
423 #ifdef CONFIG_ARCH_OMAP15XX
424 case METHOD_GPIO_1510:
425 reg += OMAP1510_GPIO_DIR_CONTROL;
426 break;
427 #endif
428 #ifdef CONFIG_ARCH_OMAP16XX
429 case METHOD_GPIO_1610:
430 reg += OMAP1610_GPIO_DIRECTION;
431 break;
432 #endif
433 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
434 case METHOD_GPIO_7XX:
435 reg += OMAP7XX_GPIO_DIR_CONTROL;
436 break;
437 #endif
438 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
439 case METHOD_GPIO_24XX:
440 reg += OMAP24XX_GPIO_OE;
441 break;
442 #endif
443 #if defined(CONFIG_ARCH_OMAP4)
444 case METHOD_GPIO_44XX:
445 reg += OMAP4_GPIO_OE;
446 break;
447 #endif
448 default:
449 WARN_ON(1);
450 return;
451 }
452 l = __raw_readl(reg);
453 if (is_input)
454 l |= 1 << gpio;
455 else
456 l &= ~(1 << gpio);
457 __raw_writel(l, reg);
458 }
459
460 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
461 {
462 void __iomem *reg = bank->base;
463 u32 l = 0;
464
465 switch (bank->method) {
466 #ifdef CONFIG_ARCH_OMAP1
467 case METHOD_MPUIO:
468 reg += OMAP_MPUIO_OUTPUT;
469 l = __raw_readl(reg);
470 if (enable)
471 l |= 1 << gpio;
472 else
473 l &= ~(1 << gpio);
474 break;
475 #endif
476 #ifdef CONFIG_ARCH_OMAP15XX
477 case METHOD_GPIO_1510:
478 reg += OMAP1510_GPIO_DATA_OUTPUT;
479 l = __raw_readl(reg);
480 if (enable)
481 l |= 1 << gpio;
482 else
483 l &= ~(1 << gpio);
484 break;
485 #endif
486 #ifdef CONFIG_ARCH_OMAP16XX
487 case METHOD_GPIO_1610:
488 if (enable)
489 reg += OMAP1610_GPIO_SET_DATAOUT;
490 else
491 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
492 l = 1 << gpio;
493 break;
494 #endif
495 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
496 case METHOD_GPIO_7XX:
497 reg += OMAP7XX_GPIO_DATA_OUTPUT;
498 l = __raw_readl(reg);
499 if (enable)
500 l |= 1 << gpio;
501 else
502 l &= ~(1 << gpio);
503 break;
504 #endif
505 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
506 case METHOD_GPIO_24XX:
507 if (enable)
508 reg += OMAP24XX_GPIO_SETDATAOUT;
509 else
510 reg += OMAP24XX_GPIO_CLEARDATAOUT;
511 l = 1 << gpio;
512 break;
513 #endif
514 #ifdef CONFIG_ARCH_OMAP4
515 case METHOD_GPIO_44XX:
516 if (enable)
517 reg += OMAP4_GPIO_SETDATAOUT;
518 else
519 reg += OMAP4_GPIO_CLEARDATAOUT;
520 l = 1 << gpio;
521 break;
522 #endif
523 default:
524 WARN_ON(1);
525 return;
526 }
527 __raw_writel(l, reg);
528 }
529
530 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
531 {
532 void __iomem *reg;
533
534 if (check_gpio(gpio) < 0)
535 return -EINVAL;
536 reg = bank->base;
537 switch (bank->method) {
538 #ifdef CONFIG_ARCH_OMAP1
539 case METHOD_MPUIO:
540 reg += OMAP_MPUIO_INPUT_LATCH;
541 break;
542 #endif
543 #ifdef CONFIG_ARCH_OMAP15XX
544 case METHOD_GPIO_1510:
545 reg += OMAP1510_GPIO_DATA_INPUT;
546 break;
547 #endif
548 #ifdef CONFIG_ARCH_OMAP16XX
549 case METHOD_GPIO_1610:
550 reg += OMAP1610_GPIO_DATAIN;
551 break;
552 #endif
553 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
554 case METHOD_GPIO_7XX:
555 reg += OMAP7XX_GPIO_DATA_INPUT;
556 break;
557 #endif
558 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
559 case METHOD_GPIO_24XX:
560 reg += OMAP24XX_GPIO_DATAIN;
561 break;
562 #endif
563 #ifdef CONFIG_ARCH_OMAP4
564 case METHOD_GPIO_44XX:
565 reg += OMAP4_GPIO_DATAIN;
566 break;
567 #endif
568 default:
569 return -EINVAL;
570 }
571 return (__raw_readl(reg)
572 & (1 << get_gpio_index(gpio))) != 0;
573 }
574
575 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
576 {
577 void __iomem *reg;
578
579 if (check_gpio(gpio) < 0)
580 return -EINVAL;
581 reg = bank->base;
582
583 switch (bank->method) {
584 #ifdef CONFIG_ARCH_OMAP1
585 case METHOD_MPUIO:
586 reg += OMAP_MPUIO_OUTPUT;
587 break;
588 #endif
589 #ifdef CONFIG_ARCH_OMAP15XX
590 case METHOD_GPIO_1510:
591 reg += OMAP1510_GPIO_DATA_OUTPUT;
592 break;
593 #endif
594 #ifdef CONFIG_ARCH_OMAP16XX
595 case METHOD_GPIO_1610:
596 reg += OMAP1610_GPIO_DATAOUT;
597 break;
598 #endif
599 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
600 case METHOD_GPIO_7XX:
601 reg += OMAP7XX_GPIO_DATA_OUTPUT;
602 break;
603 #endif
604 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
605 case METHOD_GPIO_24XX:
606 reg += OMAP24XX_GPIO_DATAOUT;
607 break;
608 #endif
609 #ifdef CONFIG_ARCH_OMAP4
610 case METHOD_GPIO_44XX:
611 reg += OMAP4_GPIO_DATAOUT;
612 break;
613 #endif
614 default:
615 return -EINVAL;
616 }
617
618 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
619 }
620
621 #define MOD_REG_BIT(reg, bit_mask, set) \
622 do { \
623 int l = __raw_readl(base + reg); \
624 if (set) l |= bit_mask; \
625 else l &= ~bit_mask; \
626 __raw_writel(l, base + reg); \
627 } while(0)
628
629 /**
630 * _set_gpio_debounce - low level gpio debounce time
631 * @bank: the gpio bank we're acting upon
632 * @gpio: the gpio number on this @gpio
633 * @debounce: debounce time to use
634 *
635 * OMAP's debounce time is in 31us steps so we need
636 * to convert and round up to the closest unit.
637 */
638 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
639 unsigned debounce)
640 {
641 void __iomem *reg = bank->base;
642 u32 val;
643 u32 l;
644
645 if (debounce < 32)
646 debounce = 0x01;
647 else if (debounce > 7936)
648 debounce = 0xff;
649 else
650 debounce = (debounce / 0x1f) - 1;
651
652 l = 1 << get_gpio_index(gpio);
653
654 if (cpu_is_omap44xx())
655 reg += OMAP4_GPIO_DEBOUNCINGTIME;
656 else
657 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
658
659 __raw_writel(debounce, reg);
660
661 reg = bank->base;
662 if (cpu_is_omap44xx())
663 reg += OMAP4_GPIO_DEBOUNCENABLE;
664 else
665 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
666
667 val = __raw_readl(reg);
668
669 if (debounce) {
670 val |= l;
671 if (cpu_is_omap34xx() || cpu_is_omap44xx())
672 clk_enable(bank->dbck);
673 } else {
674 val &= ~l;
675 if (cpu_is_omap34xx() || cpu_is_omap44xx())
676 clk_disable(bank->dbck);
677 }
678 bank->dbck_enable_mask = val;
679
680 __raw_writel(val, reg);
681 }
682
683 #ifdef CONFIG_ARCH_OMAP2PLUS
684 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
685 int trigger)
686 {
687 void __iomem *base = bank->base;
688 u32 gpio_bit = 1 << gpio;
689 u32 val;
690
691 if (cpu_is_omap44xx()) {
692 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
693 trigger & IRQ_TYPE_LEVEL_LOW);
694 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
695 trigger & IRQ_TYPE_LEVEL_HIGH);
696 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
697 trigger & IRQ_TYPE_EDGE_RISING);
698 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
699 trigger & IRQ_TYPE_EDGE_FALLING);
700 } else {
701 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
702 trigger & IRQ_TYPE_LEVEL_LOW);
703 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
704 trigger & IRQ_TYPE_LEVEL_HIGH);
705 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
706 trigger & IRQ_TYPE_EDGE_RISING);
707 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
708 trigger & IRQ_TYPE_EDGE_FALLING);
709 }
710 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
711 if (cpu_is_omap44xx()) {
712 if (trigger != 0)
713 __raw_writel(1 << gpio, bank->base+
714 OMAP4_GPIO_IRQWAKEN0);
715 else {
716 val = __raw_readl(bank->base +
717 OMAP4_GPIO_IRQWAKEN0);
718 __raw_writel(val & (~(1 << gpio)), bank->base +
719 OMAP4_GPIO_IRQWAKEN0);
720 }
721 } else {
722 /*
723 * GPIO wakeup request can only be generated on edge
724 * transitions
725 */
726 if (trigger & IRQ_TYPE_EDGE_BOTH)
727 __raw_writel(1 << gpio, bank->base
728 + OMAP24XX_GPIO_SETWKUENA);
729 else
730 __raw_writel(1 << gpio, bank->base
731 + OMAP24XX_GPIO_CLEARWKUENA);
732 }
733 }
734 /* This part needs to be executed always for OMAP34xx */
735 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
736 /*
737 * Log the edge gpio and manually trigger the IRQ
738 * after resume if the input level changes
739 * to avoid irq lost during PER RET/OFF mode
740 * Applies for omap2 non-wakeup gpio and all omap3 gpios
741 */
742 if (trigger & IRQ_TYPE_EDGE_BOTH)
743 bank->enabled_non_wakeup_gpios |= gpio_bit;
744 else
745 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
746 }
747
748 if (cpu_is_omap44xx()) {
749 bank->level_mask =
750 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
751 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
752 } else {
753 bank->level_mask =
754 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
755 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
756 }
757 }
758 #endif
759
760 #ifdef CONFIG_ARCH_OMAP1
761 /*
762 * This only applies to chips that can't do both rising and falling edge
763 * detection at once. For all other chips, this function is a noop.
764 */
765 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
766 {
767 void __iomem *reg = bank->base;
768 u32 l = 0;
769
770 switch (bank->method) {
771 case METHOD_MPUIO:
772 reg += OMAP_MPUIO_GPIO_INT_EDGE;
773 break;
774 #ifdef CONFIG_ARCH_OMAP15XX
775 case METHOD_GPIO_1510:
776 reg += OMAP1510_GPIO_INT_CONTROL;
777 break;
778 #endif
779 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
780 case METHOD_GPIO_7XX:
781 reg += OMAP7XX_GPIO_INT_CONTROL;
782 break;
783 #endif
784 default:
785 return;
786 }
787
788 l = __raw_readl(reg);
789 if ((l >> gpio) & 1)
790 l &= ~(1 << gpio);
791 else
792 l |= 1 << gpio;
793
794 __raw_writel(l, reg);
795 }
796 #endif
797
798 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
799 {
800 void __iomem *reg = bank->base;
801 u32 l = 0;
802
803 switch (bank->method) {
804 #ifdef CONFIG_ARCH_OMAP1
805 case METHOD_MPUIO:
806 reg += OMAP_MPUIO_GPIO_INT_EDGE;
807 l = __raw_readl(reg);
808 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
809 bank->toggle_mask |= 1 << gpio;
810 if (trigger & IRQ_TYPE_EDGE_RISING)
811 l |= 1 << gpio;
812 else if (trigger & IRQ_TYPE_EDGE_FALLING)
813 l &= ~(1 << gpio);
814 else
815 goto bad;
816 break;
817 #endif
818 #ifdef CONFIG_ARCH_OMAP15XX
819 case METHOD_GPIO_1510:
820 reg += OMAP1510_GPIO_INT_CONTROL;
821 l = __raw_readl(reg);
822 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
823 bank->toggle_mask |= 1 << gpio;
824 if (trigger & IRQ_TYPE_EDGE_RISING)
825 l |= 1 << gpio;
826 else if (trigger & IRQ_TYPE_EDGE_FALLING)
827 l &= ~(1 << gpio);
828 else
829 goto bad;
830 break;
831 #endif
832 #ifdef CONFIG_ARCH_OMAP16XX
833 case METHOD_GPIO_1610:
834 if (gpio & 0x08)
835 reg += OMAP1610_GPIO_EDGE_CTRL2;
836 else
837 reg += OMAP1610_GPIO_EDGE_CTRL1;
838 gpio &= 0x07;
839 l = __raw_readl(reg);
840 l &= ~(3 << (gpio << 1));
841 if (trigger & IRQ_TYPE_EDGE_RISING)
842 l |= 2 << (gpio << 1);
843 if (trigger & IRQ_TYPE_EDGE_FALLING)
844 l |= 1 << (gpio << 1);
845 if (trigger)
846 /* Enable wake-up during idle for dynamic tick */
847 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
848 else
849 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
850 break;
851 #endif
852 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
853 case METHOD_GPIO_7XX:
854 reg += OMAP7XX_GPIO_INT_CONTROL;
855 l = __raw_readl(reg);
856 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
857 bank->toggle_mask |= 1 << gpio;
858 if (trigger & IRQ_TYPE_EDGE_RISING)
859 l |= 1 << gpio;
860 else if (trigger & IRQ_TYPE_EDGE_FALLING)
861 l &= ~(1 << gpio);
862 else
863 goto bad;
864 break;
865 #endif
866 #ifdef CONFIG_ARCH_OMAP2PLUS
867 case METHOD_GPIO_24XX:
868 case METHOD_GPIO_44XX:
869 set_24xx_gpio_triggering(bank, gpio, trigger);
870 break;
871 #endif
872 default:
873 goto bad;
874 }
875 __raw_writel(l, reg);
876 return 0;
877 bad:
878 return -EINVAL;
879 }
880
881 static int gpio_irq_type(unsigned irq, unsigned type)
882 {
883 struct gpio_bank *bank;
884 unsigned gpio;
885 int retval;
886 unsigned long flags;
887
888 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
889 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
890 else
891 gpio = irq - IH_GPIO_BASE;
892
893 if (check_gpio(gpio) < 0)
894 return -EINVAL;
895
896 if (type & ~IRQ_TYPE_SENSE_MASK)
897 return -EINVAL;
898
899 /* OMAP1 allows only only edge triggering */
900 if (!cpu_class_is_omap2()
901 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
902 return -EINVAL;
903
904 bank = get_irq_chip_data(irq);
905 spin_lock_irqsave(&bank->lock, flags);
906 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
907 if (retval == 0) {
908 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
909 irq_desc[irq].status |= type;
910 }
911 spin_unlock_irqrestore(&bank->lock, flags);
912
913 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
914 __set_irq_handler_unlocked(irq, handle_level_irq);
915 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
916 __set_irq_handler_unlocked(irq, handle_edge_irq);
917
918 return retval;
919 }
920
921 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
922 {
923 void __iomem *reg = bank->base;
924
925 switch (bank->method) {
926 #ifdef CONFIG_ARCH_OMAP1
927 case METHOD_MPUIO:
928 /* MPUIO irqstatus is reset by reading the status register,
929 * so do nothing here */
930 return;
931 #endif
932 #ifdef CONFIG_ARCH_OMAP15XX
933 case METHOD_GPIO_1510:
934 reg += OMAP1510_GPIO_INT_STATUS;
935 break;
936 #endif
937 #ifdef CONFIG_ARCH_OMAP16XX
938 case METHOD_GPIO_1610:
939 reg += OMAP1610_GPIO_IRQSTATUS1;
940 break;
941 #endif
942 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
943 case METHOD_GPIO_7XX:
944 reg += OMAP7XX_GPIO_INT_STATUS;
945 break;
946 #endif
947 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
948 case METHOD_GPIO_24XX:
949 reg += OMAP24XX_GPIO_IRQSTATUS1;
950 break;
951 #endif
952 #if defined(CONFIG_ARCH_OMAP4)
953 case METHOD_GPIO_44XX:
954 reg += OMAP4_GPIO_IRQSTATUS0;
955 break;
956 #endif
957 default:
958 WARN_ON(1);
959 return;
960 }
961 __raw_writel(gpio_mask, reg);
962
963 /* Workaround for clearing DSP GPIO interrupts to allow retention */
964 if (cpu_is_omap24xx() || cpu_is_omap34xx())
965 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
966 else if (cpu_is_omap44xx())
967 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
968
969 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
970 __raw_writel(gpio_mask, reg);
971
972 /* Flush posted write for the irq status to avoid spurious interrupts */
973 __raw_readl(reg);
974 }
975 }
976
977 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
978 {
979 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
980 }
981
982 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
983 {
984 void __iomem *reg = bank->base;
985 int inv = 0;
986 u32 l;
987 u32 mask;
988
989 switch (bank->method) {
990 #ifdef CONFIG_ARCH_OMAP1
991 case METHOD_MPUIO:
992 reg += OMAP_MPUIO_GPIO_MASKIT;
993 mask = 0xffff;
994 inv = 1;
995 break;
996 #endif
997 #ifdef CONFIG_ARCH_OMAP15XX
998 case METHOD_GPIO_1510:
999 reg += OMAP1510_GPIO_INT_MASK;
1000 mask = 0xffff;
1001 inv = 1;
1002 break;
1003 #endif
1004 #ifdef CONFIG_ARCH_OMAP16XX
1005 case METHOD_GPIO_1610:
1006 reg += OMAP1610_GPIO_IRQENABLE1;
1007 mask = 0xffff;
1008 break;
1009 #endif
1010 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1011 case METHOD_GPIO_7XX:
1012 reg += OMAP7XX_GPIO_INT_MASK;
1013 mask = 0xffffffff;
1014 inv = 1;
1015 break;
1016 #endif
1017 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1018 case METHOD_GPIO_24XX:
1019 reg += OMAP24XX_GPIO_IRQENABLE1;
1020 mask = 0xffffffff;
1021 break;
1022 #endif
1023 #if defined(CONFIG_ARCH_OMAP4)
1024 case METHOD_GPIO_44XX:
1025 reg += OMAP4_GPIO_IRQSTATUSSET0;
1026 mask = 0xffffffff;
1027 break;
1028 #endif
1029 default:
1030 WARN_ON(1);
1031 return 0;
1032 }
1033
1034 l = __raw_readl(reg);
1035 if (inv)
1036 l = ~l;
1037 l &= mask;
1038 return l;
1039 }
1040
1041 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1042 {
1043 void __iomem *reg = bank->base;
1044 u32 l;
1045
1046 switch (bank->method) {
1047 #ifdef CONFIG_ARCH_OMAP1
1048 case METHOD_MPUIO:
1049 reg += OMAP_MPUIO_GPIO_MASKIT;
1050 l = __raw_readl(reg);
1051 if (enable)
1052 l &= ~(gpio_mask);
1053 else
1054 l |= gpio_mask;
1055 break;
1056 #endif
1057 #ifdef CONFIG_ARCH_OMAP15XX
1058 case METHOD_GPIO_1510:
1059 reg += OMAP1510_GPIO_INT_MASK;
1060 l = __raw_readl(reg);
1061 if (enable)
1062 l &= ~(gpio_mask);
1063 else
1064 l |= gpio_mask;
1065 break;
1066 #endif
1067 #ifdef CONFIG_ARCH_OMAP16XX
1068 case METHOD_GPIO_1610:
1069 if (enable)
1070 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1071 else
1072 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1073 l = gpio_mask;
1074 break;
1075 #endif
1076 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1077 case METHOD_GPIO_7XX:
1078 reg += OMAP7XX_GPIO_INT_MASK;
1079 l = __raw_readl(reg);
1080 if (enable)
1081 l &= ~(gpio_mask);
1082 else
1083 l |= gpio_mask;
1084 break;
1085 #endif
1086 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1087 case METHOD_GPIO_24XX:
1088 if (enable)
1089 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1090 else
1091 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1092 l = gpio_mask;
1093 break;
1094 #endif
1095 #ifdef CONFIG_ARCH_OMAP4
1096 case METHOD_GPIO_44XX:
1097 if (enable)
1098 reg += OMAP4_GPIO_IRQSTATUSSET0;
1099 else
1100 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1101 l = gpio_mask;
1102 break;
1103 #endif
1104 default:
1105 WARN_ON(1);
1106 return;
1107 }
1108 __raw_writel(l, reg);
1109 }
1110
1111 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1112 {
1113 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1114 }
1115
1116 /*
1117 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1118 * 1510 does not seem to have a wake-up register. If JTAG is connected
1119 * to the target, system will wake up always on GPIO events. While
1120 * system is running all registered GPIO interrupts need to have wake-up
1121 * enabled. When system is suspended, only selected GPIO interrupts need
1122 * to have wake-up enabled.
1123 */
1124 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1125 {
1126 unsigned long uninitialized_var(flags);
1127
1128 switch (bank->method) {
1129 #ifdef CONFIG_ARCH_OMAP16XX
1130 case METHOD_MPUIO:
1131 case METHOD_GPIO_1610:
1132 spin_lock_irqsave(&bank->lock, flags);
1133 if (enable)
1134 bank->suspend_wakeup |= (1 << gpio);
1135 else
1136 bank->suspend_wakeup &= ~(1 << gpio);
1137 spin_unlock_irqrestore(&bank->lock, flags);
1138 return 0;
1139 #endif
1140 #ifdef CONFIG_ARCH_OMAP2PLUS
1141 case METHOD_GPIO_24XX:
1142 case METHOD_GPIO_44XX:
1143 if (bank->non_wakeup_gpios & (1 << gpio)) {
1144 printk(KERN_ERR "Unable to modify wakeup on "
1145 "non-wakeup GPIO%d\n",
1146 (bank - gpio_bank) * 32 + gpio);
1147 return -EINVAL;
1148 }
1149 spin_lock_irqsave(&bank->lock, flags);
1150 if (enable)
1151 bank->suspend_wakeup |= (1 << gpio);
1152 else
1153 bank->suspend_wakeup &= ~(1 << gpio);
1154 spin_unlock_irqrestore(&bank->lock, flags);
1155 return 0;
1156 #endif
1157 default:
1158 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1159 bank->method);
1160 return -EINVAL;
1161 }
1162 }
1163
1164 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1165 {
1166 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1167 _set_gpio_irqenable(bank, gpio, 0);
1168 _clear_gpio_irqstatus(bank, gpio);
1169 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1170 }
1171
1172 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1173 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1174 {
1175 unsigned int gpio = irq - IH_GPIO_BASE;
1176 struct gpio_bank *bank;
1177 int retval;
1178
1179 if (check_gpio(gpio) < 0)
1180 return -ENODEV;
1181 bank = get_irq_chip_data(irq);
1182 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1183
1184 return retval;
1185 }
1186
1187 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1188 {
1189 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1190 unsigned long flags;
1191
1192 spin_lock_irqsave(&bank->lock, flags);
1193
1194 /* Set trigger to none. You need to enable the desired trigger with
1195 * request_irq() or set_irq_type().
1196 */
1197 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1198
1199 #ifdef CONFIG_ARCH_OMAP15XX
1200 if (bank->method == METHOD_GPIO_1510) {
1201 void __iomem *reg;
1202
1203 /* Claim the pin for MPU */
1204 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1205 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1206 }
1207 #endif
1208 if (!cpu_class_is_omap1()) {
1209 if (!bank->mod_usage) {
1210 void __iomem *reg = bank->base;
1211 u32 ctrl;
1212
1213 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1214 reg += OMAP24XX_GPIO_CTRL;
1215 else if (cpu_is_omap44xx())
1216 reg += OMAP4_GPIO_CTRL;
1217 ctrl = __raw_readl(reg);
1218 /* Module is enabled, clocks are not gated */
1219 ctrl &= 0xFFFFFFFE;
1220 __raw_writel(ctrl, reg);
1221 }
1222 bank->mod_usage |= 1 << offset;
1223 }
1224 spin_unlock_irqrestore(&bank->lock, flags);
1225
1226 return 0;
1227 }
1228
1229 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1230 {
1231 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1232 unsigned long flags;
1233
1234 spin_lock_irqsave(&bank->lock, flags);
1235 #ifdef CONFIG_ARCH_OMAP16XX
1236 if (bank->method == METHOD_GPIO_1610) {
1237 /* Disable wake-up during idle for dynamic tick */
1238 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1239 __raw_writel(1 << offset, reg);
1240 }
1241 #endif
1242 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1243 if (bank->method == METHOD_GPIO_24XX) {
1244 /* Disable wake-up during idle for dynamic tick */
1245 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1246 __raw_writel(1 << offset, reg);
1247 }
1248 #endif
1249 #ifdef CONFIG_ARCH_OMAP4
1250 if (bank->method == METHOD_GPIO_44XX) {
1251 /* Disable wake-up during idle for dynamic tick */
1252 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1253 __raw_writel(1 << offset, reg);
1254 }
1255 #endif
1256 if (!cpu_class_is_omap1()) {
1257 bank->mod_usage &= ~(1 << offset);
1258 if (!bank->mod_usage) {
1259 void __iomem *reg = bank->base;
1260 u32 ctrl;
1261
1262 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1263 reg += OMAP24XX_GPIO_CTRL;
1264 else if (cpu_is_omap44xx())
1265 reg += OMAP4_GPIO_CTRL;
1266 ctrl = __raw_readl(reg);
1267 /* Module is disabled, clocks are gated */
1268 ctrl |= 1;
1269 __raw_writel(ctrl, reg);
1270 }
1271 }
1272 _reset_gpio(bank, bank->chip.base + offset);
1273 spin_unlock_irqrestore(&bank->lock, flags);
1274 }
1275
1276 /*
1277 * We need to unmask the GPIO bank interrupt as soon as possible to
1278 * avoid missing GPIO interrupts for other lines in the bank.
1279 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1280 * in the bank to avoid missing nested interrupts for a GPIO line.
1281 * If we wait to unmask individual GPIO lines in the bank after the
1282 * line's interrupt handler has been run, we may miss some nested
1283 * interrupts.
1284 */
1285 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1286 {
1287 void __iomem *isr_reg = NULL;
1288 u32 isr;
1289 unsigned int gpio_irq, gpio_index;
1290 struct gpio_bank *bank;
1291 u32 retrigger = 0;
1292 int unmasked = 0;
1293
1294 desc->chip->ack(irq);
1295
1296 bank = get_irq_data(irq);
1297 #ifdef CONFIG_ARCH_OMAP1
1298 if (bank->method == METHOD_MPUIO)
1299 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1300 #endif
1301 #ifdef CONFIG_ARCH_OMAP15XX
1302 if (bank->method == METHOD_GPIO_1510)
1303 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1304 #endif
1305 #if defined(CONFIG_ARCH_OMAP16XX)
1306 if (bank->method == METHOD_GPIO_1610)
1307 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1308 #endif
1309 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1310 if (bank->method == METHOD_GPIO_7XX)
1311 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1312 #endif
1313 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1314 if (bank->method == METHOD_GPIO_24XX)
1315 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1316 #endif
1317 #if defined(CONFIG_ARCH_OMAP4)
1318 if (bank->method == METHOD_GPIO_44XX)
1319 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1320 #endif
1321 while(1) {
1322 u32 isr_saved, level_mask = 0;
1323 u32 enabled;
1324
1325 enabled = _get_gpio_irqbank_mask(bank);
1326 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1327
1328 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1329 isr &= 0x0000ffff;
1330
1331 if (cpu_class_is_omap2()) {
1332 level_mask = bank->level_mask & enabled;
1333 }
1334
1335 /* clear edge sensitive interrupts before handler(s) are
1336 called so that we don't miss any interrupt occurred while
1337 executing them */
1338 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1339 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1340 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1341
1342 /* if there is only edge sensitive GPIO pin interrupts
1343 configured, we could unmask GPIO bank interrupt immediately */
1344 if (!level_mask && !unmasked) {
1345 unmasked = 1;
1346 desc->chip->unmask(irq);
1347 }
1348
1349 isr |= retrigger;
1350 retrigger = 0;
1351 if (!isr)
1352 break;
1353
1354 gpio_irq = bank->virtual_irq_start;
1355 for (; isr != 0; isr >>= 1, gpio_irq++) {
1356 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1357
1358 if (!(isr & 1))
1359 continue;
1360
1361 #ifdef CONFIG_ARCH_OMAP1
1362 /*
1363 * Some chips can't respond to both rising and falling
1364 * at the same time. If this irq was requested with
1365 * both flags, we need to flip the ICR data for the IRQ
1366 * to respond to the IRQ for the opposite direction.
1367 * This will be indicated in the bank toggle_mask.
1368 */
1369 if (bank->toggle_mask & (1 << gpio_index))
1370 _toggle_gpio_edge_triggering(bank, gpio_index);
1371 #endif
1372
1373 generic_handle_irq(gpio_irq);
1374 }
1375 }
1376 /* if bank has any level sensitive GPIO pin interrupt
1377 configured, we must unmask the bank interrupt only after
1378 handler(s) are executed in order to avoid spurious bank
1379 interrupt */
1380 if (!unmasked)
1381 desc->chip->unmask(irq);
1382
1383 }
1384
1385 static void gpio_irq_shutdown(unsigned int irq)
1386 {
1387 unsigned int gpio = irq - IH_GPIO_BASE;
1388 struct gpio_bank *bank = get_irq_chip_data(irq);
1389
1390 _reset_gpio(bank, gpio);
1391 }
1392
1393 static void gpio_ack_irq(unsigned int irq)
1394 {
1395 unsigned int gpio = irq - IH_GPIO_BASE;
1396 struct gpio_bank *bank = get_irq_chip_data(irq);
1397
1398 _clear_gpio_irqstatus(bank, gpio);
1399 }
1400
1401 static void gpio_mask_irq(unsigned int irq)
1402 {
1403 unsigned int gpio = irq - IH_GPIO_BASE;
1404 struct gpio_bank *bank = get_irq_chip_data(irq);
1405
1406 _set_gpio_irqenable(bank, gpio, 0);
1407 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1408 }
1409
1410 static void gpio_unmask_irq(unsigned int irq)
1411 {
1412 unsigned int gpio = irq - IH_GPIO_BASE;
1413 struct gpio_bank *bank = get_irq_chip_data(irq);
1414 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1415 struct irq_desc *desc = irq_to_desc(irq);
1416 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1417
1418 if (trigger)
1419 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1420
1421 /* For level-triggered GPIOs, the clearing must be done after
1422 * the HW source is cleared, thus after the handler has run */
1423 if (bank->level_mask & irq_mask) {
1424 _set_gpio_irqenable(bank, gpio, 0);
1425 _clear_gpio_irqstatus(bank, gpio);
1426 }
1427
1428 _set_gpio_irqenable(bank, gpio, 1);
1429 }
1430
1431 static struct irq_chip gpio_irq_chip = {
1432 .name = "GPIO",
1433 .shutdown = gpio_irq_shutdown,
1434 .ack = gpio_ack_irq,
1435 .mask = gpio_mask_irq,
1436 .unmask = gpio_unmask_irq,
1437 .set_type = gpio_irq_type,
1438 .set_wake = gpio_wake_enable,
1439 };
1440
1441 /*---------------------------------------------------------------------*/
1442
1443 #ifdef CONFIG_ARCH_OMAP1
1444
1445 /* MPUIO uses the always-on 32k clock */
1446
1447 static void mpuio_ack_irq(unsigned int irq)
1448 {
1449 /* The ISR is reset automatically, so do nothing here. */
1450 }
1451
1452 static void mpuio_mask_irq(unsigned int irq)
1453 {
1454 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1455 struct gpio_bank *bank = get_irq_chip_data(irq);
1456
1457 _set_gpio_irqenable(bank, gpio, 0);
1458 }
1459
1460 static void mpuio_unmask_irq(unsigned int irq)
1461 {
1462 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1463 struct gpio_bank *bank = get_irq_chip_data(irq);
1464
1465 _set_gpio_irqenable(bank, gpio, 1);
1466 }
1467
1468 static struct irq_chip mpuio_irq_chip = {
1469 .name = "MPUIO",
1470 .ack = mpuio_ack_irq,
1471 .mask = mpuio_mask_irq,
1472 .unmask = mpuio_unmask_irq,
1473 .set_type = gpio_irq_type,
1474 #ifdef CONFIG_ARCH_OMAP16XX
1475 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1476 .set_wake = gpio_wake_enable,
1477 #endif
1478 };
1479
1480
1481 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1482
1483
1484 #ifdef CONFIG_ARCH_OMAP16XX
1485
1486 #include <linux/platform_device.h>
1487
1488 static int omap_mpuio_suspend_noirq(struct device *dev)
1489 {
1490 struct platform_device *pdev = to_platform_device(dev);
1491 struct gpio_bank *bank = platform_get_drvdata(pdev);
1492 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1493 unsigned long flags;
1494
1495 spin_lock_irqsave(&bank->lock, flags);
1496 bank->saved_wakeup = __raw_readl(mask_reg);
1497 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1498 spin_unlock_irqrestore(&bank->lock, flags);
1499
1500 return 0;
1501 }
1502
1503 static int omap_mpuio_resume_noirq(struct device *dev)
1504 {
1505 struct platform_device *pdev = to_platform_device(dev);
1506 struct gpio_bank *bank = platform_get_drvdata(pdev);
1507 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1508 unsigned long flags;
1509
1510 spin_lock_irqsave(&bank->lock, flags);
1511 __raw_writel(bank->saved_wakeup, mask_reg);
1512 spin_unlock_irqrestore(&bank->lock, flags);
1513
1514 return 0;
1515 }
1516
1517 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1518 .suspend_noirq = omap_mpuio_suspend_noirq,
1519 .resume_noirq = omap_mpuio_resume_noirq,
1520 };
1521
1522 /* use platform_driver for this, now that there's no longer any
1523 * point to sys_device (other than not disturbing old code).
1524 */
1525 static struct platform_driver omap_mpuio_driver = {
1526 .driver = {
1527 .name = "mpuio",
1528 .pm = &omap_mpuio_dev_pm_ops,
1529 },
1530 };
1531
1532 static struct platform_device omap_mpuio_device = {
1533 .name = "mpuio",
1534 .id = -1,
1535 .dev = {
1536 .driver = &omap_mpuio_driver.driver,
1537 }
1538 /* could list the /proc/iomem resources */
1539 };
1540
1541 static inline void mpuio_init(void)
1542 {
1543 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1544
1545 if (platform_driver_register(&omap_mpuio_driver) == 0)
1546 (void) platform_device_register(&omap_mpuio_device);
1547 }
1548
1549 #else
1550 static inline void mpuio_init(void) {}
1551 #endif /* 16xx */
1552
1553 #else
1554
1555 extern struct irq_chip mpuio_irq_chip;
1556
1557 #define bank_is_mpuio(bank) 0
1558 static inline void mpuio_init(void) {}
1559
1560 #endif
1561
1562 /*---------------------------------------------------------------------*/
1563
1564 /* REVISIT these are stupid implementations! replace by ones that
1565 * don't switch on METHOD_* and which mostly avoid spinlocks
1566 */
1567
1568 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1569 {
1570 struct gpio_bank *bank;
1571 unsigned long flags;
1572
1573 bank = container_of(chip, struct gpio_bank, chip);
1574 spin_lock_irqsave(&bank->lock, flags);
1575 _set_gpio_direction(bank, offset, 1);
1576 spin_unlock_irqrestore(&bank->lock, flags);
1577 return 0;
1578 }
1579
1580 static int gpio_is_input(struct gpio_bank *bank, int mask)
1581 {
1582 void __iomem *reg = bank->base;
1583
1584 switch (bank->method) {
1585 case METHOD_MPUIO:
1586 reg += OMAP_MPUIO_IO_CNTL;
1587 break;
1588 case METHOD_GPIO_1510:
1589 reg += OMAP1510_GPIO_DIR_CONTROL;
1590 break;
1591 case METHOD_GPIO_1610:
1592 reg += OMAP1610_GPIO_DIRECTION;
1593 break;
1594 case METHOD_GPIO_7XX:
1595 reg += OMAP7XX_GPIO_DIR_CONTROL;
1596 break;
1597 case METHOD_GPIO_24XX:
1598 reg += OMAP24XX_GPIO_OE;
1599 break;
1600 case METHOD_GPIO_44XX:
1601 reg += OMAP4_GPIO_OE;
1602 break;
1603 default:
1604 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1605 return -EINVAL;
1606 }
1607 return __raw_readl(reg) & mask;
1608 }
1609
1610 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1611 {
1612 struct gpio_bank *bank;
1613 void __iomem *reg;
1614 int gpio;
1615 u32 mask;
1616
1617 gpio = chip->base + offset;
1618 bank = get_gpio_bank(gpio);
1619 reg = bank->base;
1620 mask = 1 << get_gpio_index(gpio);
1621
1622 if (gpio_is_input(bank, mask))
1623 return _get_gpio_datain(bank, gpio);
1624 else
1625 return _get_gpio_dataout(bank, gpio);
1626 }
1627
1628 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1629 {
1630 struct gpio_bank *bank;
1631 unsigned long flags;
1632
1633 bank = container_of(chip, struct gpio_bank, chip);
1634 spin_lock_irqsave(&bank->lock, flags);
1635 _set_gpio_dataout(bank, offset, value);
1636 _set_gpio_direction(bank, offset, 0);
1637 spin_unlock_irqrestore(&bank->lock, flags);
1638 return 0;
1639 }
1640
1641 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1642 unsigned debounce)
1643 {
1644 struct gpio_bank *bank;
1645 unsigned long flags;
1646
1647 bank = container_of(chip, struct gpio_bank, chip);
1648 spin_lock_irqsave(&bank->lock, flags);
1649 _set_gpio_debounce(bank, offset, debounce);
1650 spin_unlock_irqrestore(&bank->lock, flags);
1651
1652 return 0;
1653 }
1654
1655 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1656 {
1657 struct gpio_bank *bank;
1658 unsigned long flags;
1659
1660 bank = container_of(chip, struct gpio_bank, chip);
1661 spin_lock_irqsave(&bank->lock, flags);
1662 _set_gpio_dataout(bank, offset, value);
1663 spin_unlock_irqrestore(&bank->lock, flags);
1664 }
1665
1666 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1667 {
1668 struct gpio_bank *bank;
1669
1670 bank = container_of(chip, struct gpio_bank, chip);
1671 return bank->virtual_irq_start + offset;
1672 }
1673
1674 /*---------------------------------------------------------------------*/
1675
1676 static int initialized;
1677 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1678 static struct clk * gpio_ick;
1679 #endif
1680
1681 #if defined(CONFIG_ARCH_OMAP2)
1682 static struct clk * gpio_fck;
1683 #endif
1684
1685 #if defined(CONFIG_ARCH_OMAP2430)
1686 static struct clk * gpio5_ick;
1687 static struct clk * gpio5_fck;
1688 #endif
1689
1690 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1691 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1692 #endif
1693
1694 static void __init omap_gpio_show_rev(void)
1695 {
1696 u32 rev;
1697
1698 if (cpu_is_omap16xx())
1699 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1700 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1701 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1702 else if (cpu_is_omap44xx())
1703 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1704 else
1705 return;
1706
1707 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1708 (rev >> 4) & 0x0f, rev & 0x0f);
1709 }
1710
1711 /* This lock class tells lockdep that GPIO irqs are in a different
1712 * category than their parents, so it won't report false recursion.
1713 */
1714 static struct lock_class_key gpio_lock_class;
1715
1716 static int __init _omap_gpio_init(void)
1717 {
1718 int i;
1719 int gpio = 0;
1720 struct gpio_bank *bank;
1721 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1722 char clk_name[11];
1723
1724 initialized = 1;
1725
1726 #if defined(CONFIG_ARCH_OMAP1)
1727 if (cpu_is_omap15xx()) {
1728 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1729 if (IS_ERR(gpio_ick))
1730 printk("Could not get arm_gpio_ck\n");
1731 else
1732 clk_enable(gpio_ick);
1733 }
1734 #endif
1735 #if defined(CONFIG_ARCH_OMAP2)
1736 if (cpu_class_is_omap2()) {
1737 gpio_ick = clk_get(NULL, "gpios_ick");
1738 if (IS_ERR(gpio_ick))
1739 printk("Could not get gpios_ick\n");
1740 else
1741 clk_enable(gpio_ick);
1742 gpio_fck = clk_get(NULL, "gpios_fck");
1743 if (IS_ERR(gpio_fck))
1744 printk("Could not get gpios_fck\n");
1745 else
1746 clk_enable(gpio_fck);
1747
1748 /*
1749 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1750 */
1751 #if defined(CONFIG_ARCH_OMAP2430)
1752 if (cpu_is_omap2430()) {
1753 gpio5_ick = clk_get(NULL, "gpio5_ick");
1754 if (IS_ERR(gpio5_ick))
1755 printk("Could not get gpio5_ick\n");
1756 else
1757 clk_enable(gpio5_ick);
1758 gpio5_fck = clk_get(NULL, "gpio5_fck");
1759 if (IS_ERR(gpio5_fck))
1760 printk("Could not get gpio5_fck\n");
1761 else
1762 clk_enable(gpio5_fck);
1763 }
1764 #endif
1765 }
1766 #endif
1767
1768 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1769 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1770 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1771 sprintf(clk_name, "gpio%d_ick", i + 1);
1772 gpio_iclks[i] = clk_get(NULL, clk_name);
1773 if (IS_ERR(gpio_iclks[i]))
1774 printk(KERN_ERR "Could not get %s\n", clk_name);
1775 else
1776 clk_enable(gpio_iclks[i]);
1777 }
1778 }
1779 #endif
1780
1781
1782 #ifdef CONFIG_ARCH_OMAP15XX
1783 if (cpu_is_omap15xx()) {
1784 gpio_bank_count = 2;
1785 gpio_bank = gpio_bank_1510;
1786 bank_size = SZ_2K;
1787 }
1788 #endif
1789 #if defined(CONFIG_ARCH_OMAP16XX)
1790 if (cpu_is_omap16xx()) {
1791 gpio_bank_count = 5;
1792 gpio_bank = gpio_bank_1610;
1793 bank_size = SZ_2K;
1794 }
1795 #endif
1796 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1797 if (cpu_is_omap7xx()) {
1798 gpio_bank_count = 7;
1799 gpio_bank = gpio_bank_7xx;
1800 bank_size = SZ_2K;
1801 }
1802 #endif
1803 #ifdef CONFIG_ARCH_OMAP2
1804 if (cpu_is_omap242x()) {
1805 gpio_bank_count = 4;
1806 gpio_bank = gpio_bank_242x;
1807 }
1808 if (cpu_is_omap243x()) {
1809 gpio_bank_count = 5;
1810 gpio_bank = gpio_bank_243x;
1811 }
1812 #endif
1813 #ifdef CONFIG_ARCH_OMAP3
1814 if (cpu_is_omap34xx()) {
1815 gpio_bank_count = OMAP34XX_NR_GPIOS;
1816 gpio_bank = gpio_bank_34xx;
1817 }
1818 #endif
1819 #ifdef CONFIG_ARCH_OMAP4
1820 if (cpu_is_omap44xx()) {
1821 gpio_bank_count = OMAP34XX_NR_GPIOS;
1822 gpio_bank = gpio_bank_44xx;
1823 }
1824 #endif
1825 for (i = 0; i < gpio_bank_count; i++) {
1826 int j, gpio_count = 16;
1827
1828 bank = &gpio_bank[i];
1829 spin_lock_init(&bank->lock);
1830
1831 /* Static mapping, never released */
1832 bank->base = ioremap(bank->pbase, bank_size);
1833 if (!bank->base) {
1834 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1835 continue;
1836 }
1837
1838 if (bank_is_mpuio(bank))
1839 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1840 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1841 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1842 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1843 }
1844 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1845 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1846 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1847 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1848 }
1849 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1850 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1851 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1852
1853 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1854 }
1855
1856 #ifdef CONFIG_ARCH_OMAP2PLUS
1857 if ((bank->method == METHOD_GPIO_24XX) ||
1858 (bank->method == METHOD_GPIO_44XX)) {
1859 static const u32 non_wakeup_gpios[] = {
1860 0xe203ffc0, 0x08700040
1861 };
1862
1863 if (cpu_is_omap44xx()) {
1864 __raw_writel(0xffffffff, bank->base +
1865 OMAP4_GPIO_IRQSTATUSCLR0);
1866 __raw_writew(0x0015, bank->base +
1867 OMAP4_GPIO_SYSCONFIG);
1868 __raw_writel(0x00000000, bank->base +
1869 OMAP4_GPIO_DEBOUNCENABLE);
1870 /*
1871 * Initialize interface clock ungated,
1872 * module enabled
1873 */
1874 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1875 } else {
1876 __raw_writel(0x00000000, bank->base +
1877 OMAP24XX_GPIO_IRQENABLE1);
1878 __raw_writel(0xffffffff, bank->base +
1879 OMAP24XX_GPIO_IRQSTATUS1);
1880 __raw_writew(0x0015, bank->base +
1881 OMAP24XX_GPIO_SYSCONFIG);
1882 __raw_writel(0x00000000, bank->base +
1883 OMAP24XX_GPIO_DEBOUNCE_EN);
1884
1885 /*
1886 * Initialize interface clock ungated,
1887 * module enabled
1888 */
1889 __raw_writel(0, bank->base +
1890 OMAP24XX_GPIO_CTRL);
1891 }
1892 if (cpu_is_omap24xx() &&
1893 i < ARRAY_SIZE(non_wakeup_gpios))
1894 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1895 gpio_count = 32;
1896 }
1897 #endif
1898
1899 bank->mod_usage = 0;
1900 /* REVISIT eventually switch from OMAP-specific gpio structs
1901 * over to the generic ones
1902 */
1903 bank->chip.request = omap_gpio_request;
1904 bank->chip.free = omap_gpio_free;
1905 bank->chip.direction_input = gpio_input;
1906 bank->chip.get = gpio_get;
1907 bank->chip.direction_output = gpio_output;
1908 bank->chip.set_debounce = gpio_debounce;
1909 bank->chip.set = gpio_set;
1910 bank->chip.to_irq = gpio_2irq;
1911 if (bank_is_mpuio(bank)) {
1912 bank->chip.label = "mpuio";
1913 #ifdef CONFIG_ARCH_OMAP16XX
1914 bank->chip.dev = &omap_mpuio_device.dev;
1915 #endif
1916 bank->chip.base = OMAP_MPUIO(0);
1917 } else {
1918 bank->chip.label = "gpio";
1919 bank->chip.base = gpio;
1920 gpio += gpio_count;
1921 }
1922 bank->chip.ngpio = gpio_count;
1923
1924 gpiochip_add(&bank->chip);
1925
1926 for (j = bank->virtual_irq_start;
1927 j < bank->virtual_irq_start + gpio_count; j++) {
1928 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1929 set_irq_chip_data(j, bank);
1930 if (bank_is_mpuio(bank))
1931 set_irq_chip(j, &mpuio_irq_chip);
1932 else
1933 set_irq_chip(j, &gpio_irq_chip);
1934 set_irq_handler(j, handle_simple_irq);
1935 set_irq_flags(j, IRQF_VALID);
1936 }
1937 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1938 set_irq_data(bank->irq, bank);
1939
1940 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1941 sprintf(clk_name, "gpio%d_dbck", i + 1);
1942 bank->dbck = clk_get(NULL, clk_name);
1943 if (IS_ERR(bank->dbck))
1944 printk(KERN_ERR "Could not get %s\n", clk_name);
1945 }
1946 }
1947
1948 /* Enable system clock for GPIO module.
1949 * The CAM_CLK_CTRL *is* really the right place. */
1950 if (cpu_is_omap16xx())
1951 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1952
1953 /* Enable autoidle for the OCP interface */
1954 if (cpu_is_omap24xx())
1955 omap_writel(1 << 0, 0x48019010);
1956 if (cpu_is_omap34xx())
1957 omap_writel(1 << 0, 0x48306814);
1958
1959 omap_gpio_show_rev();
1960
1961 return 0;
1962 }
1963
1964 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1965 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1966 {
1967 int i;
1968
1969 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1970 return 0;
1971
1972 for (i = 0; i < gpio_bank_count; i++) {
1973 struct gpio_bank *bank = &gpio_bank[i];
1974 void __iomem *wake_status;
1975 void __iomem *wake_clear;
1976 void __iomem *wake_set;
1977 unsigned long flags;
1978
1979 switch (bank->method) {
1980 #ifdef CONFIG_ARCH_OMAP16XX
1981 case METHOD_GPIO_1610:
1982 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1983 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1984 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1985 break;
1986 #endif
1987 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1988 case METHOD_GPIO_24XX:
1989 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1990 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1991 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1992 break;
1993 #endif
1994 #ifdef CONFIG_ARCH_OMAP4
1995 case METHOD_GPIO_44XX:
1996 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1997 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1998 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1999 break;
2000 #endif
2001 default:
2002 continue;
2003 }
2004
2005 spin_lock_irqsave(&bank->lock, flags);
2006 bank->saved_wakeup = __raw_readl(wake_status);
2007 __raw_writel(0xffffffff, wake_clear);
2008 __raw_writel(bank->suspend_wakeup, wake_set);
2009 spin_unlock_irqrestore(&bank->lock, flags);
2010 }
2011
2012 return 0;
2013 }
2014
2015 static int omap_gpio_resume(struct sys_device *dev)
2016 {
2017 int i;
2018
2019 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
2020 return 0;
2021
2022 for (i = 0; i < gpio_bank_count; i++) {
2023 struct gpio_bank *bank = &gpio_bank[i];
2024 void __iomem *wake_clear;
2025 void __iomem *wake_set;
2026 unsigned long flags;
2027
2028 switch (bank->method) {
2029 #ifdef CONFIG_ARCH_OMAP16XX
2030 case METHOD_GPIO_1610:
2031 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
2032 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
2033 break;
2034 #endif
2035 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
2036 case METHOD_GPIO_24XX:
2037 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
2038 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
2039 break;
2040 #endif
2041 #ifdef CONFIG_ARCH_OMAP4
2042 case METHOD_GPIO_44XX:
2043 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2044 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2045 break;
2046 #endif
2047 default:
2048 continue;
2049 }
2050
2051 spin_lock_irqsave(&bank->lock, flags);
2052 __raw_writel(0xffffffff, wake_clear);
2053 __raw_writel(bank->saved_wakeup, wake_set);
2054 spin_unlock_irqrestore(&bank->lock, flags);
2055 }
2056
2057 return 0;
2058 }
2059
2060 static struct sysdev_class omap_gpio_sysclass = {
2061 .name = "gpio",
2062 .suspend = omap_gpio_suspend,
2063 .resume = omap_gpio_resume,
2064 };
2065
2066 static struct sys_device omap_gpio_device = {
2067 .id = 0,
2068 .cls = &omap_gpio_sysclass,
2069 };
2070
2071 #endif
2072
2073 #ifdef CONFIG_ARCH_OMAP2PLUS
2074
2075 static int workaround_enabled;
2076
2077 void omap2_gpio_prepare_for_idle(int power_state)
2078 {
2079 int i, c = 0;
2080 int min = 0;
2081
2082 if (cpu_is_omap34xx())
2083 min = 1;
2084
2085 for (i = min; i < gpio_bank_count; i++) {
2086 struct gpio_bank *bank = &gpio_bank[i];
2087 u32 l1, l2;
2088 int j;
2089
2090 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
2091 clk_disable(bank->dbck);
2092
2093 if (power_state > PWRDM_POWER_OFF)
2094 continue;
2095
2096 /* If going to OFF, remove triggering for all
2097 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2098 * generated. See OMAP2420 Errata item 1.101. */
2099 if (!(bank->enabled_non_wakeup_gpios))
2100 continue;
2101
2102 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2103 bank->saved_datain = __raw_readl(bank->base +
2104 OMAP24XX_GPIO_DATAIN);
2105 l1 = __raw_readl(bank->base +
2106 OMAP24XX_GPIO_FALLINGDETECT);
2107 l2 = __raw_readl(bank->base +
2108 OMAP24XX_GPIO_RISINGDETECT);
2109 }
2110
2111 if (cpu_is_omap44xx()) {
2112 bank->saved_datain = __raw_readl(bank->base +
2113 OMAP4_GPIO_DATAIN);
2114 l1 = __raw_readl(bank->base +
2115 OMAP4_GPIO_FALLINGDETECT);
2116 l2 = __raw_readl(bank->base +
2117 OMAP4_GPIO_RISINGDETECT);
2118 }
2119
2120 bank->saved_fallingdetect = l1;
2121 bank->saved_risingdetect = l2;
2122 l1 &= ~bank->enabled_non_wakeup_gpios;
2123 l2 &= ~bank->enabled_non_wakeup_gpios;
2124
2125 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2126 __raw_writel(l1, bank->base +
2127 OMAP24XX_GPIO_FALLINGDETECT);
2128 __raw_writel(l2, bank->base +
2129 OMAP24XX_GPIO_RISINGDETECT);
2130 }
2131
2132 if (cpu_is_omap44xx()) {
2133 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2134 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2135 }
2136
2137 c++;
2138 }
2139 if (!c) {
2140 workaround_enabled = 0;
2141 return;
2142 }
2143 workaround_enabled = 1;
2144 }
2145
2146 void omap2_gpio_resume_after_idle(void)
2147 {
2148 int i;
2149 int min = 0;
2150
2151 if (cpu_is_omap34xx())
2152 min = 1;
2153 for (i = min; i < gpio_bank_count; i++) {
2154 struct gpio_bank *bank = &gpio_bank[i];
2155 u32 l, gen, gen0, gen1;
2156 int j;
2157
2158 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
2159 clk_enable(bank->dbck);
2160
2161 if (!workaround_enabled)
2162 continue;
2163
2164 if (!(bank->enabled_non_wakeup_gpios))
2165 continue;
2166
2167 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2168 __raw_writel(bank->saved_fallingdetect,
2169 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2170 __raw_writel(bank->saved_risingdetect,
2171 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2172 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2173 }
2174
2175 if (cpu_is_omap44xx()) {
2176 __raw_writel(bank->saved_fallingdetect,
2177 bank->base + OMAP4_GPIO_FALLINGDETECT);
2178 __raw_writel(bank->saved_risingdetect,
2179 bank->base + OMAP4_GPIO_RISINGDETECT);
2180 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2181 }
2182
2183 /* Check if any of the non-wakeup interrupt GPIOs have changed
2184 * state. If so, generate an IRQ by software. This is
2185 * horribly racy, but it's the best we can do to work around
2186 * this silicon bug. */
2187 l ^= bank->saved_datain;
2188 l &= bank->enabled_non_wakeup_gpios;
2189
2190 /*
2191 * No need to generate IRQs for the rising edge for gpio IRQs
2192 * configured with falling edge only; and vice versa.
2193 */
2194 gen0 = l & bank->saved_fallingdetect;
2195 gen0 &= bank->saved_datain;
2196
2197 gen1 = l & bank->saved_risingdetect;
2198 gen1 &= ~(bank->saved_datain);
2199
2200 /* FIXME: Consider GPIO IRQs with level detections properly! */
2201 gen = l & (~(bank->saved_fallingdetect) &
2202 ~(bank->saved_risingdetect));
2203 /* Consider all GPIO IRQs needed to be updated */
2204 gen |= gen0 | gen1;
2205
2206 if (gen) {
2207 u32 old0, old1;
2208
2209 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2210 old0 = __raw_readl(bank->base +
2211 OMAP24XX_GPIO_LEVELDETECT0);
2212 old1 = __raw_readl(bank->base +
2213 OMAP24XX_GPIO_LEVELDETECT1);
2214 __raw_writel(old0 | gen, bank->base +
2215 OMAP24XX_GPIO_LEVELDETECT0);
2216 __raw_writel(old1 | gen, bank->base +
2217 OMAP24XX_GPIO_LEVELDETECT1);
2218 __raw_writel(old0, bank->base +
2219 OMAP24XX_GPIO_LEVELDETECT0);
2220 __raw_writel(old1, bank->base +
2221 OMAP24XX_GPIO_LEVELDETECT1);
2222 }
2223
2224 if (cpu_is_omap44xx()) {
2225 old0 = __raw_readl(bank->base +
2226 OMAP4_GPIO_LEVELDETECT0);
2227 old1 = __raw_readl(bank->base +
2228 OMAP4_GPIO_LEVELDETECT1);
2229 __raw_writel(old0 | l, bank->base +
2230 OMAP4_GPIO_LEVELDETECT0);
2231 __raw_writel(old1 | l, bank->base +
2232 OMAP4_GPIO_LEVELDETECT1);
2233 __raw_writel(old0, bank->base +
2234 OMAP4_GPIO_LEVELDETECT0);
2235 __raw_writel(old1, bank->base +
2236 OMAP4_GPIO_LEVELDETECT1);
2237 }
2238 }
2239 }
2240
2241 }
2242
2243 #endif
2244
2245 #ifdef CONFIG_ARCH_OMAP3
2246 /* save the registers of bank 2-6 */
2247 void omap_gpio_save_context(void)
2248 {
2249 int i;
2250
2251 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2252 for (i = 1; i < gpio_bank_count; i++) {
2253 struct gpio_bank *bank = &gpio_bank[i];
2254 gpio_context[i].sysconfig =
2255 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2256 gpio_context[i].irqenable1 =
2257 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2258 gpio_context[i].irqenable2 =
2259 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2260 gpio_context[i].wake_en =
2261 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2262 gpio_context[i].ctrl =
2263 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2264 gpio_context[i].oe =
2265 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2266 gpio_context[i].leveldetect0 =
2267 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2268 gpio_context[i].leveldetect1 =
2269 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2270 gpio_context[i].risingdetect =
2271 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2272 gpio_context[i].fallingdetect =
2273 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2274 gpio_context[i].dataout =
2275 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2276 }
2277 }
2278
2279 /* restore the required registers of bank 2-6 */
2280 void omap_gpio_restore_context(void)
2281 {
2282 int i;
2283
2284 for (i = 1; i < gpio_bank_count; i++) {
2285 struct gpio_bank *bank = &gpio_bank[i];
2286 __raw_writel(gpio_context[i].sysconfig,
2287 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2288 __raw_writel(gpio_context[i].irqenable1,
2289 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2290 __raw_writel(gpio_context[i].irqenable2,
2291 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2292 __raw_writel(gpio_context[i].wake_en,
2293 bank->base + OMAP24XX_GPIO_WAKE_EN);
2294 __raw_writel(gpio_context[i].ctrl,
2295 bank->base + OMAP24XX_GPIO_CTRL);
2296 __raw_writel(gpio_context[i].oe,
2297 bank->base + OMAP24XX_GPIO_OE);
2298 __raw_writel(gpio_context[i].leveldetect0,
2299 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2300 __raw_writel(gpio_context[i].leveldetect1,
2301 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2302 __raw_writel(gpio_context[i].risingdetect,
2303 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2304 __raw_writel(gpio_context[i].fallingdetect,
2305 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2306 __raw_writel(gpio_context[i].dataout,
2307 bank->base + OMAP24XX_GPIO_DATAOUT);
2308 }
2309 }
2310 #endif
2311
2312 /*
2313 * This may get called early from board specific init
2314 * for boards that have interrupts routed via FPGA.
2315 */
2316 int __init omap_gpio_init(void)
2317 {
2318 if (!initialized)
2319 return _omap_gpio_init();
2320 else
2321 return 0;
2322 }
2323
2324 static int __init omap_gpio_sysinit(void)
2325 {
2326 int ret = 0;
2327
2328 if (!initialized)
2329 ret = _omap_gpio_init();
2330
2331 mpuio_init();
2332
2333 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2334 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2335 if (ret == 0) {
2336 ret = sysdev_class_register(&omap_gpio_sysclass);
2337 if (ret == 0)
2338 ret = sysdev_register(&omap_gpio_device);
2339 }
2340 }
2341 #endif
2342
2343 return ret;
2344 }
2345
2346 arch_initcall(omap_gpio_sysinit);
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