arch/arm/plat-omap/include/mach/irqs.h

   1 /*
   2  *  arch/arm/plat-omap/include/mach/irqs.h
   3  *
   4  *  Copyright (C) Greg Lonnon 2001
   5  *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments
   8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23  *
  24  * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
  25  *       are different.
  26  */
  27
  28 #ifndef __ASM_ARCH_OMAP15XX_IRQS_H
  29 #define __ASM_ARCH_OMAP15XX_IRQS_H
  30
  31 /*
  32  * IRQ numbers for interrupt handler 1
  33  *
  34  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
  35  *
  36  */
  37 #define INT_CAMERA              1
  38 #define INT_FIQ                 3
  39 #define INT_RTDX                6
  40 #define INT_DSP_MMU_ABORT       7
  41 #define INT_HOST                8
  42 #define INT_ABORT               9
  43 #define INT_BRIDGE_PRIV         13
  44 #define INT_GPIO_BANK1          14
  45 #define INT_UART3               15
  46 #define INT_TIMER3              16
  47 #define INT_DMA_CH0_6           19
  48 #define INT_DMA_CH1_7           20
  49 #define INT_DMA_CH2_8           21
  50 #define INT_DMA_CH3             22
  51 #define INT_DMA_CH4             23
  52 #define INT_DMA_CH5             24
  53 #define INT_DMA_LCD             25
  54 #define INT_TIMER1              26
  55 #define INT_WD_TIMER            27
  56 #define INT_BRIDGE_PUB          28
  57 #define INT_TIMER2              30
  58 #define INT_LCD_CTRL            31
  59
  60 /*
  61  * OMAP-1510 specific IRQ numbers for interrupt handler 1
  62  */
  63 #define INT_1510_IH2_IRQ        0
  64 #define INT_1510_RES2           2
  65 #define INT_1510_SPI_TX         4
  66 #define INT_1510_SPI_RX         5
  67 #define INT_1510_DSP_MAILBOX1   10
  68 #define INT_1510_DSP_MAILBOX2   11
  69 #define INT_1510_RES12          12
  70 #define INT_1510_LB_MMU         17
  71 #define INT_1510_RES18          18
  72 #define INT_1510_LOCAL_BUS      29
  73
  74 /*
  75  * OMAP-1610 specific IRQ numbers for interrupt handler 1
  76  */
  77 #define INT_1610_IH2_IRQ        0
  78 #define INT_1610_IH2_FIQ        2
  79 #define INT_1610_McBSP2_TX      4
  80 #define INT_1610_McBSP2_RX      5
  81 #define INT_1610_DSP_MAILBOX1   10
  82 #define INT_1610_DSP_MAILBOX2   11
  83 #define INT_1610_LCD_LINE       12
  84 #define INT_1610_GPTIMER1       17
  85 #define INT_1610_GPTIMER2       18
  86 #define INT_1610_SSR_FIFO_0     29
  87
  88 /*
  89  * OMAP-730 specific IRQ numbers for interrupt handler 1
  90  */
  91 #define INT_730_IH2_FIQ         0
  92 #define INT_730_IH2_IRQ         1
  93 #define INT_730_USB_NON_ISO     2
  94 #define INT_730_USB_ISO         3
  95 #define INT_730_ICR             4
  96 #define INT_730_EAC             5
  97 #define INT_730_GPIO_BANK1      6
  98 #define INT_730_GPIO_BANK2      7
  99 #define INT_730_GPIO_BANK3      8
 100 #define INT_730_McBSP2TX        10
 101 #define INT_730_McBSP2RX        11
 102 #define INT_730_McBSP2RX_OVF    12
 103 #define INT_730_LCD_LINE        14
 104 #define INT_730_GSM_PROTECT     15
 105 #define INT_730_TIMER3          16
 106 #define INT_730_GPIO_BANK5      17
 107 #define INT_730_GPIO_BANK6      18
 108 #define INT_730_SPGIO_WR        29
 109
 110 /*
 111  * OMAP-850 specific IRQ numbers for interrupt handler 1
 112  */
 113 #define INT_850_IH2_FIQ         0
 114 #define INT_850_IH2_IRQ         1
 115 #define INT_850_USB_NON_ISO     2
 116 #define INT_850_USB_ISO         3
 117 #define INT_850_ICR             4
 118 #define INT_850_EAC             5
 119 #define INT_850_GPIO_BANK1      6
 120 #define INT_850_GPIO_BANK2      7
 121 #define INT_850_GPIO_BANK3      8
 122 #define INT_850_McBSP2TX        10
 123 #define INT_850_McBSP2RX        11
 124 #define INT_850_McBSP2RX_OVF    12
 125 #define INT_850_LCD_LINE        14
 126 #define INT_850_GSM_PROTECT     15
 127 #define INT_850_TIMER3          16
 128 #define INT_850_GPIO_BANK5      17
 129 #define INT_850_GPIO_BANK6      18
 130 #define INT_850_SPGIO_WR        29
 131
 132
 133 /*
 134  * IRQ numbers for interrupt handler 2
 135  *
 136  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
 137  */
 138 #define IH2_BASE                32
 139
 140 #define INT_KEYBOARD            (1 + IH2_BASE)
 141 #define INT_uWireTX             (2 + IH2_BASE)
 142 #define INT_uWireRX             (3 + IH2_BASE)
 143 #define INT_I2C                 (4 + IH2_BASE)
 144 #define INT_MPUIO               (5 + IH2_BASE)
 145 #define INT_USB_HHC_1           (6 + IH2_BASE)
 146 #define INT_McBSP3TX            (10 + IH2_BASE)
 147 #define INT_McBSP3RX            (11 + IH2_BASE)
 148 #define INT_McBSP1TX            (12 + IH2_BASE)
 149 #define INT_McBSP1RX            (13 + IH2_BASE)
 150 #define INT_UART1               (14 + IH2_BASE)
 151 #define INT_UART2               (15 + IH2_BASE)
 152 #define INT_BT_MCSI1TX          (16 + IH2_BASE)
 153 #define INT_BT_MCSI1RX          (17 + IH2_BASE)
 154 #define INT_SOSSI_MATCH         (19 + IH2_BASE)
 155 #define INT_USB_W2FC            (20 + IH2_BASE)
 156 #define INT_1WIRE               (21 + IH2_BASE)
 157 #define INT_OS_TIMER            (22 + IH2_BASE)
 158 #define INT_MMC                 (23 + IH2_BASE)
 159 #define INT_GAUGE_32K           (24 + IH2_BASE)
 160 #define INT_RTC_TIMER           (25 + IH2_BASE)
 161 #define INT_RTC_ALARM           (26 + IH2_BASE)
 162 #define INT_MEM_STICK           (27 + IH2_BASE)
 163
 164 /*
 165  * OMAP-1510 specific IRQ numbers for interrupt handler 2
 166  */
 167 #define INT_1510_DSP_MMU        (28 + IH2_BASE)
 168 #define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
 169
 170 /*
 171  * OMAP-1610 specific IRQ numbers for interrupt handler 2
 172  */
 173 #define INT_1610_FAC            (0 + IH2_BASE)
 174 #define INT_1610_USB_HHC_2      (7 + IH2_BASE)
 175 #define INT_1610_USB_OTG        (8 + IH2_BASE)
 176 #define INT_1610_SoSSI          (9 + IH2_BASE)
 177 #define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
 178 #define INT_1610_DSP_MMU        (28 + IH2_BASE)
 179 #define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
 180 #define INT_1610_STI            (32 + IH2_BASE)
 181 #define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
 182 #define INT_1610_GPTIMER3       (34 + IH2_BASE)
 183 #define INT_1610_GPTIMER4       (35 + IH2_BASE)
 184 #define INT_1610_GPTIMER5       (36 + IH2_BASE)
 185 #define INT_1610_GPTIMER6       (37 + IH2_BASE)
 186 #define INT_1610_GPTIMER7       (38 + IH2_BASE)
 187 #define INT_1610_GPTIMER8       (39 + IH2_BASE)
 188 #define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
 189 #define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
 190 #define INT_1610_MMC2           (42 + IH2_BASE)
 191 #define INT_1610_CF             (43 + IH2_BASE)
 192 #define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
 193 #define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
 194 #define INT_1610_SPI            (49 + IH2_BASE)
 195 #define INT_1610_DMA_CH6        (53 + IH2_BASE)
 196 #define INT_1610_DMA_CH7        (54 + IH2_BASE)
 197 #define INT_1610_DMA_CH8        (55 + IH2_BASE)
 198 #define INT_1610_DMA_CH9        (56 + IH2_BASE)
 199 #define INT_1610_DMA_CH10       (57 + IH2_BASE)
 200 #define INT_1610_DMA_CH11       (58 + IH2_BASE)
 201 #define INT_1610_DMA_CH12       (59 + IH2_BASE)
 202 #define INT_1610_DMA_CH13       (60 + IH2_BASE)
 203 #define INT_1610_DMA_CH14       (61 + IH2_BASE)
 204 #define INT_1610_DMA_CH15       (62 + IH2_BASE)
 205 #define INT_1610_NAND           (63 + IH2_BASE)
 206 #define INT_1610_SHA1MD5        (91 + IH2_BASE)
 207
 208 /*
 209  * OMAP-730 specific IRQ numbers for interrupt handler 2
 210  */
 211 #define INT_730_HW_ERRORS       (0 + IH2_BASE)
 212 #define INT_730_NFIQ_PWR_FAIL   (1 + IH2_BASE)
 213 #define INT_730_CFCD            (2 + IH2_BASE)
 214 #define INT_730_CFIREQ          (3 + IH2_BASE)
 215 #define INT_730_I2C             (4 + IH2_BASE)
 216 #define INT_730_PCC             (5 + IH2_BASE)
 217 #define INT_730_MPU_EXT_NIRQ    (6 + IH2_BASE)
 218 #define INT_730_SPI_100K_1      (7 + IH2_BASE)
 219 #define INT_730_SYREN_SPI       (8 + IH2_BASE)
 220 #define INT_730_VLYNQ           (9 + IH2_BASE)
 221 #define INT_730_GPIO_BANK4      (10 + IH2_BASE)
 222 #define INT_730_McBSP1TX        (11 + IH2_BASE)
 223 #define INT_730_McBSP1RX        (12 + IH2_BASE)
 224 #define INT_730_McBSP1RX_OF     (13 + IH2_BASE)
 225 #define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
 226 #define INT_730_UART_MODEM_1    (15 + IH2_BASE)
 227 #define INT_730_MCSI            (16 + IH2_BASE)
 228 #define INT_730_uWireTX         (17 + IH2_BASE)
 229 #define INT_730_uWireRX         (18 + IH2_BASE)
 230 #define INT_730_SMC_CD          (19 + IH2_BASE)
 231 #define INT_730_SMC_IREQ        (20 + IH2_BASE)
 232 #define INT_730_HDQ_1WIRE       (21 + IH2_BASE)
 233 #define INT_730_TIMER32K        (22 + IH2_BASE)
 234 #define INT_730_MMC_SDIO        (23 + IH2_BASE)
 235 #define INT_730_UPLD            (24 + IH2_BASE)
 236 #define INT_730_USB_HHC_1       (27 + IH2_BASE)
 237 #define INT_730_USB_HHC_2       (28 + IH2_BASE)
 238 #define INT_730_USB_GENI        (29 + IH2_BASE)
 239 #define INT_730_USB_OTG         (30 + IH2_BASE)
 240 #define INT_730_CAMERA_IF       (31 + IH2_BASE)
 241 #define INT_730_RNG             (32 + IH2_BASE)
 242 #define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
 243 #define INT_730_DBB_RF_EN       (34 + IH2_BASE)
 244 #define INT_730_MPUIO_KEYPAD    (35 + IH2_BASE)
 245 #define INT_730_SHA1_MD5        (36 + IH2_BASE)
 246 #define INT_730_SPI_100K_2      (37 + IH2_BASE)
 247 #define INT_730_RNG_IDLE        (38 + IH2_BASE)
 248 #define INT_730_MPUIO           (39 + IH2_BASE)
 249 #define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
 250 #define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
 251 #define INT_730_LLPC_OE_RISING  (42 + IH2_BASE)
 252 #define INT_730_LLPC_VSYNC      (43 + IH2_BASE)
 253 #define INT_730_WAKE_UP_REQ     (46 + IH2_BASE)
 254 #define INT_730_DMA_CH6         (53 + IH2_BASE)
 255 #define INT_730_DMA_CH7         (54 + IH2_BASE)
 256 #define INT_730_DMA_CH8         (55 + IH2_BASE)
 257 #define INT_730_DMA_CH9         (56 + IH2_BASE)
 258 #define INT_730_DMA_CH10        (57 + IH2_BASE)
 259 #define INT_730_DMA_CH11        (58 + IH2_BASE)
 260 #define INT_730_DMA_CH12        (59 + IH2_BASE)
 261 #define INT_730_DMA_CH13        (60 + IH2_BASE)
 262 #define INT_730_DMA_CH14        (61 + IH2_BASE)
 263 #define INT_730_DMA_CH15        (62 + IH2_BASE)
 264 #define INT_730_NAND            (63 + IH2_BASE)
 265
 266 /*
 267  * OMAP-850 specific IRQ numbers for interrupt handler 2
 268  */
 269 #define INT_850_HW_ERRORS       (0 + IH2_BASE)
 270 #define INT_850_NFIQ_PWR_FAIL   (1 + IH2_BASE)
 271 #define INT_850_CFCD            (2 + IH2_BASE)
 272 #define INT_850_CFIREQ          (3 + IH2_BASE)
 273 #define INT_850_I2C             (4 + IH2_BASE)
 274 #define INT_850_PCC             (5 + IH2_BASE)
 275 #define INT_850_MPU_EXT_NIRQ    (6 + IH2_BASE)
 276 #define INT_850_SPI_100K_1      (7 + IH2_BASE)
 277 #define INT_850_SYREN_SPI       (8 + IH2_BASE)
 278 #define INT_850_VLYNQ           (9 + IH2_BASE)
 279 #define INT_850_GPIO_BANK4      (10 + IH2_BASE)
 280 #define INT_850_McBSP1TX        (11 + IH2_BASE)
 281 #define INT_850_McBSP1RX        (12 + IH2_BASE)
 282 #define INT_850_McBSP1RX_OF     (13 + IH2_BASE)
 283 #define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
 284 #define INT_850_UART_MODEM_1    (15 + IH2_BASE)
 285 #define INT_850_MCSI            (16 + IH2_BASE)
 286 #define INT_850_uWireTX         (17 + IH2_BASE)
 287 #define INT_850_uWireRX         (18 + IH2_BASE)
 288 #define INT_850_SMC_CD          (19 + IH2_BASE)
 289 #define INT_850_SMC_IREQ        (20 + IH2_BASE)
 290 #define INT_850_HDQ_1WIRE       (21 + IH2_BASE)
 291 #define INT_850_TIMER32K        (22 + IH2_BASE)
 292 #define INT_850_MMC_SDIO        (23 + IH2_BASE)
 293 #define INT_850_UPLD            (24 + IH2_BASE)
 294 #define INT_850_USB_HHC_1       (27 + IH2_BASE)
 295 #define INT_850_USB_HHC_2       (28 + IH2_BASE)
 296 #define INT_850_USB_GENI        (29 + IH2_BASE)
 297 #define INT_850_USB_OTG         (30 + IH2_BASE)
 298 #define INT_850_CAMERA_IF       (31 + IH2_BASE)
 299 #define INT_850_RNG             (32 + IH2_BASE)
 300 #define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
 301 #define INT_850_DBB_RF_EN       (34 + IH2_BASE)
 302 #define INT_850_MPUIO_KEYPAD    (35 + IH2_BASE)
 303 #define INT_850_SHA1_MD5        (36 + IH2_BASE)
 304 #define INT_850_SPI_100K_2      (37 + IH2_BASE)
 305 #define INT_850_RNG_IDLE        (38 + IH2_BASE)
 306 #define INT_850_MPUIO           (39 + IH2_BASE)
 307 #define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
 308 #define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
 309 #define INT_850_LLPC_OE_RISING  (42 + IH2_BASE)
 310 #define INT_850_LLPC_VSYNC      (43 + IH2_BASE)
 311 #define INT_850_WAKE_UP_REQ     (46 + IH2_BASE)
 312 #define INT_850_DMA_CH6         (53 + IH2_BASE)
 313 #define INT_850_DMA_CH7         (54 + IH2_BASE)
 314 #define INT_850_DMA_CH8         (55 + IH2_BASE)
 315 #define INT_850_DMA_CH9         (56 + IH2_BASE)
 316 #define INT_850_DMA_CH10        (57 + IH2_BASE)
 317 #define INT_850_DMA_CH11        (58 + IH2_BASE)
 318 #define INT_850_DMA_CH12        (59 + IH2_BASE)
 319 #define INT_850_DMA_CH13        (60 + IH2_BASE)
 320 #define INT_850_DMA_CH14        (61 + IH2_BASE)
 321 #define INT_850_DMA_CH15        (62 + IH2_BASE)
 322 #define INT_850_NAND            (63 + IH2_BASE)
 323
 324 #define INT_24XX_SYS_NIRQ       7
 325 #define INT_24XX_SDMA_IRQ0      12
 326 #define INT_24XX_SDMA_IRQ1      13
 327 #define INT_24XX_SDMA_IRQ2      14
 328 #define INT_24XX_SDMA_IRQ3      15
 329 #define INT_24XX_CAM_IRQ        24
 330 #define INT_24XX_DSS_IRQ        25
 331 #define INT_24XX_MAIL_U0_MPU    26
 332 #define INT_24XX_DSP_UMA        27
 333 #define INT_24XX_DSP_MMU        28
 334 #define INT_24XX_GPIO_BANK1     29
 335 #define INT_24XX_GPIO_BANK2     30
 336 #define INT_24XX_GPIO_BANK3     31
 337 #define INT_24XX_GPIO_BANK4     32
 338 #define INT_24XX_GPIO_BANK5     33
 339 #define INT_24XX_MAIL_U3_MPU    34
 340 #define INT_24XX_GPTIMER1       37
 341 #define INT_24XX_GPTIMER2       38
 342 #define INT_24XX_GPTIMER3       39
 343 #define INT_24XX_GPTIMER4       40
 344 #define INT_24XX_GPTIMER5       41
 345 #define INT_24XX_GPTIMER6       42
 346 #define INT_24XX_GPTIMER7       43
 347 #define INT_24XX_GPTIMER8       44
 348 #define INT_24XX_GPTIMER9       45
 349 #define INT_24XX_GPTIMER10      46
 350 #define INT_24XX_GPTIMER11      47
 351 #define INT_24XX_GPTIMER12      48
 352 #define INT_24XX_SHA1MD5        51
 353 #define INT_24XX_MCBSP4_IRQ_TX  54
 354 #define INT_24XX_MCBSP4_IRQ_RX  55
 355 #define INT_24XX_I2C1_IRQ       56
 356 #define INT_24XX_I2C2_IRQ       57
 357 #define INT_24XX_HDQ_IRQ        58
 358 #define INT_24XX_MCBSP1_IRQ_TX  59
 359 #define INT_24XX_MCBSP1_IRQ_RX  60
 360 #define INT_24XX_MCBSP2_IRQ_TX  62
 361 #define INT_24XX_MCBSP2_IRQ_RX  63
 362 #define INT_24XX_SPI1_IRQ       65
 363 #define INT_24XX_SPI2_IRQ       66
 364 #define INT_24XX_UART1_IRQ      72
 365 #define INT_24XX_UART2_IRQ      73
 366 #define INT_24XX_UART3_IRQ      74
 367 #define INT_24XX_USB_IRQ_GEN    75
 368 #define INT_24XX_USB_IRQ_NISO   76
 369 #define INT_24XX_USB_IRQ_ISO    77
 370 #define INT_24XX_USB_IRQ_HGEN   78
 371 #define INT_24XX_USB_IRQ_HSOF   79
 372 #define INT_24XX_USB_IRQ_OTG    80
 373 #define INT_24XX_MCBSP5_IRQ_TX  81
 374 #define INT_24XX_MCBSP5_IRQ_RX  82
 375 #define INT_24XX_MMC_IRQ        83
 376 #define INT_24XX_MMC2_IRQ       86
 377 #define INT_24XX_MCBSP3_IRQ_TX  89
 378 #define INT_24XX_MCBSP3_IRQ_RX  90
 379 #define INT_24XX_SPI3_IRQ       91
 380
 381 #define INT_243X_MCBSP2_IRQ     16
 382 #define INT_243X_MCBSP3_IRQ     17
 383 #define INT_243X_MCBSP4_IRQ     18
 384 #define INT_243X_MCBSP5_IRQ     19
 385 #define INT_243X_MCBSP1_IRQ     64
 386 #define INT_243X_HS_USB_MC      92
 387 #define INT_243X_HS_USB_DMA     93
 388 #define INT_243X_CARKIT_IRQ     94
 389
 390 #define INT_34XX_BENCH_MPU_EMUL 3
 391 #define INT_34XX_ST_MCBSP2_IRQ  4
 392 #define INT_34XX_ST_MCBSP3_IRQ  5
 393 #define INT_34XX_SSM_ABORT_IRQ  6
 394 #define INT_34XX_SYS_NIRQ       7
 395 #define INT_34XX_D2D_FW_IRQ     8
 396 #define INT_34XX_PRCM_MPU_IRQ   11
 397 #define INT_34XX_MCBSP1_IRQ     16
 398 #define INT_34XX_MCBSP2_IRQ     17
 399 #define INT_34XX_MCBSP3_IRQ     22
 400 #define INT_34XX_MCBSP4_IRQ     23
 401 #define INT_34XX_CAM_IRQ        24
 402 #define INT_34XX_MCBSP5_IRQ     27
 403 #define INT_34XX_GPIO_BANK1     29
 404 #define INT_34XX_GPIO_BANK2     30
 405 #define INT_34XX_GPIO_BANK3     31
 406 #define INT_34XX_GPIO_BANK4     32
 407 #define INT_34XX_GPIO_BANK5     33
 408 #define INT_34XX_GPIO_BANK6     34
 409 #define INT_34XX_USIM_IRQ       35
 410 #define INT_34XX_WDT3_IRQ       36
 411 #define INT_34XX_SPI4_IRQ       48
 412 #define INT_34XX_SHA1MD52_IRQ   49
 413 #define INT_34XX_FPKA_READY_IRQ 50
 414 #define INT_34XX_SHA1MD51_IRQ   51
 415 #define INT_34XX_RNG_IRQ        52
 416 #define INT_34XX_I2C3_IRQ       61
 417 #define INT_34XX_FPKA_ERROR_IRQ 64
 418 #define INT_34XX_PBIAS_IRQ      75
 419 #define INT_34XX_OHCI_IRQ       76
 420 #define INT_34XX_EHCI_IRQ       77
 421 #define INT_34XX_TLL_IRQ        78
 422 #define INT_34XX_PARTHASH_IRQ   79
 423 #define INT_34XX_MMC3_IRQ       94
 424 #define INT_34XX_GPT12_IRQ      95
 425
 426 #define INT_34XX_BENCH_MPU_EMUL 3
 427
 428
 429 #define IRQ_GIC_START           32
 430 #define INT_44XX_LOCALTIMER_IRQ 29
 431 #define INT_44XX_LOCALWDT_IRQ   30
 432
 433 #define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
 434 #define INT_44XX_SSM_ABORT_IRQ  (6 + IRQ_GIC_START)
 435 #define INT_44XX_SYS_NIRQ       (7 + IRQ_GIC_START)
 436 #define INT_44XX_D2D_FW_IRQ     (8 + IRQ_GIC_START)
 437 #define INT_44XX_PRCM_MPU_IRQ   (11 + IRQ_GIC_START)
 438 #define INT_44XX_SDMA_IRQ0      (12 + IRQ_GIC_START)
 439 #define INT_44XX_SDMA_IRQ1      (13 + IRQ_GIC_START)
 440 #define INT_44XX_SDMA_IRQ2      (14 + IRQ_GIC_START)
 441 #define INT_44XX_SDMA_IRQ3      (15 + IRQ_GIC_START)
 442 #define INT_44XX_ISS_IRQ        (24 + IRQ_GIC_START)
 443 #define INT_44XX_DSS_IRQ        (25 + IRQ_GIC_START)
 444 #define INT_44XX_MAIL_U0_MPU    (26 + IRQ_GIC_START)
 445 #define INT_44XX_DSP_MMU        (28 + IRQ_GIC_START)
 446 #define INT_44XX_GPTIMER1       (37 + IRQ_GIC_START)
 447 #define INT_44XX_GPTIMER2       (38 + IRQ_GIC_START)
 448 #define INT_44XX_GPTIMER3       (39 + IRQ_GIC_START)
 449 #define INT_44XX_GPTIMER4       (40 + IRQ_GIC_START)
 450 #define INT_44XX_GPTIMER5       (41 + IRQ_GIC_START)
 451 #define INT_44XX_GPTIMER6       (42 + IRQ_GIC_START)
 452 #define INT_44XX_GPTIMER7       (43 + IRQ_GIC_START)
 453 #define INT_44XX_GPTIMER8       (44 + IRQ_GIC_START)
 454 #define INT_44XX_GPTIMER9       (45 + IRQ_GIC_START)
 455 #define INT_44XX_GPTIMER10      (46 + IRQ_GIC_START)
 456 #define INT_44XX_GPTIMER11      (47 + IRQ_GIC_START)
 457 #define INT_44XX_GPTIMER12      (95 + IRQ_GIC_START)
 458 #define INT_44XX_SHA1MD5        (51 + IRQ_GIC_START)
 459 #define INT_44XX_I2C1_IRQ       (56 + IRQ_GIC_START)
 460 #define INT_44XX_I2C2_IRQ       (57 + IRQ_GIC_START)
 461 #define INT_44XX_HDQ_IRQ        (58 + IRQ_GIC_START)
 462 #define INT_44XX_SPI1_IRQ       (65 + IRQ_GIC_START)
 463 #define INT_44XX_SPI2_IRQ       (66 + IRQ_GIC_START)
 464 #define INT_44XX_HSI_1_IRQ0     (67 + IRQ_GIC_START)
 465 #define INT_44XX_HSI_2_IRQ1     (68 + IRQ_GIC_START)
 466 #define INT_44XX_HSI_1_DMAIRQ   (71 + IRQ_GIC_START)
 467 #define INT_44XX_UART1_IRQ      (72 + IRQ_GIC_START)
 468 #define INT_44XX_UART2_IRQ      (73 + IRQ_GIC_START)
 469 #define INT_44XX_UART3_IRQ      (74 + IRQ_GIC_START)
 470 #define INT_44XX_UART4_IRQ      (70 + IRQ_GIC_START)
 471 #define INT_44XX_USB_IRQ_NISO   (76 + IRQ_GIC_START)
 472 #define INT_44XX_USB_IRQ_ISO    (77 + IRQ_GIC_START)
 473 #define INT_44XX_USB_IRQ_HGEN   (78 + IRQ_GIC_START)
 474 #define INT_44XX_USB_IRQ_HSOF   (79 + IRQ_GIC_START)
 475 #define INT_44XX_USB_IRQ_OTG    (80 + IRQ_GIC_START)
 476 #define INT_44XX_MCBSP4_IRQ_TX  (81 + IRQ_GIC_START)
 477 #define INT_44XX_MCBSP4_IRQ_RX  (82 + IRQ_GIC_START)
 478 #define INT_44XX_MMC_IRQ        (83 + IRQ_GIC_START)
 479 #define INT_44XX_MMC2_IRQ       (86 + IRQ_GIC_START)
 480 #define INT_44XX_MCBSP2_IRQ_TX  (89 + IRQ_GIC_START)
 481 #define INT_44XX_MCBSP2_IRQ_RX  (90 + IRQ_GIC_START)
 482 #define INT_44XX_SPI3_IRQ       (91 + IRQ_GIC_START)
 483 #define INT_44XX_SPI5_IRQ       (69 + IRQ_GIC_START)
 484
 485 #define INT_44XX_MCBSP5_IRQ     (16 + IRQ_GIC_START)
 486 #define INT_44xX_MCBSP1_IRQ     (17 + IRQ_GIC_START)
 487 #define INT_44XX_MCBSP2_IRQ     (22 + IRQ_GIC_START)
 488 #define INT_44XX_MCBSP3_IRQ     (23 + IRQ_GIC_START)
 489 #define INT_44XX_MCBSP4_IRQ     (27 + IRQ_GIC_START)
 490 #define INT_44XX_HS_USB_MC      (92 + IRQ_GIC_START)
 491 #define INT_44XX_HS_USB_DMA     (93 + IRQ_GIC_START)
 492
 493 #define INT_44XX_GPIO_BANK1     (29 + IRQ_GIC_START)
 494 #define INT_44XX_GPIO_BANK2     (30 + IRQ_GIC_START)
 495 #define INT_44XX_GPIO_BANK3     (31 + IRQ_GIC_START)
 496 #define INT_44XX_GPIO_BANK4     (32 + IRQ_GIC_START)
 497 #define INT_44XX_GPIO_BANK5     (33 + IRQ_GIC_START)
 498 #define INT_44XX_GPIO_BANK6     (34 + IRQ_GIC_START)
 499 #define INT_44XX_USIM_IRQ       (35 + IRQ_GIC_START)
 500 #define INT_44XX_WDT3_IRQ       (36 + IRQ_GIC_START)
 501 #define INT_44XX_SPI4_IRQ       (48 + IRQ_GIC_START)
 502 #define INT_44XX_SHA1MD52_IRQ   (49 + IRQ_GIC_START)
 503 #define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
 504 #define INT_44XX_SHA1MD51_IRQ   (51 + IRQ_GIC_START)
 505 #define INT_44XX_RNG_IRQ        (52 + IRQ_GIC_START)
 506 #define INT_44XX_I2C3_IRQ       (61 + IRQ_GIC_START)
 507 #define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
 508 #define INT_44XX_PBIAS_IRQ      (75 + IRQ_GIC_START)
 509 #define INT_44XX_OHCI_IRQ       (76 + IRQ_GIC_START)
 510 #define INT_44XX_EHCI_IRQ       (77 + IRQ_GIC_START)
 511 #define INT_44XX_TLL_IRQ        (78 + IRQ_GIC_START)
 512 #define INT_44XX_PARTHASH_IRQ   (79 + IRQ_GIC_START)
 513 #define INT_44XX_MMC3_IRQ       (94 + IRQ_GIC_START)
 514
 515
 516 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
 517  * 16 MPUIO lines */
 518 #define OMAP_MAX_GPIO_LINES     192
 519 #define IH_GPIO_BASE            (128 + IH2_BASE)
 520 #define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
 521 #define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
 522
 523 /* External FPGA handles interrupts on Innovator boards */
 524 #define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
 525 #ifdef  CONFIG_MACH_OMAP_INNOVATOR
 526 #define OMAP_FPGA_NR_IRQS       24
 527 #else
 528 #define OMAP_FPGA_NR_IRQS       0
 529 #endif
 530 #define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
 531
 532 /* External TWL4030 can handle interrupts on 2430 and 34xx boards */
 533 #define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
 534 #ifdef  CONFIG_TWL4030_CORE
 535 #define TWL4030_BASE_NR_IRQS    8
 536 #define TWL4030_PWR_NR_IRQS     8
 537 #else
 538 #define TWL4030_BASE_NR_IRQS    0
 539 #define TWL4030_PWR_NR_IRQS     0
 540 #endif
 541 #define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
 542 #define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
 543 #define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
 544
 545 /* External TWL4030 gpio interrupts are optional */
 546 #define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
 547 #ifdef  CONFIG_GPIO_TWL4030
 548 #define TWL4030_GPIO_NR_IRQS    18
 549 #else
 550 #define TWL4030_GPIO_NR_IRQS    0
 551 #endif
 552 #define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
 553
 554 /* Total number of interrupts depends on the enabled blocks above */
 555 #define NR_IRQS                 TWL4030_GPIO_IRQ_END
 556
 557 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 558
 559 #ifndef __ASSEMBLY__
 560 extern void omap_init_irq(void);
 561 extern int omap_irq_pending(void);
 562 #endif
 563
 564 #include <mach/hardware.h>
 565
 566 #endif