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[mirror_ubuntu-bionic-kernel.git] / arch / arm / plat-omap / mcbsp.c
1 /*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 #include <plat/dma.h>
29 #include <plat/mcbsp.h>
30
31 #include "../mach-omap2/cm-regbits-34xx.h"
32
33 struct omap_mcbsp **mcbsp_ptr;
34 int omap_mcbsp_count, omap_mcbsp_cache_size;
35
36 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
37 {
38 if (cpu_class_is_omap1()) {
39 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
40 __raw_writew((u16)val, mcbsp->io_base + reg);
41 } else if (cpu_is_omap2420()) {
42 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
43 __raw_writew((u16)val, mcbsp->io_base + reg);
44 } else {
45 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
46 __raw_writel(val, mcbsp->io_base + reg);
47 }
48 }
49
50 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
51 {
52 if (cpu_class_is_omap1()) {
53 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
54 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
55 } else if (cpu_is_omap2420()) {
56 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
57 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
58 } else {
59 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
60 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
61 }
62 }
63
64 #ifdef CONFIG_ARCH_OMAP3
65 void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
66 {
67 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
68 }
69
70 int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
71 {
72 return __raw_readl(mcbsp->st_data->io_base_st + reg);
73 }
74 #endif
75
76 #define MCBSP_READ(mcbsp, reg) \
77 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
78 #define MCBSP_WRITE(mcbsp, reg, val) \
79 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
80 #define MCBSP_READ_CACHE(mcbsp, reg) \
81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
82
83 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
84 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
85
86 #define MCBSP_ST_READ(mcbsp, reg) \
87 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
88 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
89 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
90
91 static void omap_mcbsp_dump_reg(u8 id)
92 {
93 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
94
95 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
96 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
97 MCBSP_READ(mcbsp, DRR2));
98 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
99 MCBSP_READ(mcbsp, DRR1));
100 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
101 MCBSP_READ(mcbsp, DXR2));
102 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
103 MCBSP_READ(mcbsp, DXR1));
104 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
105 MCBSP_READ(mcbsp, SPCR2));
106 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
107 MCBSP_READ(mcbsp, SPCR1));
108 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
109 MCBSP_READ(mcbsp, RCR2));
110 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
111 MCBSP_READ(mcbsp, RCR1));
112 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
113 MCBSP_READ(mcbsp, XCR2));
114 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
115 MCBSP_READ(mcbsp, XCR1));
116 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
117 MCBSP_READ(mcbsp, SRGR2));
118 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
119 MCBSP_READ(mcbsp, SRGR1));
120 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
121 MCBSP_READ(mcbsp, PCR0));
122 dev_dbg(mcbsp->dev, "***********************\n");
123 }
124
125 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
126 {
127 struct omap_mcbsp *mcbsp_tx = dev_id;
128 u16 irqst_spcr2;
129
130 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
131 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
132
133 if (irqst_spcr2 & XSYNC_ERR) {
134 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
135 irqst_spcr2);
136 /* Writing zero to XSYNC_ERR clears the IRQ */
137 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
138 } else {
139 complete(&mcbsp_tx->tx_irq_completion);
140 }
141
142 return IRQ_HANDLED;
143 }
144
145 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
146 {
147 struct omap_mcbsp *mcbsp_rx = dev_id;
148 u16 irqst_spcr1;
149
150 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
151 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
152
153 if (irqst_spcr1 & RSYNC_ERR) {
154 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
155 irqst_spcr1);
156 /* Writing zero to RSYNC_ERR clears the IRQ */
157 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
158 } else {
159 complete(&mcbsp_rx->tx_irq_completion);
160 }
161
162 return IRQ_HANDLED;
163 }
164
165 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
166 {
167 struct omap_mcbsp *mcbsp_dma_tx = data;
168
169 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
170 MCBSP_READ(mcbsp_dma_tx, SPCR2));
171
172 /* We can free the channels */
173 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
174 mcbsp_dma_tx->dma_tx_lch = -1;
175
176 complete(&mcbsp_dma_tx->tx_dma_completion);
177 }
178
179 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
180 {
181 struct omap_mcbsp *mcbsp_dma_rx = data;
182
183 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
184 MCBSP_READ(mcbsp_dma_rx, SPCR2));
185
186 /* We can free the channels */
187 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
188 mcbsp_dma_rx->dma_rx_lch = -1;
189
190 complete(&mcbsp_dma_rx->rx_dma_completion);
191 }
192
193 /*
194 * omap_mcbsp_config simply write a config to the
195 * appropriate McBSP.
196 * You either call this function or set the McBSP registers
197 * by yourself before calling omap_mcbsp_start().
198 */
199 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
200 {
201 struct omap_mcbsp *mcbsp;
202
203 if (!omap_mcbsp_check_valid_id(id)) {
204 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
205 return;
206 }
207 mcbsp = id_to_mcbsp_ptr(id);
208
209 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
210 mcbsp->id, mcbsp->phys_base);
211
212 /* We write the given config */
213 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
214 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
215 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
216 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
217 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
218 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
219 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
220 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
221 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
222 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
223 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
224 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
225 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
226 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
227 }
228 }
229 EXPORT_SYMBOL(omap_mcbsp_config);
230
231 #ifdef CONFIG_ARCH_OMAP3
232 static void omap_st_on(struct omap_mcbsp *mcbsp)
233 {
234 unsigned int w;
235
236 /*
237 * Sidetone uses McBSP ICLK - which must not idle when sidetones
238 * are enabled or sidetones start sounding ugly.
239 */
240 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
241 w &= ~(1 << (mcbsp->id - 2));
242 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
243
244 /* Enable McBSP Sidetone */
245 w = MCBSP_READ(mcbsp, SSELCR);
246 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
247
248 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
249 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
250
251 /* Enable Sidetone from Sidetone Core */
252 w = MCBSP_ST_READ(mcbsp, SSELCR);
253 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
254 }
255
256 static void omap_st_off(struct omap_mcbsp *mcbsp)
257 {
258 unsigned int w;
259
260 w = MCBSP_ST_READ(mcbsp, SSELCR);
261 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
262
263 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
264 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
265
266 w = MCBSP_READ(mcbsp, SSELCR);
267 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
268
269 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
270 w |= 1 << (mcbsp->id - 2);
271 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
272 }
273
274 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
275 {
276 u16 val, i;
277
278 val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
279 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
280
281 val = MCBSP_ST_READ(mcbsp, SSELCR);
282
283 if (val & ST_COEFFWREN)
284 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
285
286 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
287
288 for (i = 0; i < 128; i++)
289 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
290
291 i = 0;
292
293 val = MCBSP_ST_READ(mcbsp, SSELCR);
294 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
295 val = MCBSP_ST_READ(mcbsp, SSELCR);
296
297 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
298
299 if (i == 1000)
300 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
301 }
302
303 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
304 {
305 u16 w;
306 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
307
308 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
309 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
310
311 w = MCBSP_ST_READ(mcbsp, SSELCR);
312
313 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
314 ST_CH1GAIN(st_data->ch1gain));
315 }
316
317 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
318 {
319 struct omap_mcbsp *mcbsp;
320 struct omap_mcbsp_st_data *st_data;
321 int ret = 0;
322
323 if (!omap_mcbsp_check_valid_id(id)) {
324 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
325 return -ENODEV;
326 }
327
328 mcbsp = id_to_mcbsp_ptr(id);
329 st_data = mcbsp->st_data;
330
331 if (!st_data)
332 return -ENOENT;
333
334 spin_lock_irq(&mcbsp->lock);
335 if (channel == 0)
336 st_data->ch0gain = chgain;
337 else if (channel == 1)
338 st_data->ch1gain = chgain;
339 else
340 ret = -EINVAL;
341
342 if (st_data->enabled)
343 omap_st_chgain(mcbsp);
344 spin_unlock_irq(&mcbsp->lock);
345
346 return ret;
347 }
348 EXPORT_SYMBOL(omap_st_set_chgain);
349
350 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
351 {
352 struct omap_mcbsp *mcbsp;
353 struct omap_mcbsp_st_data *st_data;
354 int ret = 0;
355
356 if (!omap_mcbsp_check_valid_id(id)) {
357 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
358 return -ENODEV;
359 }
360
361 mcbsp = id_to_mcbsp_ptr(id);
362 st_data = mcbsp->st_data;
363
364 if (!st_data)
365 return -ENOENT;
366
367 spin_lock_irq(&mcbsp->lock);
368 if (channel == 0)
369 *chgain = st_data->ch0gain;
370 else if (channel == 1)
371 *chgain = st_data->ch1gain;
372 else
373 ret = -EINVAL;
374 spin_unlock_irq(&mcbsp->lock);
375
376 return ret;
377 }
378 EXPORT_SYMBOL(omap_st_get_chgain);
379
380 static int omap_st_start(struct omap_mcbsp *mcbsp)
381 {
382 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
383
384 if (st_data && st_data->enabled && !st_data->running) {
385 omap_st_fir_write(mcbsp, st_data->taps);
386 omap_st_chgain(mcbsp);
387
388 if (!mcbsp->free) {
389 omap_st_on(mcbsp);
390 st_data->running = 1;
391 }
392 }
393
394 return 0;
395 }
396
397 int omap_st_enable(unsigned int id)
398 {
399 struct omap_mcbsp *mcbsp;
400 struct omap_mcbsp_st_data *st_data;
401
402 if (!omap_mcbsp_check_valid_id(id)) {
403 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
404 return -ENODEV;
405 }
406
407 mcbsp = id_to_mcbsp_ptr(id);
408 st_data = mcbsp->st_data;
409
410 if (!st_data)
411 return -ENODEV;
412
413 spin_lock_irq(&mcbsp->lock);
414 st_data->enabled = 1;
415 omap_st_start(mcbsp);
416 spin_unlock_irq(&mcbsp->lock);
417
418 return 0;
419 }
420 EXPORT_SYMBOL(omap_st_enable);
421
422 static int omap_st_stop(struct omap_mcbsp *mcbsp)
423 {
424 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
425
426 if (st_data && st_data->running) {
427 if (!mcbsp->free) {
428 omap_st_off(mcbsp);
429 st_data->running = 0;
430 }
431 }
432
433 return 0;
434 }
435
436 int omap_st_disable(unsigned int id)
437 {
438 struct omap_mcbsp *mcbsp;
439 struct omap_mcbsp_st_data *st_data;
440 int ret = 0;
441
442 if (!omap_mcbsp_check_valid_id(id)) {
443 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
444 return -ENODEV;
445 }
446
447 mcbsp = id_to_mcbsp_ptr(id);
448 st_data = mcbsp->st_data;
449
450 if (!st_data)
451 return -ENODEV;
452
453 spin_lock_irq(&mcbsp->lock);
454 omap_st_stop(mcbsp);
455 st_data->enabled = 0;
456 spin_unlock_irq(&mcbsp->lock);
457
458 return ret;
459 }
460 EXPORT_SYMBOL(omap_st_disable);
461
462 int omap_st_is_enabled(unsigned int id)
463 {
464 struct omap_mcbsp *mcbsp;
465 struct omap_mcbsp_st_data *st_data;
466
467 if (!omap_mcbsp_check_valid_id(id)) {
468 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
469 return -ENODEV;
470 }
471
472 mcbsp = id_to_mcbsp_ptr(id);
473 st_data = mcbsp->st_data;
474
475 if (!st_data)
476 return -ENODEV;
477
478
479 return st_data->enabled;
480 }
481 EXPORT_SYMBOL(omap_st_is_enabled);
482
483 /*
484 * omap_mcbsp_set_tx_threshold configures how to deal
485 * with transmit threshold. the threshold value and handler can be
486 * configure in here.
487 */
488 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
489 {
490 struct omap_mcbsp *mcbsp;
491
492 if (!cpu_is_omap34xx())
493 return;
494
495 if (!omap_mcbsp_check_valid_id(id)) {
496 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
497 return;
498 }
499 mcbsp = id_to_mcbsp_ptr(id);
500
501 MCBSP_WRITE(mcbsp, THRSH2, threshold);
502 }
503 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
504
505 /*
506 * omap_mcbsp_set_rx_threshold configures how to deal
507 * with receive threshold. the threshold value and handler can be
508 * configure in here.
509 */
510 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
511 {
512 struct omap_mcbsp *mcbsp;
513
514 if (!cpu_is_omap34xx())
515 return;
516
517 if (!omap_mcbsp_check_valid_id(id)) {
518 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
519 return;
520 }
521 mcbsp = id_to_mcbsp_ptr(id);
522
523 MCBSP_WRITE(mcbsp, THRSH1, threshold);
524 }
525 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
526
527 /*
528 * omap_mcbsp_get_max_tx_thres just return the current configured
529 * maximum threshold for transmission
530 */
531 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
532 {
533 struct omap_mcbsp *mcbsp;
534
535 if (!omap_mcbsp_check_valid_id(id)) {
536 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
537 return -ENODEV;
538 }
539 mcbsp = id_to_mcbsp_ptr(id);
540
541 return mcbsp->max_tx_thres;
542 }
543 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
544
545 /*
546 * omap_mcbsp_get_max_rx_thres just return the current configured
547 * maximum threshold for reception
548 */
549 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
550 {
551 struct omap_mcbsp *mcbsp;
552
553 if (!omap_mcbsp_check_valid_id(id)) {
554 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
555 return -ENODEV;
556 }
557 mcbsp = id_to_mcbsp_ptr(id);
558
559 return mcbsp->max_rx_thres;
560 }
561 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
562
563 /*
564 * omap_mcbsp_get_dma_op_mode just return the current configured
565 * operating mode for the mcbsp channel
566 */
567 int omap_mcbsp_get_dma_op_mode(unsigned int id)
568 {
569 struct omap_mcbsp *mcbsp;
570 int dma_op_mode;
571
572 if (!omap_mcbsp_check_valid_id(id)) {
573 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
574 return -ENODEV;
575 }
576 mcbsp = id_to_mcbsp_ptr(id);
577
578 dma_op_mode = mcbsp->dma_op_mode;
579
580 return dma_op_mode;
581 }
582 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
583
584 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
585 {
586 /*
587 * Enable wakup behavior, smart idle and all wakeups
588 * REVISIT: some wakeups may be unnecessary
589 */
590 if (cpu_is_omap34xx()) {
591 u16 syscon;
592
593 syscon = MCBSP_READ(mcbsp, SYSCON);
594 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
595
596 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
597 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
598 CLOCKACTIVITY(0x02));
599 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
600 } else {
601 syscon |= SIDLEMODE(0x01);
602 }
603
604 MCBSP_WRITE(mcbsp, SYSCON, syscon);
605 }
606 }
607
608 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
609 {
610 /*
611 * Disable wakup behavior, smart idle and all wakeups
612 */
613 if (cpu_is_omap34xx()) {
614 u16 syscon;
615
616 syscon = MCBSP_READ(mcbsp, SYSCON);
617 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
618 /*
619 * HW bug workaround - If no_idle mode is taken, we need to
620 * go to smart_idle before going to always_idle, or the
621 * device will not hit retention anymore.
622 */
623 syscon |= SIDLEMODE(0x02);
624 MCBSP_WRITE(mcbsp, SYSCON, syscon);
625
626 syscon &= ~(SIDLEMODE(0x03));
627 MCBSP_WRITE(mcbsp, SYSCON, syscon);
628
629 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
630 }
631 }
632 #else
633 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
634 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
635 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
636 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
637 #endif
638
639 /*
640 * We can choose between IRQ based or polled IO.
641 * This needs to be called before omap_mcbsp_request().
642 */
643 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
644 {
645 struct omap_mcbsp *mcbsp;
646
647 if (!omap_mcbsp_check_valid_id(id)) {
648 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
649 return -ENODEV;
650 }
651 mcbsp = id_to_mcbsp_ptr(id);
652
653 spin_lock(&mcbsp->lock);
654
655 if (!mcbsp->free) {
656 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
657 mcbsp->id);
658 spin_unlock(&mcbsp->lock);
659 return -EINVAL;
660 }
661
662 mcbsp->io_type = io_type;
663
664 spin_unlock(&mcbsp->lock);
665
666 return 0;
667 }
668 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
669
670 int omap_mcbsp_request(unsigned int id)
671 {
672 struct omap_mcbsp *mcbsp;
673 void *reg_cache;
674 int err;
675
676 if (!omap_mcbsp_check_valid_id(id)) {
677 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
678 return -ENODEV;
679 }
680 mcbsp = id_to_mcbsp_ptr(id);
681
682 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
683 if (!reg_cache) {
684 return -ENOMEM;
685 }
686
687 spin_lock(&mcbsp->lock);
688 if (!mcbsp->free) {
689 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
690 mcbsp->id);
691 err = -EBUSY;
692 goto err_kfree;
693 }
694
695 mcbsp->free = 0;
696 mcbsp->reg_cache = reg_cache;
697 spin_unlock(&mcbsp->lock);
698
699 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
700 mcbsp->pdata->ops->request(id);
701
702 clk_enable(mcbsp->iclk);
703 clk_enable(mcbsp->fclk);
704
705 /* Do procedure specific to omap34xx arch, if applicable */
706 omap34xx_mcbsp_request(mcbsp);
707
708 /*
709 * Make sure that transmitter, receiver and sample-rate generator are
710 * not running before activating IRQs.
711 */
712 MCBSP_WRITE(mcbsp, SPCR1, 0);
713 MCBSP_WRITE(mcbsp, SPCR2, 0);
714
715 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
716 /* We need to get IRQs here */
717 init_completion(&mcbsp->tx_irq_completion);
718 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
719 0, "McBSP", (void *)mcbsp);
720 if (err != 0) {
721 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
722 "for McBSP%d\n", mcbsp->tx_irq,
723 mcbsp->id);
724 goto err_clk_disable;
725 }
726
727 init_completion(&mcbsp->rx_irq_completion);
728 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
729 0, "McBSP", (void *)mcbsp);
730 if (err != 0) {
731 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
732 "for McBSP%d\n", mcbsp->rx_irq,
733 mcbsp->id);
734 goto err_free_irq;
735 }
736 }
737
738 return 0;
739 err_free_irq:
740 free_irq(mcbsp->tx_irq, (void *)mcbsp);
741 err_clk_disable:
742 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
743 mcbsp->pdata->ops->free(id);
744
745 /* Do procedure specific to omap34xx arch, if applicable */
746 omap34xx_mcbsp_free(mcbsp);
747
748 clk_disable(mcbsp->fclk);
749 clk_disable(mcbsp->iclk);
750
751 spin_lock(&mcbsp->lock);
752 mcbsp->free = 1;
753 mcbsp->reg_cache = NULL;
754 err_kfree:
755 spin_unlock(&mcbsp->lock);
756 kfree(reg_cache);
757
758 return err;
759 }
760 EXPORT_SYMBOL(omap_mcbsp_request);
761
762 void omap_mcbsp_free(unsigned int id)
763 {
764 struct omap_mcbsp *mcbsp;
765 void *reg_cache;
766
767 if (!omap_mcbsp_check_valid_id(id)) {
768 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
769 return;
770 }
771 mcbsp = id_to_mcbsp_ptr(id);
772
773 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
774 mcbsp->pdata->ops->free(id);
775
776 /* Do procedure specific to omap34xx arch, if applicable */
777 omap34xx_mcbsp_free(mcbsp);
778
779 clk_disable(mcbsp->fclk);
780 clk_disable(mcbsp->iclk);
781
782 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
783 /* Free IRQs */
784 free_irq(mcbsp->rx_irq, (void *)mcbsp);
785 free_irq(mcbsp->tx_irq, (void *)mcbsp);
786 }
787
788 reg_cache = mcbsp->reg_cache;
789
790 spin_lock(&mcbsp->lock);
791 if (mcbsp->free)
792 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
793 else
794 mcbsp->free = 1;
795 mcbsp->reg_cache = NULL;
796 spin_unlock(&mcbsp->lock);
797
798 if (reg_cache)
799 kfree(reg_cache);
800 }
801 EXPORT_SYMBOL(omap_mcbsp_free);
802
803 /*
804 * Here we start the McBSP, by enabling transmitter, receiver or both.
805 * If no transmitter or receiver is active prior calling, then sample-rate
806 * generator and frame sync are started.
807 */
808 void omap_mcbsp_start(unsigned int id, int tx, int rx)
809 {
810 struct omap_mcbsp *mcbsp;
811 int idle;
812 u16 w;
813
814 if (!omap_mcbsp_check_valid_id(id)) {
815 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
816 return;
817 }
818 mcbsp = id_to_mcbsp_ptr(id);
819
820 if (cpu_is_omap34xx())
821 omap_st_start(mcbsp);
822
823 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
824 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
825
826 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
827 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
828
829 if (idle) {
830 /* Start the sample generator */
831 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
832 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
833 }
834
835 /* Enable transmitter and receiver */
836 tx &= 1;
837 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
838 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
839
840 rx &= 1;
841 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
842 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
843
844 /*
845 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
846 * REVISIT: 100us may give enough time for two CLKSRG, however
847 * due to some unknown PM related, clock gating etc. reason it
848 * is now at 500us.
849 */
850 udelay(500);
851
852 if (idle) {
853 /* Start frame sync */
854 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
855 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
856 }
857
858 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
859 /* Release the transmitter and receiver */
860 w = MCBSP_READ_CACHE(mcbsp, XCCR);
861 w &= ~(tx ? XDISABLE : 0);
862 MCBSP_WRITE(mcbsp, XCCR, w);
863 w = MCBSP_READ_CACHE(mcbsp, RCCR);
864 w &= ~(rx ? RDISABLE : 0);
865 MCBSP_WRITE(mcbsp, RCCR, w);
866 }
867
868 /* Dump McBSP Regs */
869 omap_mcbsp_dump_reg(id);
870 }
871 EXPORT_SYMBOL(omap_mcbsp_start);
872
873 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
874 {
875 struct omap_mcbsp *mcbsp;
876 int idle;
877 u16 w;
878
879 if (!omap_mcbsp_check_valid_id(id)) {
880 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
881 return;
882 }
883
884 mcbsp = id_to_mcbsp_ptr(id);
885
886 /* Reset transmitter */
887 tx &= 1;
888 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
889 w = MCBSP_READ_CACHE(mcbsp, XCCR);
890 w |= (tx ? XDISABLE : 0);
891 MCBSP_WRITE(mcbsp, XCCR, w);
892 }
893 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
894 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
895
896 /* Reset receiver */
897 rx &= 1;
898 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
899 w = MCBSP_READ_CACHE(mcbsp, RCCR);
900 w |= (rx ? RDISABLE : 0);
901 MCBSP_WRITE(mcbsp, RCCR, w);
902 }
903 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
904 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
905
906 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
907 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
908
909 if (idle) {
910 /* Reset the sample rate generator */
911 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
912 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
913 }
914
915 if (cpu_is_omap34xx())
916 omap_st_stop(mcbsp);
917 }
918 EXPORT_SYMBOL(omap_mcbsp_stop);
919
920 /* polled mcbsp i/o operations */
921 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
922 {
923 struct omap_mcbsp *mcbsp;
924
925 if (!omap_mcbsp_check_valid_id(id)) {
926 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
927 return -ENODEV;
928 }
929
930 mcbsp = id_to_mcbsp_ptr(id);
931
932 MCBSP_WRITE(mcbsp, DXR1, buf);
933 /* if frame sync error - clear the error */
934 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
935 /* clear error */
936 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
937 /* resend */
938 return -1;
939 } else {
940 /* wait for transmit confirmation */
941 int attemps = 0;
942 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
943 if (attemps++ > 1000) {
944 MCBSP_WRITE(mcbsp, SPCR2,
945 MCBSP_READ_CACHE(mcbsp, SPCR2) &
946 (~XRST));
947 udelay(10);
948 MCBSP_WRITE(mcbsp, SPCR2,
949 MCBSP_READ_CACHE(mcbsp, SPCR2) |
950 (XRST));
951 udelay(10);
952 dev_err(mcbsp->dev, "Could not write to"
953 " McBSP%d Register\n", mcbsp->id);
954 return -2;
955 }
956 }
957 }
958
959 return 0;
960 }
961 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
962
963 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
964 {
965 struct omap_mcbsp *mcbsp;
966
967 if (!omap_mcbsp_check_valid_id(id)) {
968 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
969 return -ENODEV;
970 }
971 mcbsp = id_to_mcbsp_ptr(id);
972
973 /* if frame sync error - clear the error */
974 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
975 /* clear error */
976 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
977 /* resend */
978 return -1;
979 } else {
980 /* wait for recieve confirmation */
981 int attemps = 0;
982 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
983 if (attemps++ > 1000) {
984 MCBSP_WRITE(mcbsp, SPCR1,
985 MCBSP_READ_CACHE(mcbsp, SPCR1) &
986 (~RRST));
987 udelay(10);
988 MCBSP_WRITE(mcbsp, SPCR1,
989 MCBSP_READ_CACHE(mcbsp, SPCR1) |
990 (RRST));
991 udelay(10);
992 dev_err(mcbsp->dev, "Could not read from"
993 " McBSP%d Register\n", mcbsp->id);
994 return -2;
995 }
996 }
997 }
998 *buf = MCBSP_READ(mcbsp, DRR1);
999
1000 return 0;
1001 }
1002 EXPORT_SYMBOL(omap_mcbsp_pollread);
1003
1004 /*
1005 * IRQ based word transmission.
1006 */
1007 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1008 {
1009 struct omap_mcbsp *mcbsp;
1010 omap_mcbsp_word_length word_length;
1011
1012 if (!omap_mcbsp_check_valid_id(id)) {
1013 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1014 return;
1015 }
1016
1017 mcbsp = id_to_mcbsp_ptr(id);
1018 word_length = mcbsp->tx_word_length;
1019
1020 wait_for_completion(&mcbsp->tx_irq_completion);
1021
1022 if (word_length > OMAP_MCBSP_WORD_16)
1023 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1024 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1025 }
1026 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1027
1028 u32 omap_mcbsp_recv_word(unsigned int id)
1029 {
1030 struct omap_mcbsp *mcbsp;
1031 u16 word_lsb, word_msb = 0;
1032 omap_mcbsp_word_length word_length;
1033
1034 if (!omap_mcbsp_check_valid_id(id)) {
1035 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1036 return -ENODEV;
1037 }
1038 mcbsp = id_to_mcbsp_ptr(id);
1039
1040 word_length = mcbsp->rx_word_length;
1041
1042 wait_for_completion(&mcbsp->rx_irq_completion);
1043
1044 if (word_length > OMAP_MCBSP_WORD_16)
1045 word_msb = MCBSP_READ(mcbsp, DRR2);
1046 word_lsb = MCBSP_READ(mcbsp, DRR1);
1047
1048 return (word_lsb | (word_msb << 16));
1049 }
1050 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1051
1052 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1053 {
1054 struct omap_mcbsp *mcbsp;
1055 omap_mcbsp_word_length tx_word_length;
1056 omap_mcbsp_word_length rx_word_length;
1057 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1058
1059 if (!omap_mcbsp_check_valid_id(id)) {
1060 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1061 return -ENODEV;
1062 }
1063 mcbsp = id_to_mcbsp_ptr(id);
1064 tx_word_length = mcbsp->tx_word_length;
1065 rx_word_length = mcbsp->rx_word_length;
1066
1067 if (tx_word_length != rx_word_length)
1068 return -EINVAL;
1069
1070 /* First we wait for the transmitter to be ready */
1071 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1072 while (!(spcr2 & XRDY)) {
1073 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1074 if (attempts++ > 1000) {
1075 /* We must reset the transmitter */
1076 MCBSP_WRITE(mcbsp, SPCR2,
1077 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1078 udelay(10);
1079 MCBSP_WRITE(mcbsp, SPCR2,
1080 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1081 udelay(10);
1082 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1083 "ready\n", mcbsp->id);
1084 return -EAGAIN;
1085 }
1086 }
1087
1088 /* Now we can push the data */
1089 if (tx_word_length > OMAP_MCBSP_WORD_16)
1090 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1091 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1092
1093 /* We wait for the receiver to be ready */
1094 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1095 while (!(spcr1 & RRDY)) {
1096 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1097 if (attempts++ > 1000) {
1098 /* We must reset the receiver */
1099 MCBSP_WRITE(mcbsp, SPCR1,
1100 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1101 udelay(10);
1102 MCBSP_WRITE(mcbsp, SPCR1,
1103 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1104 udelay(10);
1105 dev_err(mcbsp->dev, "McBSP%d receiver not "
1106 "ready\n", mcbsp->id);
1107 return -EAGAIN;
1108 }
1109 }
1110
1111 /* Receiver is ready, let's read the dummy data */
1112 if (rx_word_length > OMAP_MCBSP_WORD_16)
1113 word_msb = MCBSP_READ(mcbsp, DRR2);
1114 word_lsb = MCBSP_READ(mcbsp, DRR1);
1115
1116 return 0;
1117 }
1118 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1119
1120 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1121 {
1122 struct omap_mcbsp *mcbsp;
1123 u32 clock_word = 0;
1124 omap_mcbsp_word_length tx_word_length;
1125 omap_mcbsp_word_length rx_word_length;
1126 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1127
1128 if (!omap_mcbsp_check_valid_id(id)) {
1129 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1130 return -ENODEV;
1131 }
1132
1133 mcbsp = id_to_mcbsp_ptr(id);
1134
1135 tx_word_length = mcbsp->tx_word_length;
1136 rx_word_length = mcbsp->rx_word_length;
1137
1138 if (tx_word_length != rx_word_length)
1139 return -EINVAL;
1140
1141 /* First we wait for the transmitter to be ready */
1142 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1143 while (!(spcr2 & XRDY)) {
1144 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1145 if (attempts++ > 1000) {
1146 /* We must reset the transmitter */
1147 MCBSP_WRITE(mcbsp, SPCR2,
1148 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1149 udelay(10);
1150 MCBSP_WRITE(mcbsp, SPCR2,
1151 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1152 udelay(10);
1153 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1154 "ready\n", mcbsp->id);
1155 return -EAGAIN;
1156 }
1157 }
1158
1159 /* We first need to enable the bus clock */
1160 if (tx_word_length > OMAP_MCBSP_WORD_16)
1161 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1162 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1163
1164 /* We wait for the receiver to be ready */
1165 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1166 while (!(spcr1 & RRDY)) {
1167 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1168 if (attempts++ > 1000) {
1169 /* We must reset the receiver */
1170 MCBSP_WRITE(mcbsp, SPCR1,
1171 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1172 udelay(10);
1173 MCBSP_WRITE(mcbsp, SPCR1,
1174 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1175 udelay(10);
1176 dev_err(mcbsp->dev, "McBSP%d receiver not "
1177 "ready\n", mcbsp->id);
1178 return -EAGAIN;
1179 }
1180 }
1181
1182 /* Receiver is ready, there is something for us */
1183 if (rx_word_length > OMAP_MCBSP_WORD_16)
1184 word_msb = MCBSP_READ(mcbsp, DRR2);
1185 word_lsb = MCBSP_READ(mcbsp, DRR1);
1186
1187 word[0] = (word_lsb | (word_msb << 16));
1188
1189 return 0;
1190 }
1191 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1192
1193 /*
1194 * Simple DMA based buffer rx/tx routines.
1195 * Nothing fancy, just a single buffer tx/rx through DMA.
1196 * The DMA resources are released once the transfer is done.
1197 * For anything fancier, you should use your own customized DMA
1198 * routines and callbacks.
1199 */
1200 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1201 unsigned int length)
1202 {
1203 struct omap_mcbsp *mcbsp;
1204 int dma_tx_ch;
1205 int src_port = 0;
1206 int dest_port = 0;
1207 int sync_dev = 0;
1208
1209 if (!omap_mcbsp_check_valid_id(id)) {
1210 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1211 return -ENODEV;
1212 }
1213 mcbsp = id_to_mcbsp_ptr(id);
1214
1215 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1216 omap_mcbsp_tx_dma_callback,
1217 mcbsp,
1218 &dma_tx_ch)) {
1219 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1220 "McBSP%d TX. Trying IRQ based TX\n",
1221 mcbsp->id);
1222 return -EAGAIN;
1223 }
1224 mcbsp->dma_tx_lch = dma_tx_ch;
1225
1226 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1227 dma_tx_ch);
1228
1229 init_completion(&mcbsp->tx_dma_completion);
1230
1231 if (cpu_class_is_omap1()) {
1232 src_port = OMAP_DMA_PORT_TIPB;
1233 dest_port = OMAP_DMA_PORT_EMIFF;
1234 }
1235 if (cpu_class_is_omap2())
1236 sync_dev = mcbsp->dma_tx_sync;
1237
1238 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1239 OMAP_DMA_DATA_TYPE_S16,
1240 length >> 1, 1,
1241 OMAP_DMA_SYNC_ELEMENT,
1242 sync_dev, 0);
1243
1244 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1245 src_port,
1246 OMAP_DMA_AMODE_CONSTANT,
1247 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1248 0, 0);
1249
1250 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1251 dest_port,
1252 OMAP_DMA_AMODE_POST_INC,
1253 buffer,
1254 0, 0);
1255
1256 omap_start_dma(mcbsp->dma_tx_lch);
1257 wait_for_completion(&mcbsp->tx_dma_completion);
1258
1259 return 0;
1260 }
1261 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1262
1263 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1264 unsigned int length)
1265 {
1266 struct omap_mcbsp *mcbsp;
1267 int dma_rx_ch;
1268 int src_port = 0;
1269 int dest_port = 0;
1270 int sync_dev = 0;
1271
1272 if (!omap_mcbsp_check_valid_id(id)) {
1273 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1274 return -ENODEV;
1275 }
1276 mcbsp = id_to_mcbsp_ptr(id);
1277
1278 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1279 omap_mcbsp_rx_dma_callback,
1280 mcbsp,
1281 &dma_rx_ch)) {
1282 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1283 "McBSP%d RX. Trying IRQ based RX\n",
1284 mcbsp->id);
1285 return -EAGAIN;
1286 }
1287 mcbsp->dma_rx_lch = dma_rx_ch;
1288
1289 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1290 dma_rx_ch);
1291
1292 init_completion(&mcbsp->rx_dma_completion);
1293
1294 if (cpu_class_is_omap1()) {
1295 src_port = OMAP_DMA_PORT_TIPB;
1296 dest_port = OMAP_DMA_PORT_EMIFF;
1297 }
1298 if (cpu_class_is_omap2())
1299 sync_dev = mcbsp->dma_rx_sync;
1300
1301 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1302 OMAP_DMA_DATA_TYPE_S16,
1303 length >> 1, 1,
1304 OMAP_DMA_SYNC_ELEMENT,
1305 sync_dev, 0);
1306
1307 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1308 src_port,
1309 OMAP_DMA_AMODE_CONSTANT,
1310 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1311 0, 0);
1312
1313 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1314 dest_port,
1315 OMAP_DMA_AMODE_POST_INC,
1316 buffer,
1317 0, 0);
1318
1319 omap_start_dma(mcbsp->dma_rx_lch);
1320 wait_for_completion(&mcbsp->rx_dma_completion);
1321
1322 return 0;
1323 }
1324 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1325
1326 /*
1327 * SPI wrapper.
1328 * Since SPI setup is much simpler than the generic McBSP one,
1329 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1330 * Once this is done, you can call omap_mcbsp_start().
1331 */
1332 void omap_mcbsp_set_spi_mode(unsigned int id,
1333 const struct omap_mcbsp_spi_cfg *spi_cfg)
1334 {
1335 struct omap_mcbsp *mcbsp;
1336 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1337
1338 if (!omap_mcbsp_check_valid_id(id)) {
1339 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1340 return;
1341 }
1342 mcbsp = id_to_mcbsp_ptr(id);
1343
1344 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1345
1346 /* SPI has only one frame */
1347 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1348 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1349
1350 /* Clock stop mode */
1351 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1352 mcbsp_cfg.spcr1 |= (1 << 12);
1353 else
1354 mcbsp_cfg.spcr1 |= (3 << 11);
1355
1356 /* Set clock parities */
1357 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1358 mcbsp_cfg.pcr0 |= CLKRP;
1359 else
1360 mcbsp_cfg.pcr0 &= ~CLKRP;
1361
1362 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1363 mcbsp_cfg.pcr0 &= ~CLKXP;
1364 else
1365 mcbsp_cfg.pcr0 |= CLKXP;
1366
1367 /* Set SCLKME to 0 and CLKSM to 1 */
1368 mcbsp_cfg.pcr0 &= ~SCLKME;
1369 mcbsp_cfg.srgr2 |= CLKSM;
1370
1371 /* Set FSXP */
1372 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1373 mcbsp_cfg.pcr0 &= ~FSXP;
1374 else
1375 mcbsp_cfg.pcr0 |= FSXP;
1376
1377 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1378 mcbsp_cfg.pcr0 |= CLKXM;
1379 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1380 mcbsp_cfg.pcr0 |= FSXM;
1381 mcbsp_cfg.srgr2 &= ~FSGM;
1382 mcbsp_cfg.xcr2 |= XDATDLY(1);
1383 mcbsp_cfg.rcr2 |= RDATDLY(1);
1384 } else {
1385 mcbsp_cfg.pcr0 &= ~CLKXM;
1386 mcbsp_cfg.srgr1 |= CLKGDV(1);
1387 mcbsp_cfg.pcr0 &= ~FSXM;
1388 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1389 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1390 }
1391
1392 mcbsp_cfg.xcr2 &= ~XPHASE;
1393 mcbsp_cfg.rcr2 &= ~RPHASE;
1394
1395 omap_mcbsp_config(id, &mcbsp_cfg);
1396 }
1397 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1398
1399 #ifdef CONFIG_ARCH_OMAP3
1400 #define max_thres(m) (mcbsp->pdata->buffer_size)
1401 #define valid_threshold(m, val) ((val) <= max_thres(m))
1402 #define THRESHOLD_PROP_BUILDER(prop) \
1403 static ssize_t prop##_show(struct device *dev, \
1404 struct device_attribute *attr, char *buf) \
1405 { \
1406 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1407 \
1408 return sprintf(buf, "%u\n", mcbsp->prop); \
1409 } \
1410 \
1411 static ssize_t prop##_store(struct device *dev, \
1412 struct device_attribute *attr, \
1413 const char *buf, size_t size) \
1414 { \
1415 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1416 unsigned long val; \
1417 int status; \
1418 \
1419 status = strict_strtoul(buf, 0, &val); \
1420 if (status) \
1421 return status; \
1422 \
1423 if (!valid_threshold(mcbsp, val)) \
1424 return -EDOM; \
1425 \
1426 mcbsp->prop = val; \
1427 return size; \
1428 } \
1429 \
1430 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1431
1432 THRESHOLD_PROP_BUILDER(max_tx_thres);
1433 THRESHOLD_PROP_BUILDER(max_rx_thres);
1434
1435 static const char *dma_op_modes[] = {
1436 "element", "threshold", "frame",
1437 };
1438
1439 static ssize_t dma_op_mode_show(struct device *dev,
1440 struct device_attribute *attr, char *buf)
1441 {
1442 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1443 int dma_op_mode, i = 0;
1444 ssize_t len = 0;
1445 const char * const *s;
1446
1447 dma_op_mode = mcbsp->dma_op_mode;
1448
1449 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1450 if (dma_op_mode == i)
1451 len += sprintf(buf + len, "[%s] ", *s);
1452 else
1453 len += sprintf(buf + len, "%s ", *s);
1454 }
1455 len += sprintf(buf + len, "\n");
1456
1457 return len;
1458 }
1459
1460 static ssize_t dma_op_mode_store(struct device *dev,
1461 struct device_attribute *attr,
1462 const char *buf, size_t size)
1463 {
1464 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1465 const char * const *s;
1466 int i = 0;
1467
1468 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1469 if (sysfs_streq(buf, *s))
1470 break;
1471
1472 if (i == ARRAY_SIZE(dma_op_modes))
1473 return -EINVAL;
1474
1475 spin_lock_irq(&mcbsp->lock);
1476 if (!mcbsp->free) {
1477 size = -EBUSY;
1478 goto unlock;
1479 }
1480 mcbsp->dma_op_mode = i;
1481
1482 unlock:
1483 spin_unlock_irq(&mcbsp->lock);
1484
1485 return size;
1486 }
1487
1488 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1489
1490 static ssize_t st_taps_show(struct device *dev,
1491 struct device_attribute *attr, char *buf)
1492 {
1493 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1494 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1495 ssize_t status = 0;
1496 int i;
1497
1498 spin_lock_irq(&mcbsp->lock);
1499 for (i = 0; i < st_data->nr_taps; i++)
1500 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1501 st_data->taps[i]);
1502 if (i)
1503 status += sprintf(&buf[status], "\n");
1504 spin_unlock_irq(&mcbsp->lock);
1505
1506 return status;
1507 }
1508
1509 static ssize_t st_taps_store(struct device *dev,
1510 struct device_attribute *attr,
1511 const char *buf, size_t size)
1512 {
1513 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1514 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1515 int val, tmp, status, i = 0;
1516
1517 spin_lock_irq(&mcbsp->lock);
1518 memset(st_data->taps, 0, sizeof(st_data->taps));
1519 st_data->nr_taps = 0;
1520
1521 do {
1522 status = sscanf(buf, "%d%n", &val, &tmp);
1523 if (status < 0 || status == 0) {
1524 size = -EINVAL;
1525 goto out;
1526 }
1527 if (val < -32768 || val > 32767) {
1528 size = -EINVAL;
1529 goto out;
1530 }
1531 st_data->taps[i++] = val;
1532 buf += tmp;
1533 if (*buf != ',')
1534 break;
1535 buf++;
1536 } while (1);
1537
1538 st_data->nr_taps = i;
1539
1540 out:
1541 spin_unlock_irq(&mcbsp->lock);
1542
1543 return size;
1544 }
1545
1546 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1547
1548 static const struct attribute *additional_attrs[] = {
1549 &dev_attr_max_tx_thres.attr,
1550 &dev_attr_max_rx_thres.attr,
1551 &dev_attr_dma_op_mode.attr,
1552 NULL,
1553 };
1554
1555 static const struct attribute_group additional_attr_group = {
1556 .attrs = (struct attribute **)additional_attrs,
1557 };
1558
1559 static inline int __devinit omap_additional_add(struct device *dev)
1560 {
1561 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1562 }
1563
1564 static inline void __devexit omap_additional_remove(struct device *dev)
1565 {
1566 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1567 }
1568
1569 static const struct attribute *sidetone_attrs[] = {
1570 &dev_attr_st_taps.attr,
1571 NULL,
1572 };
1573
1574 static const struct attribute_group sidetone_attr_group = {
1575 .attrs = (struct attribute **)sidetone_attrs,
1576 };
1577
1578 int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1579 {
1580 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1581 struct omap_mcbsp_st_data *st_data;
1582 int err;
1583
1584 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1585 if (!st_data) {
1586 err = -ENOMEM;
1587 goto err1;
1588 }
1589
1590 st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1591 if (!st_data->io_base_st) {
1592 err = -ENOMEM;
1593 goto err2;
1594 }
1595
1596 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1597 if (err)
1598 goto err3;
1599
1600 mcbsp->st_data = st_data;
1601 return 0;
1602
1603 err3:
1604 iounmap(st_data->io_base_st);
1605 err2:
1606 kfree(st_data);
1607 err1:
1608 return err;
1609
1610 }
1611
1612 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1613 {
1614 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1615
1616 if (st_data) {
1617 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1618 iounmap(st_data->io_base_st);
1619 kfree(st_data);
1620 }
1621 }
1622
1623 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1624 {
1625 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1626 if (cpu_is_omap34xx()) {
1627 mcbsp->max_tx_thres = max_thres(mcbsp);
1628 mcbsp->max_rx_thres = max_thres(mcbsp);
1629 /*
1630 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1631 * for mcbsp2 instances.
1632 */
1633 if (omap_additional_add(mcbsp->dev))
1634 dev_warn(mcbsp->dev,
1635 "Unable to create additional controls\n");
1636
1637 if (mcbsp->id == 2 || mcbsp->id == 3)
1638 if (omap_st_add(mcbsp))
1639 dev_warn(mcbsp->dev,
1640 "Unable to create sidetone controls\n");
1641
1642 } else {
1643 mcbsp->max_tx_thres = -EINVAL;
1644 mcbsp->max_rx_thres = -EINVAL;
1645 }
1646 }
1647
1648 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1649 {
1650 if (cpu_is_omap34xx()) {
1651 omap_additional_remove(mcbsp->dev);
1652
1653 if (mcbsp->id == 2 || mcbsp->id == 3)
1654 omap_st_remove(mcbsp);
1655 }
1656 }
1657 #else
1658 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1659 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1660 #endif /* CONFIG_ARCH_OMAP3 */
1661
1662 /*
1663 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1664 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1665 */
1666 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1667 {
1668 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1669 struct omap_mcbsp *mcbsp;
1670 int id = pdev->id - 1;
1671 int ret = 0;
1672
1673 if (!pdata) {
1674 dev_err(&pdev->dev, "McBSP device initialized without"
1675 "platform data\n");
1676 ret = -EINVAL;
1677 goto exit;
1678 }
1679
1680 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1681
1682 if (id >= omap_mcbsp_count) {
1683 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1684 ret = -EINVAL;
1685 goto exit;
1686 }
1687
1688 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1689 if (!mcbsp) {
1690 ret = -ENOMEM;
1691 goto exit;
1692 }
1693
1694 spin_lock_init(&mcbsp->lock);
1695 mcbsp->id = id + 1;
1696 mcbsp->free = 1;
1697 mcbsp->dma_tx_lch = -1;
1698 mcbsp->dma_rx_lch = -1;
1699
1700 mcbsp->phys_base = pdata->phys_base;
1701 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1702 if (!mcbsp->io_base) {
1703 ret = -ENOMEM;
1704 goto err_ioremap;
1705 }
1706
1707 /* Default I/O is IRQ based */
1708 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1709 mcbsp->tx_irq = pdata->tx_irq;
1710 mcbsp->rx_irq = pdata->rx_irq;
1711 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1712 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1713
1714 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1715 if (IS_ERR(mcbsp->iclk)) {
1716 ret = PTR_ERR(mcbsp->iclk);
1717 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1718 goto err_iclk;
1719 }
1720
1721 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1722 if (IS_ERR(mcbsp->fclk)) {
1723 ret = PTR_ERR(mcbsp->fclk);
1724 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1725 goto err_fclk;
1726 }
1727
1728 mcbsp->pdata = pdata;
1729 mcbsp->dev = &pdev->dev;
1730 mcbsp_ptr[id] = mcbsp;
1731 platform_set_drvdata(pdev, mcbsp);
1732
1733 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1734 omap34xx_device_init(mcbsp);
1735
1736 return 0;
1737
1738 err_fclk:
1739 clk_put(mcbsp->iclk);
1740 err_iclk:
1741 iounmap(mcbsp->io_base);
1742 err_ioremap:
1743 kfree(mcbsp);
1744 exit:
1745 return ret;
1746 }
1747
1748 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1749 {
1750 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1751
1752 platform_set_drvdata(pdev, NULL);
1753 if (mcbsp) {
1754
1755 if (mcbsp->pdata && mcbsp->pdata->ops &&
1756 mcbsp->pdata->ops->free)
1757 mcbsp->pdata->ops->free(mcbsp->id);
1758
1759 omap34xx_device_exit(mcbsp);
1760
1761 clk_disable(mcbsp->fclk);
1762 clk_disable(mcbsp->iclk);
1763 clk_put(mcbsp->fclk);
1764 clk_put(mcbsp->iclk);
1765
1766 iounmap(mcbsp->io_base);
1767
1768 mcbsp->fclk = NULL;
1769 mcbsp->iclk = NULL;
1770 mcbsp->free = 0;
1771 mcbsp->dev = NULL;
1772 }
1773
1774 return 0;
1775 }
1776
1777 static struct platform_driver omap_mcbsp_driver = {
1778 .probe = omap_mcbsp_probe,
1779 .remove = __devexit_p(omap_mcbsp_remove),
1780 .driver = {
1781 .name = "omap-mcbsp",
1782 },
1783 };
1784
1785 int __init omap_mcbsp_init(void)
1786 {
1787 /* Register the McBSP driver */
1788 return platform_driver_register(&omap_mcbsp_driver);
1789 }
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