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1 /* linux/arch/arm/plat-s3c24xx/clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX Core clock control support
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/platform_device.h>
36 #include <linux/sysdev.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/clk.h>
40 #include <linux/mutex.h>
41 #include <linux/delay.h>
44 #include <mach/hardware.h>
47 #include <mach/regs-clock.h>
48 #include <mach/regs-gpio.h>
50 #include <plat/clock.h>
53 /* clock information */
55 static LIST_HEAD(clocks
);
57 DEFINE_MUTEX(clocks_mutex
);
59 /* enable and disable calls for use with the clk struct */
61 static int clk_null_enable(struct clk
*clk
, int enable
)
68 struct clk
*clk_get(struct device
*dev
, const char *id
)
71 struct clk
*clk
= ERR_PTR(-ENOENT
);
74 if (dev
== NULL
|| dev
->bus
!= &platform_bus_type
)
77 idno
= to_platform_device(dev
)->id
;
79 mutex_lock(&clocks_mutex
);
81 list_for_each_entry(p
, &clocks
, list
) {
83 strcmp(id
, p
->name
) == 0 &&
84 try_module_get(p
->owner
)) {
90 /* check for the case where a device was supplied, but the
91 * clock that was being searched for is not device specific */
94 list_for_each_entry(p
, &clocks
, list
) {
95 if (p
->id
== -1 && strcmp(id
, p
->name
) == 0 &&
96 try_module_get(p
->owner
)) {
103 mutex_unlock(&clocks_mutex
);
107 void clk_put(struct clk
*clk
)
109 module_put(clk
->owner
);
112 int clk_enable(struct clk
*clk
)
114 if (IS_ERR(clk
) || clk
== NULL
)
117 clk_enable(clk
->parent
);
119 mutex_lock(&clocks_mutex
);
121 if ((clk
->usage
++) == 0)
122 (clk
->enable
)(clk
, 1);
124 mutex_unlock(&clocks_mutex
);
128 void clk_disable(struct clk
*clk
)
130 if (IS_ERR(clk
) || clk
== NULL
)
133 mutex_lock(&clocks_mutex
);
135 if ((--clk
->usage
) == 0)
136 (clk
->enable
)(clk
, 0);
138 mutex_unlock(&clocks_mutex
);
139 clk_disable(clk
->parent
);
143 unsigned long clk_get_rate(struct clk
*clk
)
151 if (clk
->get_rate
!= NULL
)
152 return (clk
->get_rate
)(clk
);
154 if (clk
->parent
!= NULL
)
155 return clk_get_rate(clk
->parent
);
160 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
162 if (!IS_ERR(clk
) && clk
->round_rate
)
163 return (clk
->round_rate
)(clk
, rate
);
168 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
175 /* We do not default just do a clk->rate = rate as
176 * the clock may have been made this way by choice.
179 WARN_ON(clk
->set_rate
== NULL
);
181 if (clk
->set_rate
== NULL
)
184 mutex_lock(&clocks_mutex
);
185 ret
= (clk
->set_rate
)(clk
, rate
);
186 mutex_unlock(&clocks_mutex
);
191 struct clk
*clk_get_parent(struct clk
*clk
)
196 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
203 mutex_lock(&clocks_mutex
);
206 ret
= (clk
->set_parent
)(clk
, parent
);
208 mutex_unlock(&clocks_mutex
);
213 EXPORT_SYMBOL(clk_get
);
214 EXPORT_SYMBOL(clk_put
);
215 EXPORT_SYMBOL(clk_enable
);
216 EXPORT_SYMBOL(clk_disable
);
217 EXPORT_SYMBOL(clk_get_rate
);
218 EXPORT_SYMBOL(clk_round_rate
);
219 EXPORT_SYMBOL(clk_set_rate
);
220 EXPORT_SYMBOL(clk_get_parent
);
221 EXPORT_SYMBOL(clk_set_parent
);
225 static int clk_default_setrate(struct clk
*clk
, unsigned long rate
)
231 struct clk clk_xtal
= {
239 struct clk clk_mpll
= {
242 .set_rate
= clk_default_setrate
,
245 struct clk clk_upll
= {
258 .set_rate
= clk_default_setrate
,
267 .set_rate
= clk_default_setrate
,
276 .set_rate
= clk_default_setrate
,
279 struct clk clk_usb_bus
= {
288 struct clk s3c24xx_uclk
= {
293 /* initialise the clock system */
295 int s3c24xx_register_clock(struct clk
*clk
)
297 clk
->owner
= THIS_MODULE
;
299 if (clk
->enable
== NULL
)
300 clk
->enable
= clk_null_enable
;
302 /* add to the list of available clocks */
304 mutex_lock(&clocks_mutex
);
305 list_add(&clk
->list
, &clocks
);
306 mutex_unlock(&clocks_mutex
);
311 int s3c24xx_register_clocks(struct clk
**clks
, int nr_clks
)
315 for (; nr_clks
> 0; nr_clks
--, clks
++) {
316 if (s3c24xx_register_clock(*clks
) < 0)
323 /* initalise all the clocks */
325 int __init
s3c24xx_setup_clocks(unsigned long xtal
,
330 printk(KERN_INFO
"S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
332 /* initialise the main system clocks */
334 clk_xtal
.rate
= xtal
;
335 clk_upll
.rate
= s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON
), xtal
);
337 clk_mpll
.rate
= fclk
;
342 /* assume uart clocks are correctly setup */
344 /* register our clocks */
346 if (s3c24xx_register_clock(&clk_xtal
) < 0)
347 printk(KERN_ERR
"failed to register master xtal\n");
349 if (s3c24xx_register_clock(&clk_mpll
) < 0)
350 printk(KERN_ERR
"failed to register mpll clock\n");
352 if (s3c24xx_register_clock(&clk_upll
) < 0)
353 printk(KERN_ERR
"failed to register upll clock\n");
355 if (s3c24xx_register_clock(&clk_f
) < 0)
356 printk(KERN_ERR
"failed to register cpu fclk\n");
358 if (s3c24xx_register_clock(&clk_h
) < 0)
359 printk(KERN_ERR
"failed to register cpu hclk\n");
361 if (s3c24xx_register_clock(&clk_p
) < 0)
362 printk(KERN_ERR
"failed to register cpu pclk\n");