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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - arch/arm/plat-samsung/irq-vic-timer.c
1 /* arch/arm/plat-samsung/irq-vic-timer.c
2 * originally part of arch/arm/plat-s3c64xx/irq.c
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
9 * S3C64XX - Interrupt handling
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
22 #include <plat/irq-vic-timer.h>
23 #include <plat/regs-timer.h>
25 static void s3c_irq_demux_vic_timer(unsigned int irq
, struct irq_desc
*desc
)
27 generic_handle_irq((int)desc
->irq_data
.handler_data
);
30 /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
31 static void s3c_irq_timer_ack(struct irq_data
*d
)
33 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
34 u32 mask
= (1 << 5) << (d
->irq
- gc
->irq_base
);
36 irq_reg_writel(mask
| gc
->mask_cache
, gc
->reg_base
);
40 * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
41 * @num: Number of timers to initialize
42 * @timer_irq: Base IRQ number to be used for the timers.
44 * Register the necessary IRQ chaining and support for the timer IRQs
47 void __init
s3c_init_vic_timer_irq(unsigned int num
, unsigned int timer_irq
)
49 unsigned int pirq
[5] = { IRQ_TIMER0_VIC
, IRQ_TIMER1_VIC
, IRQ_TIMER2_VIC
,
50 IRQ_TIMER3_VIC
, IRQ_TIMER4_VIC
};
51 struct irq_chip_generic
*s3c_tgc
;
52 struct irq_chip_type
*ct
;
55 s3c_tgc
= irq_alloc_generic_chip("s3c-timer", 1, timer_irq
,
56 S3C64XX_TINT_CSTAT
, handle_level_irq
);
59 pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n",
64 ct
= s3c_tgc
->chip_types
;
65 ct
->chip
.irq_mask
= irq_gc_mask_clr_bit
;
66 ct
->chip
.irq_unmask
= irq_gc_mask_set_bit
;
67 ct
->chip
.irq_ack
= s3c_irq_timer_ack
;
68 irq_setup_generic_chip(s3c_tgc
, IRQ_MSK(num
), IRQ_GC_INIT_MASK_CACHE
,
69 IRQ_NOREQUEST
| IRQ_NOPROBE
, 0);
70 /* Clear the upper bits of the mask_cache*/
71 s3c_tgc
->mask_cache
&= 0x1f;
73 for (i
= 0; i
< num
; i
++, timer_irq
++) {
74 irq_set_chained_handler(pirq
[i
], s3c_irq_demux_vic_timer
);
75 irq_set_handler_data(pirq
[i
], (void *)timer_irq
);