arch/arm/vfp/vfphw.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  linux/arch/arm/vfp/vfphw.S
   4  *
   5  *  Copyright (C) 2004 ARM Limited.
   6  *  Written by Deep Blue Solutions Limited.
   7  *
   8  * This code is called from the kernel's undefined instruction trap.
   9  * r9 holds the return address for successful handling.
  10  * lr holds the return address for unrecognised instructions.
  11  * r10 points at the start of the private FP workspace in the thread structure
  12  * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
  13  */
  14 #include <linux/init.h>
  15 #include <linux/linkage.h>
  16 #include <asm/thread_info.h>
  17 #include <asm/vfpmacros.h>
  18 #include <linux/kern_levels.h>
  19 #include <asm/assembler.h>
  20 #include <asm/asm-offsets.h>
  21
  22         .macro  DBGSTR, str
  23 #ifdef DEBUG
  24         stmfd   sp!, {r0-r3, ip, lr}
  25         ldr     r0, =1f
  26         bl      printk
  27         ldmfd   sp!, {r0-r3, ip, lr}
  28
  29         .pushsection .rodata, "a"
  30 1:      .ascii  KERN_DEBUG "VFP: \str\n"
  31         .byte   0
  32         .previous
  33 #endif
  34         .endm
  35
  36         .macro  DBGSTR1, str, arg
  37 #ifdef DEBUG
  38         stmfd   sp!, {r0-r3, ip, lr}
  39         mov     r1, \arg
  40         ldr     r0, =1f
  41         bl      printk
  42         ldmfd   sp!, {r0-r3, ip, lr}
  43
  44         .pushsection .rodata, "a"
  45 1:      .ascii  KERN_DEBUG "VFP: \str\n"
  46         .byte   0
  47         .previous
  48 #endif
  49         .endm
  50
  51         .macro  DBGSTR3, str, arg1, arg2, arg3
  52 #ifdef DEBUG
  53         stmfd   sp!, {r0-r3, ip, lr}
  54         mov     r3, \arg3
  55         mov     r2, \arg2
  56         mov     r1, \arg1
  57         ldr     r0, =1f
  58         bl      printk
  59         ldmfd   sp!, {r0-r3, ip, lr}
  60
  61         .pushsection .rodata, "a"
  62 1:      .ascii  KERN_DEBUG "VFP: \str\n"
  63         .byte   0
  64         .previous
  65 #endif
  66         .endm
  67
  68
  69 @ VFP hardware support entry point.
  70 @
  71 @  r0  = instruction opcode (32-bit ARM or two 16-bit Thumb)
  72 @  r2  = PC value to resume execution after successful emulation
  73 @  r9  = normal "successful" return address
  74 @  r10 = vfp_state union
  75 @  r11 = CPU number
  76 @  lr  = unrecognised instruction return address
  77 @  IRQs enabled.
  78 ENTRY(vfp_support_entry)
  79         DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
  80
  81         ldr     r3, [sp, #S_PSR]        @ Neither lazy restore nor FP exceptions
  82         and     r3, r3, #MODE_MASK      @ are supported in kernel mode
  83         teq     r3, #USR_MODE
  84         bne     vfp_kmode_exception     @ Returns through lr
  85
  86         VFPFMRX r1, FPEXC               @ Is the VFP enabled?
  87         DBGSTR1 "fpexc %08x", r1
  88         tst     r1, #FPEXC_EN
  89         bne     look_for_VFP_exceptions @ VFP is already enabled
  90
  91         DBGSTR1 "enable %x", r10
  92         ldr     r3, vfp_current_hw_state_address
  93         orr     r1, r1, #FPEXC_EN       @ user FPEXC has the enable bit set
  94         ldr     r4, [r3, r11, lsl #2]   @ vfp_current_hw_state pointer
  95         bic     r5, r1, #FPEXC_EX       @ make sure exceptions are disabled
  96         cmp     r4, r10                 @ this thread owns the hw context?
  97 #ifndef CONFIG_SMP
  98         @ For UP, checking that this thread owns the hw context is
  99         @ sufficient to determine that the hardware state is valid.
 100         beq     vfp_hw_state_valid
 101
 102         @ On UP, we lazily save the VFP context.  As a different
 103         @ thread wants ownership of the VFP hardware, save the old
 104         @ state if there was a previous (valid) owner.
 105
 106         VFPFMXR FPEXC, r5               @ enable VFP, disable any pending
 107                                         @ exceptions, so we can get at the
 108                                         @ rest of it
 109
 110         DBGSTR1 "save old state %p", r4
 111         cmp     r4, #0                  @ if the vfp_current_hw_state is NULL
 112         beq     vfp_reload_hw           @ then the hw state needs reloading
 113         VFPFSTMIA r4, r5                @ save the working registers
 114         VFPFMRX r5, FPSCR               @ current status
 115 #ifndef CONFIG_CPU_FEROCEON
 116         tst     r1, #FPEXC_EX           @ is there additional state to save?
 117         beq     1f
 118         VFPFMRX r6, FPINST              @ FPINST (only if FPEXC.EX is set)
 119         tst     r1, #FPEXC_FP2V         @ is there an FPINST2 to read?
 120         beq     1f
 121         VFPFMRX r8, FPINST2             @ FPINST2 if needed (and present)
 122 1:
 123 #endif
 124         stmia   r4, {r1, r5, r6, r8}    @ save FPEXC, FPSCR, FPINST, FPINST2
 125 vfp_reload_hw:
 126
 127 #else
 128         @ For SMP, if this thread does not own the hw context, then we
 129         @ need to reload it.  No need to save the old state as on SMP,
 130         @ we always save the state when we switch away from a thread.
 131         bne     vfp_reload_hw
 132
 133         @ This thread has ownership of the current hardware context.
 134         @ However, it may have been migrated to another CPU, in which
 135         @ case the saved state is newer than the hardware context.
 136         @ Check this by looking at the CPU number which the state was
 137         @ last loaded onto.
 138         ldr     ip, [r10, #VFP_CPU]
 139         teq     ip, r11
 140         beq     vfp_hw_state_valid
 141
 142 vfp_reload_hw:
 143         @ We're loading this threads state into the VFP hardware. Update
 144         @ the CPU number which contains the most up to date VFP context.
 145         str     r11, [r10, #VFP_CPU]
 146
 147         VFPFMXR FPEXC, r5               @ enable VFP, disable any pending
 148                                         @ exceptions, so we can get at the
 149                                         @ rest of it
 150 #endif
 151
 152         DBGSTR1 "load state %p", r10
 153         str     r10, [r3, r11, lsl #2]  @ update the vfp_current_hw_state pointer
 154                                         @ Load the saved state back into the VFP
 155         VFPFLDMIA r10, r5               @ reload the working registers while
 156                                         @ FPEXC is in a safe state
 157         ldmia   r10, {r1, r5, r6, r8}   @ load FPEXC, FPSCR, FPINST, FPINST2
 158 #ifndef CONFIG_CPU_FEROCEON
 159         tst     r1, #FPEXC_EX           @ is there additional state to restore?
 160         beq     1f
 161         VFPFMXR FPINST, r6              @ restore FPINST (only if FPEXC.EX is set)
 162         tst     r1, #FPEXC_FP2V         @ is there an FPINST2 to write?
 163         beq     1f
 164         VFPFMXR FPINST2, r8             @ FPINST2 if needed (and present)
 165 1:
 166 #endif
 167         VFPFMXR FPSCR, r5               @ restore status
 168
 169 @ The context stored in the VFP hardware is up to date with this thread
 170 vfp_hw_state_valid:
 171         tst     r1, #FPEXC_EX
 172         bne     process_exception       @ might as well handle the pending
 173                                         @ exception before retrying branch
 174                                         @ out before setting an FPEXC that
 175                                         @ stops us reading stuff
 176         VFPFMXR FPEXC, r1               @ Restore FPEXC last
 177         sub     r2, r2, #4              @ Retry current instruction - if Thumb
 178         str     r2, [sp, #S_PC]         @ mode it's two 16-bit instructions,
 179                                         @ else it's one 32-bit instruction, so
 180                                         @ always subtract 4 from the following
 181                                         @ instruction address.
 182         dec_preempt_count_ti r10, r4
 183         ret     r9                      @ we think we have handled things
 184
 185
 186 look_for_VFP_exceptions:
 187         @ Check for synchronous or asynchronous exception
 188         tst     r1, #FPEXC_EX | FPEXC_DEX
 189         bne     process_exception
 190         @ On some implementations of the VFP subarch 1, setting FPSCR.IXE
 191         @ causes all the CDP instructions to be bounced synchronously without
 192         @ setting the FPEXC.EX bit
 193         VFPFMRX r5, FPSCR
 194         tst     r5, #FPSCR_IXE
 195         bne     process_exception
 196
 197         tst     r5, #FPSCR_LENGTH_MASK
 198         beq     skip
 199         orr     r1, r1, #FPEXC_DEX
 200         b       process_exception
 201 skip:
 202
 203         @ Fall into hand on to next handler - appropriate coproc instr
 204         @ not recognised by VFP
 205
 206         DBGSTR  "not VFP"
 207         dec_preempt_count_ti r10, r4
 208         ret     lr
 209
 210 process_exception:
 211         DBGSTR  "bounce"
 212         mov     r2, sp                  @ nothing stacked - regdump is at TOS
 213         mov     lr, r9                  @ setup for a return to the user code.
 214
 215         @ Now call the C code to package up the bounce to the support code
 216         @   r0 holds the trigger instruction
 217         @   r1 holds the FPEXC value
 218         @   r2 pointer to register dump
 219         b       VFP_bounce              @ we have handled this - the support
 220                                         @ code will raise an exception if
 221                                         @ required. If not, the user code will
 222                                         @ retry the faulted instruction
 223 ENDPROC(vfp_support_entry)
 224
 225 ENTRY(vfp_save_state)
 226         @ Save the current VFP state
 227         @ r0 - save location
 228         @ r1 - FPEXC
 229         DBGSTR1 "save VFP state %p", r0
 230         VFPFSTMIA r0, r2                @ save the working registers
 231         VFPFMRX r2, FPSCR               @ current status
 232         tst     r1, #FPEXC_EX           @ is there additional state to save?
 233         beq     1f
 234         VFPFMRX r3, FPINST              @ FPINST (only if FPEXC.EX is set)
 235         tst     r1, #FPEXC_FP2V         @ is there an FPINST2 to read?
 236         beq     1f
 237         VFPFMRX r12, FPINST2            @ FPINST2 if needed (and present)
 238 1:
 239         stmia   r0, {r1, r2, r3, r12}   @ save FPEXC, FPSCR, FPINST, FPINST2
 240         ret     lr
 241 ENDPROC(vfp_save_state)
 242
 243         .align
 244 vfp_current_hw_state_address:
 245         .word   vfp_current_hw_state
 246
 247         .macro  tbl_branch, base, tmp, shift
 248 #ifdef CONFIG_THUMB2_KERNEL
 249         adr     \tmp, 1f
 250         add     \tmp, \tmp, \base, lsl \shift
 251         ret     \tmp
 252 #else
 253         add     pc, pc, \base, lsl \shift
 254         mov     r0, r0
 255 #endif
 256 1:
 257         .endm
 258
 259 ENTRY(vfp_get_float)
 260         tbl_branch r0, r3, #3
 261         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
 262 1:      mrc     p10, 0, r0, c\dr, c0, 0 @ fmrs  r0, s0
 263         ret     lr
 264         .org    1b + 8
 265 1:      mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
 266         ret     lr
 267         .org    1b + 8
 268         .endr
 269 ENDPROC(vfp_get_float)
 270
 271 ENTRY(vfp_put_float)
 272         tbl_branch r1, r3, #3
 273         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
 274 1:      mcr     p10, 0, r0, c\dr, c0, 0 @ fmsr  r0, s0
 275         ret     lr
 276         .org    1b + 8
 277 1:      mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
 278         ret     lr
 279         .org    1b + 8
 280         .endr
 281 ENDPROC(vfp_put_float)
 282
 283 ENTRY(vfp_get_double)
 284         tbl_branch r0, r3, #3
 285         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
 286 1:      fmrrd   r0, r1, d\dr
 287         ret     lr
 288         .org    1b + 8
 289         .endr
 290 #ifdef CONFIG_VFPv3
 291         @ d16 - d31 registers
 292         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
 293 1:      mrrc    p11, 3, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
 294         ret     lr
 295         .org    1b + 8
 296         .endr
 297 #endif
 298
 299         @ virtual register 16 (or 32 if VFPv3) for compare with zero
 300         mov     r0, #0
 301         mov     r1, #0
 302         ret     lr
 303 ENDPROC(vfp_get_double)
 304
 305 ENTRY(vfp_put_double)
 306         tbl_branch r2, r3, #3
 307         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
 308 1:      fmdrr   d\dr, r0, r1
 309         ret     lr
 310         .org    1b + 8
 311         .endr
 312 #ifdef CONFIG_VFPv3
 313         @ d16 - d31 registers
 314         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
 315 1:      mcrr    p11, 3, r0, r1, c\dr    @ fmdrr r0, r1, d\dr
 316         ret     lr
 317         .org    1b + 8
 318         .endr
 319 #endif
 320 ENDPROC(vfp_put_double)